ls1043aqds.h 12 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright 2015 Freescale Semiconductor, Inc.
  4. */
  5. #ifndef __LS1043AQDS_H__
  6. #define __LS1043AQDS_H__
  7. #include "ls1043a_common.h"
  8. #ifndef __ASSEMBLY__
  9. unsigned long get_board_sys_clk(void);
  10. #endif
  11. #define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
  12. #define CONFIG_LAYERSCAPE_NS_ACCESS
  13. #define CONFIG_DIMM_SLOTS_PER_CTLR 1
  14. /* Physical Memory Map */
  15. #define CONFIG_CHIP_SELECTS_PER_CTRL 4
  16. #define SPD_EEPROM_ADDRESS 0x51
  17. #define CONFIG_SYS_SPD_BUS_NUM 0
  18. #ifdef CONFIG_DDR_ECC
  19. #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
  20. #endif
  21. #ifdef CONFIG_SYS_DPAA_FMAN
  22. #define RGMII_PHY1_ADDR 0x1
  23. #define RGMII_PHY2_ADDR 0x2
  24. #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
  25. #define SGMII_CARD_PORT2_PHY_ADDR 0x1D
  26. #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
  27. #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
  28. /* PHY address on QSGMII riser card on slot 1 */
  29. #define QSGMII_CARD_PORT1_PHY_ADDR_S1 0x4
  30. #define QSGMII_CARD_PORT2_PHY_ADDR_S1 0x5
  31. #define QSGMII_CARD_PORT3_PHY_ADDR_S1 0x6
  32. #define QSGMII_CARD_PORT4_PHY_ADDR_S1 0x7
  33. /* PHY address on QSGMII riser card on slot 2 */
  34. #define QSGMII_CARD_PORT1_PHY_ADDR_S2 0x8
  35. #define QSGMII_CARD_PORT2_PHY_ADDR_S2 0x9
  36. #define QSGMII_CARD_PORT3_PHY_ADDR_S2 0xA
  37. #define QSGMII_CARD_PORT4_PHY_ADDR_S2 0xB
  38. #endif
  39. /* LPUART */
  40. #ifdef CONFIG_LPUART
  41. #define CONFIG_LPUART_32B_REG
  42. #endif
  43. /* SATA */
  44. #define CONFIG_SCSI_AHCI_PLAT
  45. /* EEPROM */
  46. #define CONFIG_SYS_I2C_EEPROM_NXID
  47. #define CONFIG_SYS_EEPROM_BUS_NUM 0
  48. #define CONFIG_SYS_SATA AHCI_BASE_ADDR
  49. #define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
  50. #define CONFIG_SYS_SCSI_MAX_LUN 1
  51. #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
  52. CONFIG_SYS_SCSI_MAX_LUN)
  53. /*
  54. * IFC Definitions
  55. */
  56. #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
  57. #define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
  58. #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
  59. CSPR_PORT_SIZE_16 | \
  60. CSPR_MSEL_NOR | \
  61. CSPR_V)
  62. #define CONFIG_SYS_NOR1_CSPR_EXT (0x0)
  63. #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
  64. + 0x8000000) | \
  65. CSPR_PORT_SIZE_16 | \
  66. CSPR_MSEL_NOR | \
  67. CSPR_V)
  68. #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024)
  69. #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
  70. CSOR_NOR_TRHZ_80)
  71. #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
  72. FTIM0_NOR_TEADC(0x5) | \
  73. FTIM0_NOR_TEAHC(0x5))
  74. #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
  75. FTIM1_NOR_TRAD_NOR(0x1a) | \
  76. FTIM1_NOR_TSEQRAD_NOR(0x13))
  77. #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
  78. FTIM2_NOR_TCH(0x4) | \
  79. FTIM2_NOR_TWPH(0xe) | \
  80. FTIM2_NOR_TWP(0x1c))
  81. #define CONFIG_SYS_NOR_FTIM3 0
  82. #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
  83. #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
  84. #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
  85. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
  86. #define CONFIG_SYS_FLASH_EMPTY_INFO
  87. #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS, \
  88. CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
  89. #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
  90. #define CONFIG_SYS_WRITE_SWAPPED_DATA
  91. /*
  92. * NAND Flash Definitions
  93. */
  94. #define CONFIG_SYS_NAND_BASE 0x7e800000
  95. #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
  96. #define CONFIG_SYS_NAND_CSPR_EXT (0x0)
  97. #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
  98. | CSPR_PORT_SIZE_8 \
  99. | CSPR_MSEL_NAND \
  100. | CSPR_V)
  101. #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
  102. #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
  103. | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
  104. | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
  105. | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \
  106. | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
  107. | CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \
  108. | CSOR_NAND_PB(64)) /* 64 Pages Per Block */
  109. #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \
  110. FTIM0_NAND_TWP(0x18) | \
  111. FTIM0_NAND_TWCHT(0x7) | \
  112. FTIM0_NAND_TWH(0xa))
  113. #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
  114. FTIM1_NAND_TWBE(0x39) | \
  115. FTIM1_NAND_TRR(0xe) | \
  116. FTIM1_NAND_TRP(0x18))
  117. #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \
  118. FTIM2_NAND_TREH(0xa) | \
  119. FTIM2_NAND_TWHRE(0x1e))
  120. #define CONFIG_SYS_NAND_FTIM3 0x0
  121. #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
  122. #define CONFIG_SYS_MAX_NAND_DEVICE 1
  123. #define CONFIG_MTD_NAND_VERIFY_WRITE
  124. #endif
  125. #ifdef CONFIG_NAND_BOOT
  126. #define CONFIG_SPL_PAD_TO 0x20000 /* block aligned */
  127. #define CONFIG_SYS_NAND_U_BOOT_SIZE (640 << 10)
  128. #endif
  129. #if defined(CONFIG_TFABOOT) || \
  130. defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
  131. #define CONFIG_QIXIS_I2C_ACCESS
  132. #endif
  133. /*
  134. * QIXIS Definitions
  135. */
  136. #define CONFIG_FSL_QIXIS
  137. #ifdef CONFIG_FSL_QIXIS
  138. #define QIXIS_BASE 0x7fb00000
  139. #define QIXIS_BASE_PHYS QIXIS_BASE
  140. #define CONFIG_SYS_I2C_FPGA_ADDR 0x66
  141. #define QIXIS_LBMAP_SWITCH 6
  142. #define QIXIS_LBMAP_MASK 0x0f
  143. #define QIXIS_LBMAP_SHIFT 0
  144. #define QIXIS_LBMAP_DFLTBANK 0x00
  145. #define QIXIS_LBMAP_ALTBANK 0x04
  146. #define QIXIS_LBMAP_NAND 0x09
  147. #define QIXIS_LBMAP_SD 0x00
  148. #define QIXIS_LBMAP_SD_QSPI 0xff
  149. #define QIXIS_LBMAP_QSPI 0xff
  150. #define QIXIS_RCW_SRC_NAND 0x106
  151. #define QIXIS_RCW_SRC_SD 0x040
  152. #define QIXIS_RCW_SRC_QSPI 0x045
  153. #define QIXIS_RST_CTL_RESET 0x41
  154. #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
  155. #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
  156. #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
  157. #define CONFIG_SYS_FPGA_CSPR_EXT (0x0)
  158. #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \
  159. CSPR_PORT_SIZE_8 | \
  160. CSPR_MSEL_GPCM | \
  161. CSPR_V)
  162. #define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024)
  163. #define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
  164. CSOR_NOR_NOR_MODE_AVD_NOR | \
  165. CSOR_NOR_TRHZ_80)
  166. /*
  167. * QIXIS Timing parameters for IFC GPCM
  168. */
  169. #define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xc) | \
  170. FTIM0_GPCM_TEADC(0x20) | \
  171. FTIM0_GPCM_TEAHC(0x10))
  172. #define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0x50) | \
  173. FTIM1_GPCM_TRAD(0x1f))
  174. #define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0x8) | \
  175. FTIM2_GPCM_TCH(0x8) | \
  176. FTIM2_GPCM_TWP(0xf0))
  177. #define CONFIG_SYS_FPGA_FTIM3 0x0
  178. #endif
  179. #ifdef CONFIG_TFABOOT
  180. #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
  181. #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
  182. #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
  183. #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
  184. #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
  185. #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
  186. #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
  187. #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
  188. #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
  189. #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
  190. #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
  191. #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
  192. #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
  193. #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
  194. #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
  195. #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
  196. #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
  197. #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
  198. #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
  199. #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
  200. #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
  201. #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
  202. #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
  203. #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
  204. #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
  205. #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
  206. #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
  207. #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
  208. #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0
  209. #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1
  210. #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2
  211. #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3
  212. #else
  213. #ifdef CONFIG_NAND_BOOT
  214. #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
  215. #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
  216. #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
  217. #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
  218. #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
  219. #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
  220. #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
  221. #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
  222. #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
  223. #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
  224. #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
  225. #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
  226. #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
  227. #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
  228. #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
  229. #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
  230. #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT
  231. #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR
  232. #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
  233. #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
  234. #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
  235. #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
  236. #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
  237. #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
  238. #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
  239. #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
  240. #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
  241. #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
  242. #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0
  243. #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1
  244. #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2
  245. #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3
  246. #else
  247. #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
  248. #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
  249. #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
  250. #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
  251. #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
  252. #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
  253. #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
  254. #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
  255. #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
  256. #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
  257. #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
  258. #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
  259. #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
  260. #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
  261. #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
  262. #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
  263. #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
  264. #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
  265. #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
  266. #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
  267. #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
  268. #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
  269. #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
  270. #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
  271. #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
  272. #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
  273. #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
  274. #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
  275. #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0
  276. #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1
  277. #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2
  278. #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3
  279. #endif
  280. #endif
  281. /*
  282. * I2C bus multiplexer
  283. */
  284. #define I2C_MUX_PCA_ADDR_PRI 0x77
  285. #define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */
  286. #define I2C_RETIMER_ADDR 0x18
  287. #define I2C_MUX_CH_DEFAULT 0x8
  288. #define I2C_MUX_CH_CH7301 0xC
  289. #define I2C_MUX_CH5 0xD
  290. #define I2C_MUX_CH7 0xF
  291. #define I2C_MUX_CH_VOL_MONITOR 0xa
  292. /* Voltage monitor on channel 2*/
  293. #define I2C_VOL_MONITOR_ADDR 0x40
  294. #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
  295. #define I2C_VOL_MONITOR_BUS_V_OVF 0x1
  296. #define I2C_VOL_MONITOR_BUS_V_SHIFT 3
  297. #define CONFIG_VID_FLS_ENV "ls1043aqds_vdd_mv"
  298. #ifndef CONFIG_SPL_BUILD
  299. #define CONFIG_VID
  300. #endif
  301. #define CONFIG_VOL_MONITOR_IR36021_SET
  302. #define CONFIG_VOL_MONITOR_INA220
  303. /* The lowest and highest voltage allowed for LS1043AQDS */
  304. #define VDD_MV_MIN 819
  305. #define VDD_MV_MAX 1212
  306. /*
  307. * Miscellaneous configurable options
  308. */
  309. #define CONFIG_SYS_HZ 1000
  310. #define CONFIG_SYS_INIT_SP_OFFSET \
  311. (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  312. #ifdef CONFIG_SPL_BUILD
  313. #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
  314. #else
  315. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
  316. #endif
  317. /*
  318. * Environment
  319. */
  320. #include <asm/fsl_secure_boot.h>
  321. #endif /* __LS1043AQDS_H__ */