ls1021aqds.h 13 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright 2014 Freescale Semiconductor, Inc.
  4. * Copyright 2019 NXP
  5. */
  6. #ifndef __CONFIG_H
  7. #define __CONFIG_H
  8. #define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR
  9. #define CONFIG_SYS_FSL_CLK
  10. #define CONFIG_DEEP_SLEEP
  11. #define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR
  12. #define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE
  13. #ifndef __ASSEMBLY__
  14. unsigned long get_board_sys_clk(void);
  15. #endif
  16. #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
  17. #define CONFIG_SYS_CLK_FREQ 100000000
  18. #define CONFIG_QIXIS_I2C_ACCESS
  19. #else
  20. #define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
  21. #endif
  22. #ifdef CONFIG_SD_BOOT
  23. #define CONFIG_SPL_MAX_SIZE 0x1a000
  24. #define CONFIG_SPL_STACK 0x1001d000
  25. #define CONFIG_SPL_PAD_TO 0x1c000
  26. #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE + \
  27. CONFIG_SYS_MONITOR_LEN)
  28. #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
  29. #define CONFIG_SPL_BSS_START_ADDR 0x80100000
  30. #define CONFIG_SPL_BSS_MAX_SIZE 0x80000
  31. #define CONFIG_SYS_MONITOR_LEN 0xc0000
  32. #endif
  33. #ifdef CONFIG_NAND_BOOT
  34. #define CONFIG_SPL_MAX_SIZE 0x1a000
  35. #define CONFIG_SPL_STACK 0x1001d000
  36. #define CONFIG_SPL_PAD_TO 0x1c000
  37. #define CONFIG_SYS_NAND_U_BOOT_SIZE (400 << 10)
  38. #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
  39. #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
  40. #define CONFIG_SYS_SPL_MALLOC_START 0x80200000
  41. #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
  42. #define CONFIG_SPL_BSS_START_ADDR 0x80100000
  43. #define CONFIG_SPL_BSS_MAX_SIZE 0x80000
  44. #define CONFIG_SYS_MONITOR_LEN 0x80000
  45. #endif
  46. #define SPD_EEPROM_ADDRESS 0x51
  47. #define CONFIG_SYS_SPD_BUS_NUM 0
  48. #ifndef CONFIG_SYS_FSL_DDR4
  49. #define CONFIG_SYS_DDR_RAW_TIMING
  50. #endif
  51. #define CONFIG_DIMM_SLOTS_PER_CTLR 1
  52. #define CONFIG_CHIP_SELECTS_PER_CTRL 4
  53. #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
  54. #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
  55. #ifdef CONFIG_DDR_ECC
  56. #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
  57. #endif
  58. /*
  59. * IFC Definitions
  60. */
  61. #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
  62. #define CONFIG_FSL_IFC
  63. #define CONFIG_SYS_FLASH_BASE 0x60000000
  64. #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
  65. #define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
  66. #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
  67. CSPR_PORT_SIZE_16 | \
  68. CSPR_MSEL_NOR | \
  69. CSPR_V)
  70. #define CONFIG_SYS_NOR1_CSPR_EXT (0x0)
  71. #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
  72. + 0x8000000) | \
  73. CSPR_PORT_SIZE_16 | \
  74. CSPR_MSEL_NOR | \
  75. CSPR_V)
  76. #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024)
  77. #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
  78. CSOR_NOR_TRHZ_80)
  79. #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
  80. FTIM0_NOR_TEADC(0x5) | \
  81. FTIM0_NOR_TEAHC(0x5))
  82. #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
  83. FTIM1_NOR_TRAD_NOR(0x1a) | \
  84. FTIM1_NOR_TSEQRAD_NOR(0x13))
  85. #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
  86. FTIM2_NOR_TCH(0x4) | \
  87. FTIM2_NOR_TWPH(0xe) | \
  88. FTIM2_NOR_TWP(0x1c))
  89. #define CONFIG_SYS_NOR_FTIM3 0
  90. #define CONFIG_SYS_FLASH_QUIET_TEST
  91. #define CONFIG_FLASH_SHOW_PROGRESS 45
  92. #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
  93. #define CONFIG_SYS_WRITE_SWAPPED_DATA
  94. #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
  95. #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
  96. #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
  97. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
  98. #define CONFIG_SYS_FLASH_EMPTY_INFO
  99. #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS, \
  100. CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
  101. /*
  102. * NAND Flash Definitions
  103. */
  104. #define CONFIG_SYS_NAND_BASE 0x7e800000
  105. #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
  106. #define CONFIG_SYS_NAND_CSPR_EXT (0x0)
  107. #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
  108. | CSPR_PORT_SIZE_8 \
  109. | CSPR_MSEL_NAND \
  110. | CSPR_V)
  111. #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
  112. #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
  113. | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
  114. | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
  115. | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \
  116. | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
  117. | CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \
  118. | CSOR_NAND_PB(64)) /* 64 Pages Per Block */
  119. #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \
  120. FTIM0_NAND_TWP(0x18) | \
  121. FTIM0_NAND_TWCHT(0x7) | \
  122. FTIM0_NAND_TWH(0xa))
  123. #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
  124. FTIM1_NAND_TWBE(0x39) | \
  125. FTIM1_NAND_TRR(0xe) | \
  126. FTIM1_NAND_TRP(0x18))
  127. #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \
  128. FTIM2_NAND_TREH(0xa) | \
  129. FTIM2_NAND_TWHRE(0x1e))
  130. #define CONFIG_SYS_NAND_FTIM3 0x0
  131. #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
  132. #define CONFIG_SYS_MAX_NAND_DEVICE 1
  133. #endif
  134. /*
  135. * QIXIS Definitions
  136. */
  137. #define CONFIG_FSL_QIXIS
  138. #ifdef CONFIG_FSL_QIXIS
  139. #define QIXIS_BASE 0x7fb00000
  140. #define QIXIS_BASE_PHYS QIXIS_BASE
  141. #define CONFIG_SYS_I2C_FPGA_ADDR 0x66
  142. #define QIXIS_LBMAP_SWITCH 6
  143. #define QIXIS_LBMAP_MASK 0x0f
  144. #define QIXIS_LBMAP_SHIFT 0
  145. #define QIXIS_LBMAP_DFLTBANK 0x00
  146. #define QIXIS_LBMAP_ALTBANK 0x04
  147. #define QIXIS_PWR_CTL 0x21
  148. #define QIXIS_PWR_CTL_POWEROFF 0x80
  149. #define QIXIS_RST_CTL_RESET 0x44
  150. #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
  151. #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
  152. #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
  153. #define QIXIS_CTL_SYS 0x5
  154. #define QIXIS_CTL_SYS_EVTSW_MASK 0x0c
  155. #define QIXIS_CTL_SYS_EVTSW_IRQ 0x04
  156. #define QIXIS_RST_FORCE_3 0x45
  157. #define QIXIS_RST_FORCE_3_PCIESLOT1 0x80
  158. #define QIXIS_PWR_CTL2 0x21
  159. #define QIXIS_PWR_CTL2_PCTL 0x2
  160. #define CONFIG_SYS_FPGA_CSPR_EXT (0x0)
  161. #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \
  162. CSPR_PORT_SIZE_8 | \
  163. CSPR_MSEL_GPCM | \
  164. CSPR_V)
  165. #define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024)
  166. #define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
  167. CSOR_NOR_NOR_MODE_AVD_NOR | \
  168. CSOR_NOR_TRHZ_80)
  169. /*
  170. * QIXIS Timing parameters for IFC GPCM
  171. */
  172. #define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xe) | \
  173. FTIM0_GPCM_TEADC(0xe) | \
  174. FTIM0_GPCM_TEAHC(0xe))
  175. #define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0xe) | \
  176. FTIM1_GPCM_TRAD(0x1f))
  177. #define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0xe) | \
  178. FTIM2_GPCM_TCH(0xe) | \
  179. FTIM2_GPCM_TWP(0xf0))
  180. #define CONFIG_SYS_FPGA_FTIM3 0x0
  181. #endif
  182. #if defined(CONFIG_NAND_BOOT)
  183. #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
  184. #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
  185. #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
  186. #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
  187. #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
  188. #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
  189. #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
  190. #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
  191. #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
  192. #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
  193. #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
  194. #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
  195. #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
  196. #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
  197. #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
  198. #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
  199. #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT
  200. #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR
  201. #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
  202. #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
  203. #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
  204. #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
  205. #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
  206. #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
  207. #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
  208. #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
  209. #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
  210. #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
  211. #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0
  212. #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1
  213. #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2
  214. #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3
  215. #else
  216. #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
  217. #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
  218. #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
  219. #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
  220. #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
  221. #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
  222. #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
  223. #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
  224. #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
  225. #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
  226. #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
  227. #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
  228. #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
  229. #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
  230. #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
  231. #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
  232. #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
  233. #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
  234. #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
  235. #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
  236. #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
  237. #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
  238. #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
  239. #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
  240. #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
  241. #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
  242. #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
  243. #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
  244. #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0
  245. #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1
  246. #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2
  247. #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3
  248. #endif
  249. /*
  250. * Serial Port
  251. */
  252. #ifdef CONFIG_LPUART
  253. #define CONFIG_LPUART_32B_REG
  254. #else
  255. #define CONFIG_SYS_NS16550_SERIAL
  256. #ifndef CONFIG_DM_SERIAL
  257. #define CONFIG_SYS_NS16550_REG_SIZE 1
  258. #endif
  259. #define CONFIG_SYS_NS16550_CLK get_serial_clock()
  260. #endif
  261. /*
  262. * I2C
  263. */
  264. /* GPIO */
  265. #ifdef CONFIG_DM_GPIO
  266. #ifndef CONFIG_MPC8XXX_GPIO
  267. #define CONFIG_MPC8XXX_GPIO
  268. #endif
  269. #endif
  270. /* EEPROM */
  271. #define CONFIG_SYS_I2C_EEPROM_NXID
  272. #define CONFIG_SYS_EEPROM_BUS_NUM 0
  273. /*
  274. * I2C bus multiplexer
  275. */
  276. #define I2C_MUX_PCA_ADDR_PRI 0x77
  277. #define I2C_MUX_CH_DEFAULT 0x8
  278. #define I2C_MUX_CH_CH7301 0xC
  279. /*
  280. * MMC
  281. */
  282. /*
  283. * Video
  284. */
  285. #ifdef CONFIG_VIDEO_FSL_DCU_FB
  286. #define CONFIG_VIDEO_LOGO
  287. #define CONFIG_VIDEO_BMP_LOGO
  288. #define CONFIG_FSL_DIU_CH7301
  289. #define CONFIG_SYS_I2C_DVI_BUS_NUM 0
  290. #define CONFIG_SYS_I2C_QIXIS_ADDR 0x66
  291. #define CONFIG_SYS_I2C_DVI_ADDR 0x75
  292. #endif
  293. /*
  294. * eTSEC
  295. */
  296. #ifdef CONFIG_TSEC_ENET
  297. #define CONFIG_MII_DEFAULT_TSEC 3
  298. #define CONFIG_TSEC1 1
  299. #define CONFIG_TSEC1_NAME "eTSEC1"
  300. #define CONFIG_TSEC2 1
  301. #define CONFIG_TSEC2_NAME "eTSEC2"
  302. #define CONFIG_TSEC3 1
  303. #define CONFIG_TSEC3_NAME "eTSEC3"
  304. #define TSEC1_PHY_ADDR 1
  305. #define TSEC2_PHY_ADDR 2
  306. #define TSEC3_PHY_ADDR 3
  307. #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
  308. #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
  309. #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
  310. #define TSEC1_PHYIDX 0
  311. #define TSEC2_PHYIDX 0
  312. #define TSEC3_PHYIDX 0
  313. #define CONFIG_ETHPRIME "eTSEC1"
  314. #define CONFIG_HAS_ETH0
  315. #define CONFIG_HAS_ETH1
  316. #define CONFIG_HAS_ETH2
  317. #define CONFIG_FSL_SGMII_RISER 1
  318. #define SGMII_RISER_PHY_OFFSET 0x1b
  319. #ifdef CONFIG_FSL_SGMII_RISER
  320. #define CONFIG_SYS_TBIPA_VALUE 8
  321. #endif
  322. #endif
  323. /* PCIe */
  324. #define CONFIG_PCIE1 /* PCIE controller 1 */
  325. #define CONFIG_PCIE2 /* PCIE controller 2 */
  326. #ifdef CONFIG_PCI
  327. #define CONFIG_PCI_SCAN_SHOW
  328. #endif
  329. #define CONFIG_PEN_ADDR_BIG_ENDIAN
  330. #define CONFIG_LAYERSCAPE_NS_ACCESS
  331. #define CONFIG_SMP_PEN_ADDR 0x01ee0200
  332. #define COUNTER_FREQUENCY 12500000
  333. #define CONFIG_HWCONFIG
  334. #define HWCONFIG_BUFFER_SIZE 256
  335. #define CONFIG_FSL_DEVICE_DISABLE
  336. #define CONFIG_SYS_QE_FW_ADDR 0x60940000
  337. #ifdef CONFIG_LPUART
  338. #define CONFIG_EXTRA_ENV_SETTINGS \
  339. "bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0" \
  340. "initrd_high=0xffffffff\0" \
  341. "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0"
  342. #else
  343. #define CONFIG_EXTRA_ENV_SETTINGS \
  344. "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \
  345. "initrd_high=0xffffffff\0" \
  346. "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0"
  347. #endif
  348. /*
  349. * Miscellaneous configurable options
  350. */
  351. #define CONFIG_SYS_BOOTMAPSZ (256 << 20)
  352. #define CONFIG_LS102XA_STREAM_ID
  353. #define CONFIG_SYS_INIT_SP_OFFSET \
  354. (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  355. #define CONFIG_SYS_INIT_SP_ADDR \
  356. (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
  357. #ifdef CONFIG_SPL_BUILD
  358. #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
  359. #else
  360. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
  361. #endif
  362. /*
  363. * Environment
  364. */
  365. #include <asm/fsl_secure_boot.h>
  366. #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
  367. #endif