pfe_hw.h 4.8 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright 2015-2016 Freescale Semiconductor, Inc.
  4. * Copyright 2017 NXP
  5. */
  6. #ifndef _PFE_H_
  7. #define _PFE_H_
  8. #include <elf.h>
  9. #include <linux/bitops.h>
  10. #include "cbus.h"
  11. #define PFE_RESET_WA
  12. #define CLASS_DMEM_BASE_ADDR(i) (0x00000000 | ((i) << 20))
  13. /* Only valid for mem access register interface */
  14. #define CLASS_IMEM_BASE_ADDR(i) (0x00000000 | ((i) << 20))
  15. #define CLASS_DMEM_SIZE 0x00002000
  16. #define CLASS_IMEM_SIZE 0x00008000
  17. #define TMU_DMEM_BASE_ADDR(i) (0x00000000 + ((i) << 20))
  18. /* Only valid for mem access register interface */
  19. #define TMU_IMEM_BASE_ADDR(i) (0x00000000 + ((i) << 20))
  20. #define TMU_DMEM_SIZE 0x00000800
  21. #define TMU_IMEM_SIZE 0x00002000
  22. #define UTIL_DMEM_BASE_ADDR 0x00000000
  23. #define UTIL_DMEM_SIZE 0x00002000
  24. #define PE_LMEM_BASE_ADDR 0xc3010000
  25. #define PE_LMEM_SIZE 0x8000
  26. #define PE_LMEM_END (PE_LMEM_BASE_ADDR + PE_LMEM_SIZE)
  27. #define DMEM_BASE_ADDR 0x00000000
  28. #define DMEM_SIZE 0x2000 /* TMU has less... */
  29. #define DMEM_END (DMEM_BASE_ADDR + DMEM_SIZE)
  30. #define PMEM_BASE_ADDR 0x00010000
  31. #define PMEM_SIZE 0x8000 /* TMU has less... */
  32. #define PMEM_END (PMEM_BASE_ADDR + PMEM_SIZE)
  33. /* Memory ranges check from PE point of view/memory map */
  34. #define IS_DMEM(addr, len) (((unsigned long)(addr) >= DMEM_BASE_ADDR) &&\
  35. (((unsigned long)(addr) +\
  36. (len)) <= DMEM_END))
  37. #define IS_PMEM(addr, len) (((unsigned long)(addr) >= PMEM_BASE_ADDR) &&\
  38. (((unsigned long)(addr) +\
  39. (len)) <= PMEM_END))
  40. #define IS_PE_LMEM(addr, len) (((unsigned long)(addr) >= PE_LMEM_BASE_ADDR\
  41. ) && (((unsigned long)(addr)\
  42. + (len)) <= PE_LMEM_END))
  43. #define IS_PFE_LMEM(addr, len) (((unsigned long)(addr) >=\
  44. CBUS_VIRT_TO_PFE(LMEM_BASE_ADDR)) &&\
  45. (((unsigned long)(addr) + (len)) <=\
  46. CBUS_VIRT_TO_PFE(LMEM_END)))
  47. #define IS_PHYS_DDR(addr, len) (((unsigned long)(addr) >=\
  48. PFE_DDR_PHYS_BASE_ADDR) &&\
  49. (((unsigned long)(addr) + (len)) <=\
  50. PFE_DDR_PHYS_END))
  51. /* Host View Address */
  52. extern void *ddr_pfe_base_addr;
  53. /* PFE View Address */
  54. /* DDR physical base address as seen by PE's. */
  55. #define PFE_DDR_PHYS_BASE_ADDR 0x03800000
  56. #define PFE_DDR_PHYS_SIZE 0xC000000
  57. #define PFE_DDR_PHYS_END (PFE_DDR_PHYS_BASE_ADDR + PFE_DDR_PHYS_SIZE)
  58. /* CBUS physical base address as seen by PE's. */
  59. #define PFE_CBUS_PHYS_BASE_ADDR 0xc0000000
  60. /* Host<->PFE Mapping */
  61. #define DDR_PFE_TO_VIRT(p) ((unsigned long int)((p) + 0x80000000))
  62. #define CBUS_VIRT_TO_PFE(v) (((v) - CBUS_BASE_ADDR) +\
  63. PFE_CBUS_PHYS_BASE_ADDR)
  64. #define CBUS_PFE_TO_VIRT(p) (((p) - PFE_CBUS_PHYS_BASE_ADDR) +\
  65. CBUS_BASE_ADDR)
  66. enum {
  67. CLASS0_ID = 0,
  68. CLASS1_ID,
  69. CLASS2_ID,
  70. CLASS3_ID,
  71. CLASS4_ID,
  72. CLASS5_ID,
  73. TMU0_ID,
  74. TMU1_ID,
  75. TMU2_ID,
  76. TMU3_ID,
  77. MAX_PE
  78. };
  79. #define CLASS_MASK (BIT(CLASS0_ID) | BIT(CLASS1_ID) | BIT(CLASS2_ID)\
  80. | BIT(CLASS3_ID) | BIT(CLASS4_ID) |\
  81. BIT(CLASS5_ID))
  82. #define CLASS_MAX_ID CLASS5_ID
  83. #define TMU_MASK (BIT(TMU0_ID) | BIT(TMU1_ID) | BIT(TMU3_ID))
  84. #define TMU_MAX_ID TMU3_ID
  85. /*
  86. * PE information.
  87. * Structure containing PE's specific information. It is used to create
  88. * generic C functions common to all PEs.
  89. * Before using the library functions this structure needs to be
  90. * initialized with the different registers virtual addresses
  91. * (according to the ARM MMU mmaping). The default initialization supports a
  92. * virtual == physical mapping.
  93. *
  94. */
  95. struct pe_info {
  96. u32 dmem_base_addr; /* PE's dmem base address */
  97. u32 pmem_base_addr; /* PE's pmem base address */
  98. u32 pmem_size; /* PE's pmem size */
  99. void *mem_access_wdata; /* PE's _MEM_ACCESS_WDATA
  100. * register address
  101. */
  102. void *mem_access_addr; /* PE's _MEM_ACCESS_ADDR
  103. * register address
  104. */
  105. void *mem_access_rdata; /* PE's _MEM_ACCESS_RDATA
  106. * register address
  107. */
  108. };
  109. void pe_lmem_read(u32 *dst, u32 len, u32 offset);
  110. void pe_lmem_write(u32 *src, u32 len, u32 offset);
  111. u32 pe_pmem_read(int id, u32 addr, u8 size);
  112. void pe_dmem_write(int id, u32 val, u32 addr, u8 size);
  113. u32 pe_dmem_read(int id, u32 addr, u8 size);
  114. int pe_load_elf_section(int id, const void *data, Elf32_Shdr *shdr);
  115. void pfe_lib_init(void);
  116. void bmu_init(void *base, struct bmu_cfg *cfg);
  117. void bmu_enable(void *base);
  118. void gpi_init(void *base, struct gpi_cfg *cfg);
  119. void gpi_enable(void *base);
  120. void gpi_disable(void *base);
  121. void class_init(struct class_cfg *cfg);
  122. void class_enable(void);
  123. void class_disable(void);
  124. void tmu_init(struct tmu_cfg *cfg);
  125. void tmu_enable(u32 pe_mask);
  126. void tmu_disable(u32 pe_mask);
  127. void hif_init(void);
  128. void hif_tx_enable(void);
  129. void hif_tx_disable(void);
  130. void hif_rx_enable(void);
  131. void hif_rx_disable(void);
  132. void hif_rx_desc_disable(void);
  133. #ifdef PFE_RESET_WA
  134. void pfe_command_stop(int argc, char *const argv[]);
  135. #else
  136. static void pfe_command_stop(int argc, char *const argv[]) {}
  137. #endif
  138. #endif /* _PFE_H_ */