ls1012aqds.c 6.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2016 Freescale Semiconductor, Inc.
  4. */
  5. #include <common.h>
  6. #include <i2c.h>
  7. #include <fdt_support.h>
  8. #include <asm/cache.h>
  9. #include <init.h>
  10. #include <asm/global_data.h>
  11. #include <asm/io.h>
  12. #include <asm/arch/clock.h>
  13. #include <asm/arch/fsl_serdes.h>
  14. #ifdef CONFIG_FSL_LS_PPA
  15. #include <asm/arch/ppa.h>
  16. #endif
  17. #include <asm/arch/fdt.h>
  18. #include <asm/arch/mmu.h>
  19. #include <asm/arch/soc.h>
  20. #include <ahci.h>
  21. #include <hwconfig.h>
  22. #include <mmc.h>
  23. #include <env_internal.h>
  24. #include <scsi.h>
  25. #include <fm_eth.h>
  26. #include <fsl_esdhc.h>
  27. #include <fsl_mmdc.h>
  28. #include <spl.h>
  29. #include <netdev.h>
  30. #include <fsl_sec.h>
  31. #include "../common/qixis.h"
  32. #include "ls1012aqds_qixis.h"
  33. #include "ls1012aqds_pfe.h"
  34. #include <net/pfe_eth/pfe/pfe_hw.h>
  35. DECLARE_GLOBAL_DATA_PTR;
  36. int checkboard(void)
  37. {
  38. char buf[64];
  39. u8 sw;
  40. sw = QIXIS_READ(arch);
  41. printf("Board Arch: V%d, ", sw >> 4);
  42. printf("Board version: %c, boot from ", (sw & 0xf) + 'A' - 1);
  43. sw = QIXIS_READ(brdcfg[QIXIS_LBMAP_BRDCFG_REG]);
  44. if (sw & QIXIS_LBMAP_ALTBANK)
  45. printf("flash: 2\n");
  46. else
  47. printf("flash: 1\n");
  48. printf("FPGA: v%d (%s), build %d",
  49. (int)QIXIS_READ(scver), qixis_read_tag(buf),
  50. (int)qixis_read_minor());
  51. /* the timestamp string contains "\n" at the end */
  52. printf(" on %s", qixis_read_time(buf));
  53. return 0;
  54. }
  55. #ifdef CONFIG_TFABOOT
  56. int dram_init(void)
  57. {
  58. gd->ram_size = tfa_get_dram_size();
  59. if (!gd->ram_size)
  60. gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
  61. return 0;
  62. }
  63. #else
  64. int dram_init(void)
  65. {
  66. static const struct fsl_mmdc_info mparam = {
  67. 0x05180000, /* mdctl */
  68. 0x00030035, /* mdpdc */
  69. 0x12554000, /* mdotc */
  70. 0xbabf7954, /* mdcfg0 */
  71. 0xdb328f64, /* mdcfg1 */
  72. 0x01ff00db, /* mdcfg2 */
  73. 0x00001680, /* mdmisc */
  74. 0x0f3c8000, /* mdref */
  75. 0x00002000, /* mdrwd */
  76. 0x00bf1023, /* mdor */
  77. 0x0000003f, /* mdasp */
  78. 0x0000022a, /* mpodtctrl */
  79. 0xa1390003, /* mpzqhwctrl */
  80. };
  81. mmdc_init(&mparam);
  82. gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
  83. #if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
  84. /* This will break-before-make MMU for DDR */
  85. update_early_mmu_table();
  86. #endif
  87. return 0;
  88. }
  89. #endif
  90. int board_early_init_f(void)
  91. {
  92. fsl_lsch2_early_init_f();
  93. return 0;
  94. }
  95. #ifdef CONFIG_MISC_INIT_R
  96. int misc_init_r(void)
  97. {
  98. u8 mux_sdhc_cd = 0x80;
  99. int bus_num = 0;
  100. #if CONFIG_IS_ENABLED(DM_I2C)
  101. struct udevice *dev;
  102. int ret;
  103. ret = i2c_get_chip_for_busnum(bus_num, CONFIG_SYS_I2C_FPGA_ADDR,
  104. 1, &dev);
  105. if (ret) {
  106. printf("%s: Cannot find udev for a bus %d\n", __func__,
  107. bus_num);
  108. return ret;
  109. }
  110. dm_i2c_write(dev, 0x5a, &mux_sdhc_cd, 1);
  111. #else
  112. i2c_set_bus_num(bus_num);
  113. i2c_write(CONFIG_SYS_I2C_FPGA_ADDR, 0x5a, 1, &mux_sdhc_cd, 1);
  114. #endif
  115. return 0;
  116. }
  117. #endif
  118. int board_init(void)
  119. {
  120. struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR +
  121. CONFIG_SYS_CCI400_OFFSET);
  122. /* Set CCI-400 control override register to enable barrier
  123. * transaction */
  124. if (current_el() == 3)
  125. out_le32(&cci->ctrl_ord,
  126. CCI400_CTRLORD_EN_BARRIER);
  127. #ifdef CONFIG_SYS_FSL_ERRATUM_A010315
  128. erratum_a010315();
  129. #endif
  130. #ifdef CONFIG_ENV_IS_NOWHERE
  131. gd->env_addr = (ulong)&default_environment[0];
  132. #endif
  133. #ifdef CONFIG_FSL_CAAM
  134. sec_init();
  135. #endif
  136. #ifdef CONFIG_FSL_LS_PPA
  137. ppa_init();
  138. #endif
  139. return 0;
  140. }
  141. #ifdef CONFIG_FSL_PFE
  142. void board_quiesce_devices(void)
  143. {
  144. pfe_command_stop(0, NULL);
  145. }
  146. #endif
  147. int esdhc_status_fixup(void *blob, const char *compat)
  148. {
  149. char esdhc0_path[] = "/soc/esdhc@1560000";
  150. char esdhc1_path[] = "/soc/esdhc@1580000";
  151. u8 card_id;
  152. do_fixup_by_path(blob, esdhc0_path, "status", "okay",
  153. sizeof("okay"), 1);
  154. /*
  155. * The Presence Detect 2 register detects the installation
  156. * of cards in various PCI Express or SGMII slots.
  157. *
  158. * STAT_PRS2[7:5]: Specifies the type of card installed in the
  159. * SDHC2 Adapter slot. 0b111 indicates no adapter is installed.
  160. */
  161. card_id = (QIXIS_READ(present2) & 0xe0) >> 5;
  162. /* If no adapter is installed in SDHC2, disable SDHC2 */
  163. if (card_id == 0x7)
  164. do_fixup_by_path(blob, esdhc1_path, "status", "disabled",
  165. sizeof("disabled"), 1);
  166. else
  167. do_fixup_by_path(blob, esdhc1_path, "status", "okay",
  168. sizeof("okay"), 1);
  169. return 0;
  170. }
  171. static int pfe_set_properties(void *set_blob, struct pfe_prop_val prop_val,
  172. char *enet_path, char *mdio_path)
  173. {
  174. do_fixup_by_path(set_blob, enet_path, "fsl,gemac-bus-id",
  175. &prop_val.busid, PFE_PROP_LEN, 1);
  176. do_fixup_by_path(set_blob, enet_path, "fsl,gemac-phy-id",
  177. &prop_val.phyid, PFE_PROP_LEN, 1);
  178. do_fixup_by_path(set_blob, enet_path, "fsl,mdio-mux-val",
  179. &prop_val.mux_val, PFE_PROP_LEN, 1);
  180. do_fixup_by_path(set_blob, enet_path, "phy-mode",
  181. prop_val.phy_mode, strlen(prop_val.phy_mode) + 1, 1);
  182. do_fixup_by_path(set_blob, mdio_path, "fsl,mdio-phy-mask",
  183. &prop_val.phy_mask, PFE_PROP_LEN, 1);
  184. return 0;
  185. }
  186. static void fdt_fsl_fixup_of_pfe(void *blob)
  187. {
  188. int i = 0;
  189. struct pfe_prop_val prop_val;
  190. void *l_blob = blob;
  191. struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
  192. unsigned int srds_s1 = in_be32(&gur->rcwsr[4]) &
  193. FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;
  194. srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;
  195. for (i = 0; i < NUM_ETH_NODE; i++) {
  196. switch (srds_s1) {
  197. case SERDES_1_G_PROTOCOL:
  198. if (i == 0) {
  199. prop_val.busid = cpu_to_fdt32(
  200. ETH_1_1G_BUS_ID);
  201. prop_val.phyid = cpu_to_fdt32(
  202. ETH_1_1G_PHY_ID);
  203. prop_val.mux_val = cpu_to_fdt32(
  204. ETH_1_1G_MDIO_MUX);
  205. prop_val.phy_mask = cpu_to_fdt32(
  206. ETH_1G_MDIO_PHY_MASK);
  207. prop_val.phy_mode = "sgmii";
  208. pfe_set_properties(l_blob, prop_val, ETH_1_PATH,
  209. ETH_1_MDIO);
  210. } else {
  211. prop_val.busid = cpu_to_fdt32(
  212. ETH_2_1G_BUS_ID);
  213. prop_val.phyid = cpu_to_fdt32(
  214. ETH_2_1G_PHY_ID);
  215. prop_val.mux_val = cpu_to_fdt32(
  216. ETH_2_1G_MDIO_MUX);
  217. prop_val.phy_mask = cpu_to_fdt32(
  218. ETH_1G_MDIO_PHY_MASK);
  219. prop_val.phy_mode = "rgmii";
  220. pfe_set_properties(l_blob, prop_val, ETH_2_PATH,
  221. ETH_2_MDIO);
  222. }
  223. break;
  224. case SERDES_2_5_G_PROTOCOL:
  225. if (i == 0) {
  226. prop_val.busid = cpu_to_fdt32(
  227. ETH_1_2_5G_BUS_ID);
  228. prop_val.phyid = cpu_to_fdt32(
  229. ETH_1_2_5G_PHY_ID);
  230. prop_val.mux_val = cpu_to_fdt32(
  231. ETH_1_2_5G_MDIO_MUX);
  232. prop_val.phy_mask = cpu_to_fdt32(
  233. ETH_2_5G_MDIO_PHY_MASK);
  234. prop_val.phy_mode = "sgmii-2500";
  235. pfe_set_properties(l_blob, prop_val, ETH_1_PATH,
  236. ETH_1_MDIO);
  237. } else {
  238. prop_val.busid = cpu_to_fdt32(
  239. ETH_2_2_5G_BUS_ID);
  240. prop_val.phyid = cpu_to_fdt32(
  241. ETH_2_2_5G_PHY_ID);
  242. prop_val.mux_val = cpu_to_fdt32(
  243. ETH_2_2_5G_MDIO_MUX);
  244. prop_val.phy_mask = cpu_to_fdt32(
  245. ETH_2_5G_MDIO_PHY_MASK);
  246. prop_val.phy_mode = "sgmii-2500";
  247. pfe_set_properties(l_blob, prop_val, ETH_2_PATH,
  248. ETH_2_MDIO);
  249. }
  250. break;
  251. default:
  252. printf("serdes:[%d]\n", srds_s1);
  253. }
  254. }
  255. }
  256. #ifdef CONFIG_OF_BOARD_SETUP
  257. int ft_board_setup(void *blob, struct bd_info *bd)
  258. {
  259. arch_fixup_fdt(blob);
  260. ft_cpu_setup(blob, bd);
  261. fdt_fsl_fixup_of_pfe(blob);
  262. return 0;
  263. }
  264. #endif