cache-ncore.c 3.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (C) 2019 Intel Corporation <www.intel.com>
  4. *
  5. */
  6. #include <dm.h>
  7. #include <hang.h>
  8. #include <wait_bit.h>
  9. #include <asm/io.h>
  10. #include <linux/bitops.h>
  11. /* Directory */
  12. #define DIRUSFER 0x80010
  13. #define DIRUCASER0 0x80040
  14. #define DIRUSFMCR 0x80080
  15. #define DIRUSFMAR 0x80084
  16. #define DIRUSFMCR_SFID_SHIFT 16
  17. /* Coherent cache agent interface */
  18. #define CAIUIDR 0x00ffc
  19. #define CAIUIDR_CA_GET(v) (((v) & 0x00008000) >> 15)
  20. #define CAIUIDR_TYPE_GET(v) (((v) & 0x000f0000) >> 16)
  21. #define CAIUIDR_TYPE_ACE_CAI_DVM_SUPPORT 0
  22. #define CAIUIDR_TYPE_ACELITE_CAI_DVM_SUPPORT 1
  23. /* Coherent subsystem */
  24. #define CSADSER0 0xff040
  25. #define CSUIDR 0xffff8
  26. #define CSIDR 0xffffc
  27. #define CSUIDR_NUMCAIUS_GET(v) (((v) & 0x0000007f) >> 0)
  28. #define CSUIDR_NUMDIRUS_GET(v) (((v) & 0x003f0000) >> 16)
  29. #define CSUIDR_NUMCMIUS_GET(v) (((v) & 0x3f000000) >> 24)
  30. #define CSIDR_NUMSFS_GET(v) (((v) & 0x007c0000) >> 18)
  31. #define DIR_REG_SZ 0x1000
  32. #define CAIU_REG_SZ 0x1000
  33. #define CCU_DIR_REG_ADDR(base, reg, dir) \
  34. ((base) + (reg) + ((dir) * DIR_REG_SZ))
  35. /* OCRAM firewall register */
  36. #define OCRAM_FW_01 0x100204
  37. #define OCRAM_SECURE_REGIONS 4
  38. #define OCRAM_PRIVILEGED_MASK BIT(29)
  39. #define OCRAM_SECURE_MASK BIT(30)
  40. static void ncore_ccu_init_dirs(void __iomem *base)
  41. {
  42. ulong i, f;
  43. int ret;
  44. u32 num_of_dirs;
  45. u32 num_of_snoop_filters;
  46. u32 reg;
  47. num_of_dirs = CSUIDR_NUMDIRUS_GET(readl(base + CSUIDR));
  48. num_of_snoop_filters =
  49. CSIDR_NUMSFS_GET(readl(base + CSIDR)) + 1;
  50. /* Initialize each snoop filter in each directory */
  51. for (f = 0; f < num_of_snoop_filters; f++) {
  52. reg = f << DIRUSFMCR_SFID_SHIFT;
  53. for (i = 0; i < num_of_dirs; i++) {
  54. /* Initialize all entries */
  55. writel(reg, CCU_DIR_REG_ADDR(base, DIRUSFMCR, i));
  56. /* Poll snoop filter maintenance operation active
  57. * bit become 0.
  58. */
  59. ret = wait_for_bit_le32((const void *)
  60. CCU_DIR_REG_ADDR(base,
  61. DIRUSFMAR, i),
  62. BIT(0), false, 1000, false);
  63. if (ret) {
  64. puts("CCU: Directory initialization failed!\n");
  65. hang();
  66. }
  67. /* Enable snoop filter, a bit per snoop filter */
  68. setbits_le32((ulong)CCU_DIR_REG_ADDR(base, DIRUSFER, i),
  69. BIT(f));
  70. }
  71. }
  72. }
  73. static void ncore_ccu_init_coh_agent(void __iomem *base)
  74. {
  75. u32 num_of_coh_agent_intf;
  76. u32 num_of_dirs;
  77. u32 reg;
  78. u32 type;
  79. u32 i, dir;
  80. num_of_coh_agent_intf =
  81. CSUIDR_NUMCAIUS_GET(readl(base + CSUIDR));
  82. num_of_dirs = CSUIDR_NUMDIRUS_GET(readl(base + CSUIDR));
  83. for (i = 0; i < num_of_coh_agent_intf; i++) {
  84. reg = readl(base + CAIUIDR + (i * CAIU_REG_SZ));
  85. if (CAIUIDR_CA_GET(reg)) {
  86. /* Caching agent bit is enabled, enable caching agent
  87. * snoop in each directory
  88. */
  89. for (dir = 0; dir < num_of_dirs; dir++) {
  90. setbits_le32((ulong)
  91. CCU_DIR_REG_ADDR(base, DIRUCASER0,
  92. dir),
  93. BIT(i));
  94. }
  95. }
  96. type = CAIUIDR_TYPE_GET(reg);
  97. if (type == CAIUIDR_TYPE_ACE_CAI_DVM_SUPPORT ||
  98. type == CAIUIDR_TYPE_ACELITE_CAI_DVM_SUPPORT) {
  99. /* DVM support is enabled, enable ACE DVM snoop*/
  100. setbits_le32((ulong)(base + CSADSER0),
  101. BIT(i));
  102. }
  103. }
  104. }
  105. static void ocram_bypass_firewall(void __iomem *base)
  106. {
  107. int i;
  108. for (i = 0; i < OCRAM_SECURE_REGIONS; i++) {
  109. clrbits_le32(base + OCRAM_FW_01 + (i * sizeof(u32)),
  110. OCRAM_PRIVILEGED_MASK | OCRAM_SECURE_MASK);
  111. }
  112. }
  113. static int ncore_ccu_probe(struct udevice *dev)
  114. {
  115. void __iomem *base;
  116. fdt_addr_t addr;
  117. addr = dev_read_addr(dev);
  118. if (addr == FDT_ADDR_T_NONE)
  119. return -EINVAL;
  120. base = (void __iomem *)addr;
  121. ncore_ccu_init_dirs(base);
  122. ncore_ccu_init_coh_agent(base);
  123. ocram_bypass_firewall(base);
  124. return 0;
  125. }
  126. static const struct udevice_id ncore_ccu_ids[] = {
  127. { .compatible = "arteris,ncore-ccu" },
  128. {}
  129. };
  130. U_BOOT_DRIVER(ncore_ccu) = {
  131. .name = "ncore_ccu",
  132. .id = UCLASS_CACHE,
  133. .of_match = ncore_ccu_ids,
  134. .probe = ncore_ccu_probe,
  135. .flags = DM_FLAG_PRE_RELOC,
  136. };