axs10x_mb.dtsi 1.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2017 Synopsys, Inc. All rights reserved.
  4. */
  5. / {
  6. axs10x_mb@e0000000 {
  7. compatible = "simple-bus";
  8. #address-cells = <1>;
  9. #size-cells = <1>;
  10. ranges = <0x00000000 0xe0000000 0x10000000>;
  11. u-boot,dm-pre-reloc;
  12. clocks {
  13. compatible = "simple-bus";
  14. u-boot,dm-pre-reloc;
  15. apbclk: apbclk {
  16. compatible = "fixed-clock";
  17. clock-frequency = <50000000>;
  18. #clock-cells = <0>;
  19. };
  20. uartclk: uartclk {
  21. compatible = "fixed-clock";
  22. clock-frequency = <33333333>;
  23. #clock-cells = <0>;
  24. u-boot,dm-pre-reloc;
  25. };
  26. };
  27. ethernet@18000 {
  28. compatible = "altr,socfpga-stmmac";
  29. reg = < 0x18000 0x2000 >;
  30. phy-mode = "gmii";
  31. snps,pbl = < 32 >;
  32. clocks = <&apbclk>;
  33. clock-names = "stmmaceth";
  34. max-speed = <100>;
  35. };
  36. ehci@0x40000 {
  37. compatible = "generic-ehci";
  38. reg = < 0x40000 0x100 >;
  39. };
  40. ohci@0x60000 {
  41. compatible = "generic-ohci";
  42. reg = < 0x60000 0x100 >;
  43. };
  44. uart0: serial0@22000 {
  45. compatible = "snps,dw-apb-uart";
  46. reg = <0x22000 0x100>;
  47. clocks = <&uartclk>;
  48. reg-shift = <2>;
  49. reg-io-width = <4>;
  50. };
  51. };
  52. };