config_mpc85xx.h 28 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794
  1. /*
  2. * Copyright 2011-2012 Freescale Semiconductor, Inc.
  3. *
  4. * SPDX-License-Identifier: GPL-2.0+
  5. */
  6. #ifndef _ASM_MPC85xx_CONFIG_H_
  7. #define _ASM_MPC85xx_CONFIG_H_
  8. /* SoC specific defines for Freescale MPC85xx (PQ3) and QorIQ processors */
  9. /*
  10. * This macro should be removed when we no longer care about backwards
  11. * compatibility with older operating systems.
  12. */
  13. #define CONFIG_PPC_SPINTABLE_COMPATIBLE
  14. #include <fsl_ddrc_version.h>
  15. #define CONFIG_SYS_FSL_DDR_BE
  16. /* IP endianness */
  17. #define CONFIG_SYS_FSL_IFC_BE
  18. #define CONFIG_SYS_FSL_SEC_BE
  19. #define CONFIG_SYS_FSL_SFP_BE
  20. #define CONFIG_SYS_FSL_SEC_MON_BE
  21. /* Number of TLB CAM entries we have on FSL Book-E chips */
  22. #if defined(CONFIG_E500MC)
  23. #define CONFIG_SYS_NUM_TLBCAMS 64
  24. #elif defined(CONFIG_E500)
  25. #define CONFIG_SYS_NUM_TLBCAMS 16
  26. #endif
  27. #if defined(CONFIG_ARCH_MPC8536)
  28. #define CONFIG_SYS_FSL_NUM_LAWS 12
  29. #define CONFIG_SYS_PPC_E500_DEBUG_TLB 1
  30. #define CONFIG_SYS_FSL_SEC_COMPAT 2
  31. #define CONFIG_SYS_FSL_ERRATUM_A004508
  32. #define CONFIG_SYS_FSL_ERRATUM_A005125
  33. #elif defined(CONFIG_ARCH_MPC8540)
  34. #define CONFIG_SYS_FSL_NUM_LAWS 8
  35. #define CONFIG_SYS_FSL_DDRC_GEN1
  36. #elif defined(CONFIG_ARCH_MPC8541)
  37. #define CONFIG_SYS_FSL_NUM_LAWS 8
  38. #define CONFIG_SYS_FSL_DDRC_GEN1
  39. #define CONFIG_SYS_FSL_SEC_COMPAT 2
  40. #elif defined(CONFIG_ARCH_MPC8544)
  41. #define CONFIG_SYS_FSL_NUM_LAWS 10
  42. #define CONFIG_SYS_FSL_DDRC_GEN2
  43. #define CONFIG_SYS_PPC_E500_DEBUG_TLB 0
  44. #define CONFIG_SYS_FSL_SEC_COMPAT 2
  45. #define CONFIG_SYS_FSL_ERRATUM_A005125
  46. #elif defined(CONFIG_ARCH_MPC8548)
  47. #define CONFIG_SYS_FSL_NUM_LAWS 10
  48. #define CONFIG_SYS_FSL_DDRC_GEN2
  49. #define CONFIG_SYS_PPC_E500_DEBUG_TLB 0
  50. #define CONFIG_SYS_FSL_SEC_COMPAT 2
  51. #define CONFIG_SYS_FSL_ERRATUM_NMG_DDR120
  52. #define CONFIG_SYS_FSL_ERRATUM_NMG_LBC103
  53. #define CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
  54. #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1
  55. #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
  56. #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
  57. #define CONFIG_SYS_FSL_RMU
  58. #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
  59. #define CONFIG_SYS_FSL_ERRATUM_A005125
  60. #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
  61. #define CONFIG_SYS_FSL_A004447_SVR_REV 0x00
  62. #elif defined(CONFIG_ARCH_MPC8555)
  63. #define CONFIG_SYS_FSL_NUM_LAWS 8
  64. #define CONFIG_SYS_FSL_DDRC_GEN1
  65. #define CONFIG_SYS_FSL_SEC_COMPAT 2
  66. #elif defined(CONFIG_ARCH_MPC8560)
  67. #define CONFIG_SYS_FSL_NUM_LAWS 8
  68. #define CONFIG_SYS_FSL_DDRC_GEN1
  69. #elif defined(CONFIG_ARCH_MPC8568)
  70. #define CONFIG_SYS_FSL_NUM_LAWS 10
  71. #define CONFIG_SYS_FSL_DDRC_GEN2
  72. #define CONFIG_SYS_FSL_SEC_COMPAT 2
  73. #define QE_MURAM_SIZE 0x10000UL
  74. #define MAX_QE_RISC 2
  75. #define QE_NUM_OF_SNUM 28
  76. #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1
  77. #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
  78. #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
  79. #define CONFIG_SYS_FSL_RMU
  80. #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
  81. #elif defined(CONFIG_ARCH_MPC8569)
  82. #define CONFIG_SYS_FSL_NUM_LAWS 10
  83. #define CONFIG_SYS_FSL_SEC_COMPAT 2
  84. #define QE_MURAM_SIZE 0x20000UL
  85. #define MAX_QE_RISC 4
  86. #define QE_NUM_OF_SNUM 46
  87. #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1
  88. #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
  89. #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
  90. #define CONFIG_SYS_FSL_RMU
  91. #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
  92. #define CONFIG_SYS_FSL_ERRATUM_A004508
  93. #define CONFIG_SYS_FSL_ERRATUM_A005125
  94. #elif defined(CONFIG_ARCH_MPC8572)
  95. #define CONFIG_SYS_FSL_NUM_LAWS 12
  96. #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
  97. #define CONFIG_SYS_FSL_SEC_COMPAT 2
  98. #define CONFIG_SYS_FSL_ERRATUM_DDR_115
  99. #define CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
  100. #define CONFIG_SYS_FSL_ERRATUM_A004508
  101. #define CONFIG_SYS_FSL_ERRATUM_A005125
  102. #elif defined(CONFIG_ARCH_P1010)
  103. #define CONFIG_FSL_SDHC_V2_3
  104. #define CONFIG_SYS_FSL_NUM_LAWS 12
  105. #define CONFIG_SYS_PPC_E500_DEBUG_TLB 3
  106. #define CONFIG_TSECV2
  107. #define CONFIG_SYS_FSL_SEC_COMPAT 4
  108. #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
  109. #define CONFIG_NUM_DDR_CONTROLLERS 1
  110. #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
  111. #define CONFIG_SYS_FSL_IFC_BANK_COUNT 4
  112. #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
  113. #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
  114. #define CONFIG_SYS_FSL_ERRATUM_IFC_A002769
  115. #define CONFIG_SYS_FSL_ERRATUM_P1010_A003549
  116. #define CONFIG_SYS_FSL_ERRATUM_SEC_A003571
  117. #define CONFIG_SYS_FSL_ERRATUM_IFC_A003399
  118. #define CONFIG_SYS_FSL_ERRATUM_A005125
  119. #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
  120. #define CONFIG_SYS_FSL_ERRATUM_A004508
  121. #define CONFIG_SYS_FSL_ERRATUM_A007075
  122. #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
  123. #define CONFIG_SYS_FSL_ERRATUM_A006261
  124. #define CONFIG_SYS_FSL_ERRATUM_A004477
  125. #define CONFIG_SYS_FSL_A004447_SVR_REV 0x10
  126. #define CONFIG_ESDHC_HC_BLK_ADDR
  127. /* P1011 is single core version of P1020 */
  128. #elif defined(CONFIG_ARCH_P1011)
  129. #define CONFIG_SYS_FSL_NUM_LAWS 12
  130. #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
  131. #define CONFIG_TSECV2
  132. #define CONFIG_FSL_PCIE_DISABLE_ASPM
  133. #define CONFIG_SYS_FSL_SEC_COMPAT 2
  134. #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
  135. #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
  136. #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
  137. #define CONFIG_SYS_FSL_ERRATUM_A004508
  138. #define CONFIG_SYS_FSL_ERRATUM_A005125
  139. #elif defined(CONFIG_ARCH_P1020)
  140. #define CONFIG_SYS_FSL_NUM_LAWS 12
  141. #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
  142. #define CONFIG_TSECV2
  143. #define CONFIG_FSL_PCIE_DISABLE_ASPM
  144. #define CONFIG_SYS_FSL_SEC_COMPAT 2
  145. #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
  146. #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
  147. #define CONFIG_SYS_FSL_ERRATUM_A004508
  148. #define CONFIG_SYS_FSL_ERRATUM_A005125
  149. #ifndef CONFIG_USB_MAX_CONTROLLER_COUNT
  150. #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
  151. #endif
  152. #elif defined(CONFIG_ARCH_P1021)
  153. #define CONFIG_SYS_FSL_NUM_LAWS 12
  154. #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
  155. #define CONFIG_TSECV2
  156. #define CONFIG_FSL_PCIE_DISABLE_ASPM
  157. #define CONFIG_SYS_FSL_SEC_COMPAT 2
  158. #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
  159. #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
  160. #define QE_MURAM_SIZE 0x6000UL
  161. #define MAX_QE_RISC 1
  162. #define QE_NUM_OF_SNUM 28
  163. #define CONFIG_SYS_FSL_ERRATUM_A004508
  164. #define CONFIG_SYS_FSL_ERRATUM_A005125
  165. #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
  166. #elif defined(CONFIG_ARCH_P1022)
  167. #define CONFIG_SYS_FSL_NUM_LAWS 12
  168. #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
  169. #define CONFIG_TSECV2
  170. #define CONFIG_SYS_FSL_SEC_COMPAT 2
  171. #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
  172. #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
  173. #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
  174. #define CONFIG_FSL_SATA_ERRATUM_A001
  175. #define CONFIG_SYS_FSL_ERRATUM_A004508
  176. #define CONFIG_SYS_FSL_ERRATUM_A005125
  177. #define CONFIG_SYS_FSL_ERRATUM_A004477
  178. #elif defined(CONFIG_ARCH_P1023)
  179. #define CONFIG_SYS_FSL_NUM_LAWS 12
  180. #define CONFIG_SYS_FSL_SEC_COMPAT 4
  181. #define CONFIG_SYS_NUM_FMAN 1
  182. #define CONFIG_SYS_NUM_FM1_DTSEC 2
  183. #define CONFIG_NUM_DDR_CONTROLLERS 1
  184. #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
  185. #define CONFIG_SYS_QMAN_NUM_PORTALS 3
  186. #define CONFIG_SYS_BMAN_NUM_PORTALS 3
  187. #define CONFIG_SYS_FM_MURAM_SIZE 0x10000
  188. #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
  189. #define CONFIG_SYS_FSL_ERRATUM_A004508
  190. #define CONFIG_SYS_FSL_ERRATUM_A005125
  191. #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
  192. #define CONFIG_SYS_FSL_A004447_SVR_REV 0x11
  193. /* P1024 is lower end variant of P1020 */
  194. #elif defined(CONFIG_ARCH_P1024)
  195. #define CONFIG_SYS_FSL_NUM_LAWS 12
  196. #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
  197. #define CONFIG_TSECV2
  198. #define CONFIG_FSL_PCIE_DISABLE_ASPM
  199. #define CONFIG_SYS_FSL_SEC_COMPAT 2
  200. #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
  201. #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
  202. #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
  203. #define CONFIG_SYS_FSL_ERRATUM_A004508
  204. #define CONFIG_SYS_FSL_ERRATUM_A005125
  205. /* P1025 is lower end variant of P1021 */
  206. #elif defined(CONFIG_ARCH_P1025)
  207. #define CONFIG_SYS_FSL_NUM_LAWS 12
  208. #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
  209. #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
  210. #define CONFIG_TSECV2
  211. #define CONFIG_FSL_PCIE_DISABLE_ASPM
  212. #define CONFIG_SYS_FSL_SEC_COMPAT 2
  213. #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
  214. #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
  215. #define QE_MURAM_SIZE 0x6000UL
  216. #define MAX_QE_RISC 1
  217. #define QE_NUM_OF_SNUM 28
  218. #define CONFIG_SYS_FSL_ERRATUM_A004508
  219. #define CONFIG_SYS_FSL_ERRATUM_A005125
  220. #elif defined(CONFIG_ARCH_P2020)
  221. #define CONFIG_SYS_FSL_NUM_LAWS 12
  222. #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
  223. #define CONFIG_SYS_FSL_SEC_COMPAT 2
  224. #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
  225. #define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
  226. #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
  227. #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
  228. #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
  229. #define CONFIG_SYS_FSL_RMU
  230. #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
  231. #define CONFIG_SYS_FSL_ERRATUM_A004508
  232. #define CONFIG_SYS_FSL_ERRATUM_A005125
  233. #define CONFIG_SYS_FSL_ERRATUM_A004477
  234. #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
  235. #elif defined(CONFIG_ARCH_P2041) /* also supports P2040 */
  236. #define CONFIG_SYS_FSL_QORIQ_CHASSIS1
  237. #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
  238. #define CONFIG_SYS_FSL_NUM_CC_PLLS 2
  239. #define CONFIG_SYS_FSL_NUM_LAWS 32
  240. #define CONFIG_SYS_FSL_SEC_COMPAT 4
  241. #define CONFIG_SYS_NUM_FMAN 1
  242. #define CONFIG_SYS_NUM_FM1_DTSEC 5
  243. #define CONFIG_SYS_NUM_FM1_10GEC 1
  244. #define CONFIG_NUM_DDR_CONTROLLERS 1
  245. #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
  246. #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
  247. #define CONFIG_SYS_FSL_TBCLK_DIV 32
  248. #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
  249. #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
  250. #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
  251. #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
  252. #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
  253. #define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
  254. #define CONFIG_SYS_FSL_ERRATUM_USB14
  255. #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
  256. #define CONFIG_SYS_FSL_ERRATUM_DDR_A003
  257. #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
  258. #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
  259. #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
  260. #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
  261. #define CONFIG_SYS_FSL_ERRATUM_A004510
  262. #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10
  263. #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 0x11
  264. #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
  265. #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
  266. #define CONFIG_SYS_FSL_ERRATUM_A004849
  267. #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
  268. #define CONFIG_SYS_FSL_ERRATUM_A006261
  269. #define CONFIG_SYS_FSL_A004447_SVR_REV 0x11
  270. #elif defined(CONFIG_ARCH_P3041)
  271. #define CONFIG_SYS_FSL_QORIQ_CHASSIS1
  272. #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
  273. #define CONFIG_SYS_FSL_NUM_CC_PLLS 2
  274. #define CONFIG_SYS_FSL_NUM_LAWS 32
  275. #define CONFIG_SYS_FSL_SEC_COMPAT 4
  276. #define CONFIG_SYS_NUM_FMAN 1
  277. #define CONFIG_SYS_NUM_FM1_DTSEC 5
  278. #define CONFIG_SYS_NUM_FM1_10GEC 1
  279. #define CONFIG_NUM_DDR_CONTROLLERS 1
  280. #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_5
  281. #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
  282. #define CONFIG_SYS_FSL_TBCLK_DIV 32
  283. #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
  284. #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
  285. #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
  286. #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
  287. #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
  288. #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
  289. #define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
  290. #define CONFIG_SYS_FSL_ERRATUM_USB14
  291. #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
  292. #define CONFIG_SYS_FSL_ERRATUM_DDR_A003
  293. #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
  294. #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
  295. #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
  296. #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
  297. #define CONFIG_SYS_FSL_ERRATUM_A004510
  298. #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10
  299. #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 0x11
  300. #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
  301. #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
  302. #define CONFIG_SYS_FSL_ERRATUM_A004849
  303. #define CONFIG_SYS_FSL_ERRATUM_A005812
  304. #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
  305. #define CONFIG_SYS_FSL_ERRATUM_A006261
  306. #define CONFIG_SYS_FSL_A004447_SVR_REV 0x20
  307. #elif defined(CONFIG_ARCH_P4080) /* also supports P4040 */
  308. #define CONFIG_SYS_FSL_QORIQ_CHASSIS1
  309. #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
  310. #define CONFIG_SYS_FSL_NUM_CC_PLLS 4
  311. #define CONFIG_SYS_FSL_NUM_LAWS 32
  312. #define CONFIG_SYS_FSL_SEC_COMPAT 4
  313. #define CONFIG_SYS_NUM_FMAN 2
  314. #define CONFIG_SYS_NUM_FM1_DTSEC 4
  315. #define CONFIG_SYS_NUM_FM2_DTSEC 4
  316. #define CONFIG_SYS_NUM_FM1_10GEC 1
  317. #define CONFIG_SYS_NUM_FM2_10GEC 1
  318. #define CONFIG_NUM_DDR_CONTROLLERS 2
  319. #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_4
  320. #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
  321. #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
  322. #define CONFIG_SYS_FSL_TBCLK_DIV 16
  323. #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,p4080-pcie"
  324. #define CONFIG_SYS_FSL_ERRATUM_CPC_A002
  325. #define CONFIG_SYS_FSL_ERRATUM_CPC_A003
  326. #define CONFIG_SYS_FSL_ERRATUM_DDR_A003
  327. #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
  328. #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
  329. #define CONFIG_SYS_FSL_ERRATUM_ESDHC135
  330. #define CONFIG_SYS_FSL_ERRATUM_ESDHC13
  331. #define CONFIG_SYS_P4080_ERRATUM_CPU22
  332. #define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
  333. #define CONFIG_SYS_P4080_ERRATUM_SERDES8
  334. #define CONFIG_SYS_P4080_ERRATUM_SERDES9
  335. #define CONFIG_SYS_P4080_ERRATUM_SERDES_A001
  336. #define CONFIG_SYS_P4080_ERRATUM_SERDES_A005
  337. #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
  338. #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
  339. #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
  340. #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
  341. #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
  342. #define CONFIG_SYS_FSL_RMU
  343. #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
  344. #define CONFIG_SYS_FSL_ERRATUM_A004510
  345. #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x20
  346. #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xff000000
  347. #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
  348. #define CONFIG_SYS_FSL_ERRATUM_A004849
  349. #define CONFIG_SYS_FSL_ERRATUM_A004580
  350. #define CONFIG_SYS_P4080_ERRATUM_PCIE_A003
  351. #define CONFIG_SYS_FSL_ERRATUM_A005812
  352. #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
  353. #define CONFIG_SYS_FSL_ERRATUM_A007075
  354. #define CONFIG_SYS_FSL_A004447_SVR_REV 0x20
  355. #elif defined(CONFIG_ARCH_P5020) /* also supports P5010 */
  356. #define CONFIG_SYS_PPC64 /* 64-bit core */
  357. #define CONFIG_SYS_FSL_QORIQ_CHASSIS1
  358. #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
  359. #define CONFIG_SYS_FSL_NUM_CC_PLLS 2
  360. #define CONFIG_SYS_FSL_NUM_LAWS 32
  361. #define CONFIG_SYS_FSL_SEC_COMPAT 4
  362. #define CONFIG_SYS_NUM_FMAN 1
  363. #define CONFIG_SYS_NUM_FM1_DTSEC 5
  364. #define CONFIG_SYS_NUM_FM1_10GEC 1
  365. #define CONFIG_NUM_DDR_CONTROLLERS 2
  366. #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_4
  367. #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
  368. #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
  369. #define CONFIG_SYS_FSL_TBCLK_DIV 32
  370. #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
  371. #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
  372. #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
  373. #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
  374. #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
  375. #define CONFIG_SYS_FSL_ERRATUM_USB14
  376. #define CONFIG_SYS_FSL_ERRATUM_DDR_A003
  377. #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
  378. #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
  379. #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
  380. #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
  381. #define CONFIG_SYS_FSL_ERRATUM_A004510
  382. #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10
  383. #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xc0000000
  384. #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
  385. #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
  386. #define CONFIG_SYS_FSL_ERRATUM_A006261
  387. #define CONFIG_SYS_FSL_A004447_SVR_REV 0x20
  388. #elif defined(CONFIG_ARCH_P5040)
  389. #define CONFIG_SYS_PPC64
  390. #define CONFIG_SYS_FSL_QORIQ_CHASSIS1
  391. #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
  392. #define CONFIG_SYS_FSL_NUM_CC_PLLS 3
  393. #define CONFIG_SYS_FSL_NUM_LAWS 32
  394. #define CONFIG_SYS_FSL_SEC_COMPAT 4
  395. #define CONFIG_SYS_NUM_FMAN 2
  396. #define CONFIG_SYS_NUM_FM1_DTSEC 5
  397. #define CONFIG_SYS_NUM_FM1_10GEC 1
  398. #define CONFIG_SYS_NUM_FM2_DTSEC 5
  399. #define CONFIG_SYS_NUM_FM2_10GEC 1
  400. #define CONFIG_NUM_DDR_CONTROLLERS 2
  401. #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_4
  402. #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
  403. #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
  404. #define CONFIG_SYS_FSL_TBCLK_DIV 16
  405. #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
  406. #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
  407. #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
  408. #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
  409. #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
  410. #define CONFIG_SYS_FSL_ERRATUM_USB14
  411. #define CONFIG_SYS_FSL_ERRATUM_DDR_A003
  412. #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
  413. #define CONFIG_SYS_FSL_ERRATUM_A004699
  414. #define CONFIG_SYS_FSL_ERRATUM_A004510
  415. #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10
  416. #define CONFIG_SYS_FSL_ERRATUM_A006261
  417. #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
  418. #define CONFIG_SYS_FSL_ERRATUM_A005812
  419. #elif defined(CONFIG_ARCH_BSC9131)
  420. #define CONFIG_FSL_SDHC_V2_3
  421. #define CONFIG_SYS_FSL_NUM_LAWS 12
  422. #define CONFIG_TSECV2
  423. #define CONFIG_SYS_FSL_SEC_COMPAT 4
  424. #define CONFIG_NUM_DDR_CONTROLLERS 1
  425. #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_4
  426. #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
  427. #define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000
  428. #define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000
  429. #define CONFIG_SYS_FSL_IFC_BANK_COUNT 3
  430. #define CONFIG_NAND_FSL_IFC
  431. #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
  432. #define CONFIG_SYS_FSL_ERRATUM_A005125
  433. #define CONFIG_SYS_FSL_ERRATUM_A004477
  434. #define CONFIG_ESDHC_HC_BLK_ADDR
  435. #elif defined(CONFIG_ARCH_BSC9132)
  436. #define CONFIG_SYS_PPC_E500_DEBUG_TLB 3
  437. #define CONFIG_FSL_SDHC_V2_3
  438. #define CONFIG_SYS_FSL_NUM_LAWS 12
  439. #define CONFIG_TSECV2
  440. #define CONFIG_SYS_FSL_SEC_COMPAT 4
  441. #define CONFIG_NUM_DDR_CONTROLLERS 2
  442. #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_6
  443. #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
  444. #define CONFIG_SYS_FSL_DSP_DDR_ADDR 0x40000000
  445. #define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000
  446. #define CONFIG_SYS_FSL_DSP_M3_RAM_ADDR 0xc0000000
  447. #define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000
  448. #define CONFIG_SYS_FSL_IFC_BANK_COUNT 3
  449. #define CONFIG_NAND_FSL_IFC
  450. #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
  451. #define CONFIG_SYS_FSL_ESDHC_P1010_BROKEN_SDCLK
  452. #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
  453. #define CONFIG_SYS_FSL_ERRATUM_A005125
  454. #define CONFIG_SYS_FSL_ERRATUM_A005434
  455. #define CONFIG_SYS_FSL_ERRATUM_A004477
  456. #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
  457. #define CONFIG_SYS_FSL_A004447_SVR_REV 0x11
  458. #define CONFIG_ESDHC_HC_BLK_ADDR
  459. #elif defined(CONFIG_ARCH_T4240) || defined(CONFIG_ARCH_T4160)
  460. #define CONFIG_E6500
  461. #define CONFIG_SYS_PPC64 /* 64-bit core */
  462. #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
  463. #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
  464. #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
  465. #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
  466. #ifdef CONFIG_ARCH_T4240
  467. #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4 }
  468. #define CONFIG_SYS_NUM_FM1_DTSEC 8
  469. #define CONFIG_SYS_NUM_FM1_10GEC 2
  470. #define CONFIG_SYS_NUM_FM2_DTSEC 8
  471. #define CONFIG_SYS_NUM_FM2_10GEC 2
  472. #define CONFIG_NUM_DDR_CONTROLLERS 3
  473. #define CONFIG_SYS_FSL_ERRATUM_A006261
  474. #else
  475. #define CONFIG_SYS_NUM_FM1_DTSEC 6
  476. #define CONFIG_SYS_NUM_FM1_10GEC 1
  477. #define CONFIG_SYS_NUM_FM2_DTSEC 8
  478. #define CONFIG_SYS_NUM_FM2_10GEC 1
  479. #define CONFIG_NUM_DDR_CONTROLLERS 2
  480. #if defined(CONFIG_ARCH_T4160)
  481. #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 }
  482. #endif
  483. #endif
  484. #define CONFIG_SYS_FSL_NUM_CC_PLLS 5
  485. #define CONFIG_SYS_FSL_NUM_LAWS 32
  486. #define CONFIG_SYS_FSL_SRDS_1
  487. #define CONFIG_SYS_FSL_SRDS_2
  488. #define CONFIG_SYS_FSL_SRDS_3
  489. #define CONFIG_SYS_FSL_SRDS_4
  490. #define CONFIG_SYS_FSL_SEC_COMPAT 4
  491. #define CONFIG_SYS_NUM_FMAN 2
  492. #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
  493. #define CONFIG_SYS_PME_CLK 0
  494. #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7
  495. #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
  496. #define CONFIG_SYS_FMAN_V3
  497. #define CONFIG_SYS_FM1_CLK 3
  498. #define CONFIG_SYS_FM2_CLK 3
  499. #define CONFIG_SYS_FM_MURAM_SIZE 0x60000
  500. #define CONFIG_SYS_FSL_TBCLK_DIV 16
  501. #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v3.0"
  502. #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
  503. #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
  504. #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
  505. #define CONFIG_SYS_FSL_SRIO_LIODN
  506. #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
  507. #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
  508. #define CONFIG_SYS_FSL_ERRATUM_A004468
  509. #define CONFIG_SYS_FSL_ERRATUM_A_004934
  510. #define CONFIG_SYS_FSL_ERRATUM_A005871
  511. #define CONFIG_SYS_FSL_ERRATUM_A006379
  512. #define CONFIG_SYS_FSL_ERRATUM_A007186
  513. #define CONFIG_SYS_FSL_ERRATUM_A006593
  514. #define CONFIG_SYS_FSL_ERRATUM_A007798
  515. #define CONFIG_SYS_FSL_SFP_VER_3_0
  516. #define CONFIG_SYS_FSL_PCI_VER_3_X
  517. #elif defined(CONFIG_ARCH_B4860) || defined(CONFIG_ARCH_B4420)
  518. #define CONFIG_E6500
  519. #define CONFIG_SYS_PPC64 /* 64-bit core */
  520. #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
  521. #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
  522. #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
  523. #define CONFIG_HETROGENOUS_CLUSTERS /* DSP/SC3900 core clusters */
  524. #define CONFIG_PPC_CLUSTER_START 0 /*Start index of ppc clusters*/
  525. #define CONFIG_DSP_CLUSTER_START 1 /*Start index of dsp clusters*/
  526. #define CONFIG_SYS_FSL_NUM_LAWS 32
  527. #define CONFIG_SYS_FSL_SRDS_1
  528. #define CONFIG_SYS_FSL_SRDS_2
  529. #define CONFIG_SYS_MAPLE
  530. #define CONFIG_SYS_CPRI
  531. #define CONFIG_SYS_FSL_NUM_CC_PLLS 5
  532. #define CONFIG_SYS_FSL_SEC_COMPAT 4
  533. #define CONFIG_SYS_NUM_FMAN 1
  534. #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
  535. #define CONFIG_SYS_FM1_CLK 0
  536. #define CONFIG_SYS_CPRI_CLK 3
  537. #define CONFIG_SYS_ULB_CLK 4
  538. #define CONFIG_SYS_ETVPE_CLK 1
  539. #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7
  540. #define CONFIG_SYS_FSL_IFC_BANK_COUNT 4
  541. #define CONFIG_SYS_FMAN_V3
  542. #define CONFIG_SYS_FM_MURAM_SIZE 0x60000
  543. #define CONFIG_SYS_FSL_TBCLK_DIV 16
  544. #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
  545. #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
  546. #define CONFIG_SYS_FSL_ERRATUM_A_004934
  547. #define CONFIG_SYS_FSL_ERRATUM_A005871
  548. #define CONFIG_SYS_FSL_ERRATUM_A006379
  549. #define CONFIG_SYS_FSL_ERRATUM_A007186
  550. #define CONFIG_SYS_FSL_ERRATUM_A006593
  551. #define CONFIG_SYS_FSL_ERRATUM_A007075
  552. #define CONFIG_SYS_FSL_ERRATUM_A006475
  553. #define CONFIG_SYS_FSL_ERRATUM_A006384
  554. #define CONFIG_SYS_FSL_ERRATUM_A007212
  555. #define CONFIG_SYS_FSL_ERRATUM_A004477
  556. #define CONFIG_SYS_FSL_SFP_VER_3_0
  557. #ifdef CONFIG_ARCH_B4860
  558. #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
  559. #define CONFIG_MAX_DSP_CPUS 12
  560. #define CONFIG_NUM_DSP_CPUS 6
  561. #define CONFIG_SYS_FSL_SRDS_NUM_PLLS 2
  562. #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 }
  563. #define CONFIG_SYS_NUM_FM1_DTSEC 6
  564. #define CONFIG_SYS_NUM_FM1_10GEC 2
  565. #define CONFIG_NUM_DDR_CONTROLLERS 2
  566. #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
  567. #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
  568. #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
  569. #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
  570. #define CONFIG_SYS_FSL_SRIO_LIODN
  571. #else
  572. #define CONFIG_MAX_DSP_CPUS 2
  573. #define CONFIG_SYS_FSL_SRDS_NUM_PLLS 1
  574. #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 2
  575. #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4 }
  576. #define CONFIG_SYS_NUM_FM1_DTSEC 4
  577. #define CONFIG_SYS_NUM_FM1_10GEC 0
  578. #define CONFIG_NUM_DDR_CONTROLLERS 1
  579. #endif
  580. #elif defined(CONFIG_ARCH_T1040) || defined(CONFIG_ARCH_T1042) ||\
  581. defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
  582. #define CONFIG_E5500
  583. #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
  584. #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
  585. #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 1
  586. #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
  587. #ifdef CONFIG_SYS_FSL_DDR4
  588. #define CONFIG_SYS_FSL_DDRC_GEN4
  589. #endif
  590. #define CONFIG_SYS_FSL_NUM_CC_PLLS 2
  591. #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 }
  592. #define CONFIG_SYS_FSL_NUM_LAWS 16
  593. #define CONFIG_SYS_FSL_SRDS_1
  594. #define CONFIG_SYS_FSL_SEC_COMPAT 5
  595. #define CONFIG_SYS_NUM_FMAN 1
  596. #define CONFIG_SYS_NUM_FM1_DTSEC 5
  597. #define CONFIG_NUM_DDR_CONTROLLERS 1
  598. #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
  599. #define CONFIG_PME_PLAT_CLK_DIV 2
  600. #define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV
  601. #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0
  602. #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
  603. #define CONFIG_SYS_FSL_ERRATUM_A008044
  604. #define CONFIG_SYS_FMAN_V3
  605. #define CONFIG_FM_PLAT_CLK_DIV 1
  606. #define CONFIG_SYS_FM1_CLK CONFIG_FM_PLAT_CLK_DIV
  607. #define CONFIG_SYS_SDHC_CLK 0/* Select SDHC CLK begining from PLL1
  608. per rcw field value */
  609. #define CONFIG_SYS_SDHC_CLK_2_PLL /* Select SDHC CLK from 2 PLLs */
  610. #define CONFIG_SYS_FM_MURAM_SIZE 0x30000
  611. #define CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
  612. #define CONFIG_SYS_FSL_TBCLK_DIV 16
  613. #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
  614. #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
  615. #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
  616. #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
  617. #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
  618. #define QE_MURAM_SIZE 0x6000UL
  619. #define MAX_QE_RISC 1
  620. #define QE_NUM_OF_SNUM 28
  621. #define CONFIG_SYS_FSL_SFP_VER_3_0
  622. #define CONFIG_SYS_FSL_ERRATUM_A008378
  623. #define CONFIG_SYS_FSL_ERRATUM_A009663
  624. #elif defined(CONFIG_ARCH_T1024) || defined(CONFIG_ARCH_T1023) ||\
  625. defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013)
  626. #define CONFIG_E5500
  627. #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
  628. #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
  629. #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 1
  630. #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
  631. #define CONFIG_SYS_FMAN_V3
  632. #ifdef CONFIG_SYS_FSL_DDR4
  633. #define CONFIG_SYS_FSL_DDRC_GEN4
  634. #endif
  635. #define CONFIG_SYS_FSL_NUM_CC_PLL 2
  636. #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 }
  637. #define CONFIG_SYS_FSL_NUM_LAWS 16
  638. #define CONFIG_SYS_FSL_SRDS_1
  639. #define CONFIG_SYS_FSL_SEC_COMPAT 5
  640. #define CONFIG_SYS_NUM_FMAN 1
  641. #define CONFIG_SYS_NUM_FM1_DTSEC 4
  642. #define CONFIG_SYS_NUM_FM1_10GEC 1
  643. #define CONFIG_FSL_FM_10GEC_REGULAR_NOTATION
  644. #define CONFIG_NUM_DDR_CONTROLLERS 1
  645. #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
  646. #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0
  647. #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
  648. #define CONFIG_SYS_FM1_CLK 0
  649. #define CONFIG_SYS_SDHC_CLK 0/* Select SDHC CLK begining from PLL1
  650. per rcw field value */
  651. #define CONFIG_QBMAN_CLK_DIV 1
  652. #define CONFIG_SYS_FM_MURAM_SIZE 0x30000
  653. #define CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
  654. #define CONFIG_SYS_FSL_TBCLK_DIV 16
  655. #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
  656. #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
  657. #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
  658. #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
  659. #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
  660. #define QE_MURAM_SIZE 0x6000UL
  661. #define MAX_QE_RISC 1
  662. #define QE_NUM_OF_SNUM 28
  663. #define CONFIG_SYS_FSL_SFP_VER_3_0
  664. #define CONFIG_SYS_FSL_ERRATUM_A008378
  665. #define CONFIG_SYS_FSL_ERRATUM_A009663
  666. #elif defined(CONFIG_ARCH_T2080) || defined(CONFIG_ARCH_T2081)
  667. #define CONFIG_E6500
  668. #define CONFIG_SYS_PPC64 /* 64-bit core */
  669. #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
  670. #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
  671. #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
  672. #define CONFIG_SYS_FSL_NUM_CC_PLLS 2
  673. #define CONFIG_SYS_FSL_QMAN_V3
  674. #define CONFIG_SYS_FSL_NUM_LAWS 32
  675. #define CONFIG_SYS_FSL_SEC_COMPAT 4
  676. #define CONFIG_SYS_NUM_FMAN 1
  677. #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 }
  678. #define CONFIG_SYS_FSL_SRDS_1
  679. #define CONFIG_SYS_FSL_PCI_VER_3_X
  680. #if defined(CONFIG_ARCH_T2080)
  681. #define CONFIG_SYS_NUM_FM1_DTSEC 8
  682. #define CONFIG_SYS_NUM_FM1_10GEC 4
  683. #define CONFIG_SYS_FSL_SRDS_2
  684. #define CONFIG_SYS_FSL_SRIO_LIODN
  685. #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
  686. #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
  687. #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
  688. #elif defined(CONFIG_ARCH_T2081)
  689. #define CONFIG_SYS_NUM_FM1_DTSEC 6
  690. #define CONFIG_SYS_NUM_FM1_10GEC 2
  691. #endif
  692. #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
  693. #define CONFIG_NUM_DDR_CONTROLLERS 1
  694. #define CONFIG_PME_PLAT_CLK_DIV 1
  695. #define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV
  696. #define CONFIG_SYS_FM1_CLK 0
  697. #define CONFIG_SYS_SDHC_CLK 1/* Select SDHC CLK begining from PLL2
  698. per rcw field value */
  699. #define CONFIG_SYS_SDHC_CLK_2_PLL /* Select SDHC CLK from 2 PLLs */
  700. #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7
  701. #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
  702. #define CONFIG_SYS_FMAN_V3
  703. #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
  704. #define CONFIG_SYS_FSL_TBCLK_DIV 16
  705. #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v3.0"
  706. #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
  707. #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
  708. #define CONFIG_SYS_FSL_ERRATUM_A007212
  709. #define CONFIG_SYS_FSL_SFP_VER_3_0
  710. #define CONFIG_SYS_FSL_ISBC_VER 2
  711. #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
  712. #define CONFIG_SYS_FSL_ERRATUM_A006593
  713. #define CONFIG_SYS_FSL_ERRATUM_A007186
  714. #define CONFIG_SYS_FSL_ERRATUM_A006379
  715. #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
  716. #define CONFIG_SYS_FSL_SFP_VER_3_0
  717. #elif defined(CONFIG_ARCH_C29X)
  718. #define CONFIG_FSL_SDHC_V2_3
  719. #define CONFIG_SYS_FSL_NUM_LAWS 12
  720. #define CONFIG_SYS_PPC_E500_DEBUG_TLB 3
  721. #define CONFIG_TSECV2_1
  722. #define CONFIG_SYS_FSL_SEC_COMPAT 6
  723. #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
  724. #define CONFIG_NUM_DDR_CONTROLLERS 1
  725. #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_6
  726. #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
  727. #define CONFIG_SYS_FSL_ERRATUM_A005125
  728. #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 3
  729. #define CONFIG_SYS_FSL_SEC_IDX_OFFSET 0x20000
  730. #elif defined(CONFIG_ARCH_QEMU_E500)
  731. #else
  732. #error Processor type not defined for this platform
  733. #endif
  734. #ifdef CONFIG_E6500
  735. #define CONFIG_SYS_FSL_THREADS_PER_CORE 2
  736. #else
  737. #define CONFIG_SYS_FSL_THREADS_PER_CORE 1
  738. #endif
  739. #if !defined(CONFIG_SYS_FSL_DDRC_GEN1) && \
  740. !defined(CONFIG_SYS_FSL_DDRC_GEN2) && \
  741. !defined(CONFIG_SYS_FSL_DDRC_GEN3) && \
  742. !defined(CONFIG_SYS_FSL_DDRC_GEN4)
  743. #define CONFIG_SYS_FSL_DDRC_GEN3
  744. #endif
  745. #if !defined(CONFIG_ARCH_C29X)
  746. #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
  747. #endif
  748. #endif /* _ASM_MPC85xx_CONFIG_H_ */