starfive-jh7100.h 6.6 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 OR X11 */
  2. /*
  3. * Copyright (C) 2021 Ahmad Fatoum, Pengutronix
  4. */
  5. #ifndef __DT_BINDINGS_CLOCK_STARFIVE_JH7100_H__
  6. #define __DT_BINDINGS_CLOCK_STARFIVE_JH7100_H__
  7. #define JH7100_CLK_OSC_SYS 0
  8. #define JH7100_CLK_OSC_AUD 1
  9. #define JH7100_CLK_PLL0_OUT 2
  10. #define JH7100_CLK_PLL1_OUT 3
  11. #define JH7100_CLK_PLL2_OUT 4
  12. #define JH7100_CLK_CPUNDBUS_ROOT 5
  13. #define JH7100_CLK_DLA_ROOT 6
  14. #define JH7100_CLK_DSP_ROOT 7
  15. #define JH7100_CLK_GMACUSB_ROOT 8
  16. #define JH7100_CLK_PERH0_ROOT 9
  17. #define JH7100_CLK_PERH1_ROOT 10
  18. #define JH7100_CLK_VIN_ROOT 11
  19. #define JH7100_CLK_VOUT_ROOT 12
  20. #define JH7100_CLK_AUDIO_ROOT 13
  21. #define JH7100_CLK_CDECHIFI4_ROOT 14
  22. #define JH7100_CLK_CDEC_ROOT 15
  23. #define JH7100_CLK_VOUTBUS_ROOT 16
  24. #define JH7100_CLK_CPUNBUS_ROOT_DIV 17
  25. #define JH7100_CLK_DSP_ROOT_DIV 18
  26. #define JH7100_CLK_PERH0_SRC 19
  27. #define JH7100_CLK_PERH1_SRC 20
  28. #define JH7100_CLK_PLL0_TESTOUT 21
  29. #define JH7100_CLK_PLL1_TESTOUT 22
  30. #define JH7100_CLK_PLL2_TESTOUT 23
  31. #define JH7100_CLK_PLL2_REF 24
  32. #define JH7100_CLK_CPU_CORE 25
  33. #define JH7100_CLK_CPU_AXI 26
  34. #define JH7100_CLK_AHB_BUS 27
  35. #define JH7100_CLK_APB1_BUS 28
  36. #define JH7100_CLK_APB2_BUS 29
  37. #define JH7100_CLK_DOM3AHB_BUS 30
  38. #define JH7100_CLK_DOM7AHB_BUS 31
  39. #define JH7100_CLK_U74_CORE0 32
  40. #define JH7100_CLK_U74_CORE1 33
  41. #define JH7100_CLK_U74_AXI 34
  42. #define JH7100_CLK_U74RTC_TOGGLE 35
  43. #define JH7100_CLK_SGDMA2P_AXI 36
  44. #define JH7100_CLK_DMA2PNOC_AXI 37
  45. #define JH7100_CLK_SGDMA2P_AHB 38
  46. #define JH7100_CLK_DLA_BUS 39
  47. #define JH7100_CLK_DLA_AXI 40
  48. #define JH7100_CLK_DLANOC_AXI 41
  49. #define JH7100_CLK_DLA_APB 42
  50. #define JH7100_CLK_VP6_CORE 43
  51. #define JH7100_CLK_VP6BUS_SRC 44
  52. #define JH7100_CLK_VP6_AXI 45
  53. #define JH7100_CLK_VCDECBUS_SRC 46
  54. #define JH7100_CLK_VDEC_BUS 47
  55. #define JH7100_CLK_VDEC_AXI 48
  56. #define JH7100_CLK_VDECBRG_MAIN 49
  57. #define JH7100_CLK_VDEC_BCLK 50
  58. #define JH7100_CLK_VDEC_CCLK 51
  59. #define JH7100_CLK_VDEC_APB 52
  60. #define JH7100_CLK_JPEG_AXI 53
  61. #define JH7100_CLK_JPEG_CCLK 54
  62. #define JH7100_CLK_JPEG_APB 55
  63. #define JH7100_CLK_GC300_2X 56
  64. #define JH7100_CLK_GC300_AHB 57
  65. #define JH7100_CLK_JPCGC300_AXIBUS 58
  66. #define JH7100_CLK_GC300_AXI 59
  67. #define JH7100_CLK_JPCGC300_MAIN 60
  68. #define JH7100_CLK_VENC_BUS 61
  69. #define JH7100_CLK_VENC_AXI 62
  70. #define JH7100_CLK_VENCBRG_MAIN 63
  71. #define JH7100_CLK_VENC_BCLK 64
  72. #define JH7100_CLK_VENC_CCLK 65
  73. #define JH7100_CLK_VENC_APB 66
  74. #define JH7100_CLK_DDRPLL_DIV2 67
  75. #define JH7100_CLK_DDRPLL_DIV4 68
  76. #define JH7100_CLK_DDRPLL_DIV8 69
  77. #define JH7100_CLK_DDROSC_DIV2 70
  78. #define JH7100_CLK_DDRC0 71
  79. #define JH7100_CLK_DDRC1 72
  80. #define JH7100_CLK_DDRPHY_APB 73
  81. #define JH7100_CLK_NOC_ROB 74
  82. #define JH7100_CLK_NOC_COG 75
  83. #define JH7100_CLK_NNE_AHB 76
  84. #define JH7100_CLK_NNEBUS_SRC1 77
  85. #define JH7100_CLK_NNE_BUS 78
  86. #define JH7100_CLK_NNE_AXI 79
  87. #define JH7100_CLK_NNENOC_AXI 80
  88. #define JH7100_CLK_DLASLV_AXI 81
  89. #define JH7100_CLK_DSPX2C_AXI 82
  90. #define JH7100_CLK_HIFI4_SRC 83
  91. #define JH7100_CLK_HIFI4_COREFREE 84
  92. #define JH7100_CLK_HIFI4_CORE 85
  93. #define JH7100_CLK_HIFI4_BUS 86
  94. #define JH7100_CLK_HIFI4_AXI 87
  95. #define JH7100_CLK_HIFI4NOC_AXI 88
  96. #define JH7100_CLK_SGDMA1P_BUS 89
  97. #define JH7100_CLK_SGDMA1P_AXI 90
  98. #define JH7100_CLK_DMA1P_AXI 91
  99. #define JH7100_CLK_X2C_AXI 92
  100. #define JH7100_CLK_USB_BUS 93
  101. #define JH7100_CLK_USB_AXI 94
  102. #define JH7100_CLK_USBNOC_AXI 95
  103. #define JH7100_CLK_USBPHY_ROOTDIV 96
  104. #define JH7100_CLK_USBPHY_125M 97
  105. #define JH7100_CLK_USBPHY_PLLDIV25M 98
  106. #define JH7100_CLK_USBPHY_25M 99
  107. #define JH7100_CLK_AUDIO_DIV 100
  108. #define JH7100_CLK_AUDIO_SRC 101
  109. #define JH7100_CLK_AUDIO_12288 102
  110. #define JH7100_CLK_VIN_SRC 103
  111. #define JH7100_CLK_ISP0_BUS 104
  112. #define JH7100_CLK_ISP0_AXI 105
  113. #define JH7100_CLK_ISP0NOC_AXI 106
  114. #define JH7100_CLK_ISPSLV_AXI 107
  115. #define JH7100_CLK_ISP1_BUS 108
  116. #define JH7100_CLK_ISP1_AXI 109
  117. #define JH7100_CLK_ISP1NOC_AXI 110
  118. #define JH7100_CLK_VIN_BUS 111
  119. #define JH7100_CLK_VIN_AXI 112
  120. #define JH7100_CLK_VINNOC_AXI 113
  121. #define JH7100_CLK_VOUT_SRC 114
  122. #define JH7100_CLK_DISPBUS_SRC 115
  123. #define JH7100_CLK_DISP_BUS 116
  124. #define JH7100_CLK_DISP_AXI 117
  125. #define JH7100_CLK_DISPNOC_AXI 118
  126. #define JH7100_CLK_SDIO0_AHB 119
  127. #define JH7100_CLK_SDIO0_CCLKINT 120
  128. #define JH7100_CLK_SDIO0_CCLKINT_INV 121
  129. #define JH7100_CLK_SDIO1_AHB 122
  130. #define JH7100_CLK_SDIO1_CCLKINT 123
  131. #define JH7100_CLK_SDIO1_CCLKINT_INV 124
  132. #define JH7100_CLK_GMAC_AHB 125
  133. #define JH7100_CLK_GMAC_ROOT_DIV 126
  134. #define JH7100_CLK_GMAC_PTP_REF 127
  135. #define JH7100_CLK_GMAC_GTX 128
  136. #define JH7100_CLK_GMAC_RMII_TX 129
  137. #define JH7100_CLK_GMAC_RMII_RX 130
  138. #define JH7100_CLK_GMAC_TX 131
  139. #define JH7100_CLK_GMAC_TX_INV 132
  140. #define JH7100_CLK_GMAC_RX_PRE 133
  141. #define JH7100_CLK_GMAC_RX_INV 134
  142. #define JH7100_CLK_GMAC_RMII 135
  143. #define JH7100_CLK_GMAC_TOPHYREF 136
  144. #define JH7100_CLK_SPI2AHB_AHB 137
  145. #define JH7100_CLK_SPI2AHB_CORE 138
  146. #define JH7100_CLK_EZMASTER_AHB 139
  147. #define JH7100_CLK_E24_AHB 140
  148. #define JH7100_CLK_E24RTC_TOGGLE 141
  149. #define JH7100_CLK_QSPI_AHB 142
  150. #define JH7100_CLK_QSPI_APB 143
  151. #define JH7100_CLK_QSPI_REF 144
  152. #define JH7100_CLK_SEC_AHB 145
  153. #define JH7100_CLK_AES 146
  154. #define JH7100_CLK_SHA 147
  155. #define JH7100_CLK_PKA 148
  156. #define JH7100_CLK_TRNG_APB 149
  157. #define JH7100_CLK_OTP_APB 150
  158. #define JH7100_CLK_UART0_APB 151
  159. #define JH7100_CLK_UART0_CORE 152
  160. #define JH7100_CLK_UART1_APB 153
  161. #define JH7100_CLK_UART1_CORE 154
  162. #define JH7100_CLK_SPI0_APB 155
  163. #define JH7100_CLK_SPI0_CORE 156
  164. #define JH7100_CLK_SPI1_APB 157
  165. #define JH7100_CLK_SPI1_CORE 158
  166. #define JH7100_CLK_I2C0_APB 159
  167. #define JH7100_CLK_I2C0_CORE 160
  168. #define JH7100_CLK_I2C1_APB 161
  169. #define JH7100_CLK_I2C1_CORE 162
  170. #define JH7100_CLK_GPIO_APB 163
  171. #define JH7100_CLK_UART2_APB 164
  172. #define JH7100_CLK_UART2_CORE 165
  173. #define JH7100_CLK_UART3_APB 166
  174. #define JH7100_CLK_UART3_CORE 167
  175. #define JH7100_CLK_SPI2_APB 168
  176. #define JH7100_CLK_SPI2_CORE 169
  177. #define JH7100_CLK_SPI3_APB 170
  178. #define JH7100_CLK_SPI3_CORE 171
  179. #define JH7100_CLK_I2C2_APB 172
  180. #define JH7100_CLK_I2C2_CORE 173
  181. #define JH7100_CLK_I2C3_APB 174
  182. #define JH7100_CLK_I2C3_CORE 175
  183. #define JH7100_CLK_WDTIMER_APB 176
  184. #define JH7100_CLK_WDT_CORE 177
  185. #define JH7100_CLK_TIMER0_CORE 178
  186. #define JH7100_CLK_TIMER1_CORE 179
  187. #define JH7100_CLK_TIMER2_CORE 180
  188. #define JH7100_CLK_TIMER3_CORE 181
  189. #define JH7100_CLK_TIMER4_CORE 182
  190. #define JH7100_CLK_TIMER5_CORE 183
  191. #define JH7100_CLK_TIMER6_CORE 184
  192. #define JH7100_CLK_VP6INTC_APB 185
  193. #define JH7100_CLK_PWM_APB 186
  194. #define JH7100_CLK_MSI_APB 187
  195. #define JH7100_CLK_TEMP_APB 188
  196. #define JH7100_CLK_TEMP_SENSE 189
  197. #define JH7100_CLK_SYSERR_APB 190
  198. #define JH7100_CLK_END 191
  199. #endif /* __DT_BINDINGS_CLOCK_STARFIVE_JH7100_H__ */