jh7100.dtsi 16 KB

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  1. // SPDX-License-Identifier: (GPL-2.0 OR MIT)
  2. /* Copyright (c) 2021 StarFive Technology Co., Ltd. */
  3. /dts-v1/;
  4. #include <dt-bindings/clock/starfive-jh7100.h>
  5. #include <dt-bindings/starfive_fb.h>
  6. / {
  7. #address-cells = <2>;
  8. #size-cells = <2>;
  9. compatible = "starfive,jh7100";
  10. cpus {
  11. #address-cells = <1>;
  12. #size-cells = <0>;
  13. cpu@0 {
  14. compatible = "sifive,u74-mc", "riscv";
  15. d-cache-block-size = <64>;
  16. d-cache-sets = <64>;
  17. d-cache-size = <32768>;
  18. d-tlb-sets = <1>;
  19. d-tlb-size = <32>;
  20. device_type = "cpu";
  21. i-cache-block-size = <64>;
  22. i-cache-sets = <64>;
  23. i-cache-size = <32768>;
  24. i-tlb-sets = <1>;
  25. i-tlb-size = <32>;
  26. mmu-type = "riscv,sv39";
  27. next-level-cache = <&ccache>;
  28. reg = <0>;
  29. riscv,isa = "rv64imafdc";
  30. starfive,itim = <&itim0>;
  31. status = "okay";
  32. tlb-split;
  33. cpu0_intc: interrupt-controller {
  34. #interrupt-cells = <1>;
  35. compatible = "riscv,cpu-intc";
  36. interrupt-controller;
  37. };
  38. };
  39. cpu@1 {
  40. compatible = "sifive,u74-mc", "riscv";
  41. d-cache-block-size = <64>;
  42. d-cache-sets = <64>;
  43. d-cache-size = <32768>;
  44. d-tlb-sets = <1>;
  45. d-tlb-size = <32>;
  46. device_type = "cpu";
  47. i-cache-block-size = <64>;
  48. i-cache-sets = <64>;
  49. i-cache-size = <32768>;
  50. i-tlb-sets = <1>;
  51. i-tlb-size = <32>;
  52. mmu-type = "riscv,sv39";
  53. next-level-cache = <&ccache>;
  54. reg = <1>;
  55. riscv,isa = "rv64imafdc";
  56. starfive,itim = <&itim1>;
  57. status = "okay";
  58. tlb-split;
  59. cpu1_intc: interrupt-controller {
  60. #interrupt-cells = <1>;
  61. compatible = "riscv,cpu-intc";
  62. interrupt-controller;
  63. };
  64. };
  65. };
  66. osc_sys: osc_sys {
  67. compatible = "fixed-clock";
  68. #clock-cells = <0>;
  69. /* This value must be overridden by the board */
  70. clock-frequency = <0>;
  71. };
  72. osc_aud: osc_aud {
  73. compatible = "fixed-clock";
  74. #clock-cells = <0>;
  75. /* This value must be overridden by the board */
  76. clock-frequency = <0>;
  77. };
  78. soc {
  79. compatible = "simple-bus";
  80. interrupt-parent = <&plic>;
  81. #address-cells = <2>;
  82. #size-cells = <2>;
  83. ranges;
  84. ccache: cache-controller@2010000 {
  85. cache-block-size = <64>;
  86. cache-level = <2>;
  87. cache-sets = <2048>;
  88. cache-size = <2097152>;
  89. cache-unified;
  90. compatible = "sifive,fu540-c000-ccache", "starfive,ccache0", "cache";
  91. interrupts = <128 131 129 130>;
  92. /*next-level-cache = <&L40 &L36>;*/
  93. reg = <0x0 0x2010000 0x0 0x1000>,
  94. <0x0 0x8000000 0x0 0x2000000>;
  95. reg-names = "control", "sideband";
  96. };
  97. dtim: dtim@1000000 {
  98. compatible = "starfive,dtim0";
  99. reg = <0x0 0x1000000 0x0 0x2000>;
  100. reg-names = "mem";
  101. };
  102. itim0: itim@1808000 {
  103. compatible = "starfive,itim0";
  104. reg = <0x0 0x1808000 0x0 0x8000>;
  105. reg-names = "mem";
  106. };
  107. itim1: itim@1820000 {
  108. compatible = "starfive,itim0";
  109. reg = <0x0 0x1820000 0x0 0x8000>;
  110. reg-names = "mem";
  111. };
  112. clint: clint@2000000 {
  113. #interrupt-cells = <1>;
  114. compatible = "riscv,clint0";
  115. interrupts-extended = <&cpu0_intc 3>,
  116. <&cpu0_intc 7>,
  117. <&cpu1_intc 3>,
  118. <&cpu1_intc 7>;
  119. reg = <0x0 0x2000000 0x0 0x10000>;
  120. reg-names = "control";
  121. };
  122. plic: interrupt-controller@c000000 {
  123. #interrupt-cells = <1>;
  124. compatible = "riscv,plic0";
  125. interrupt-controller;
  126. interrupts-extended = <&cpu0_intc 11>,
  127. <&cpu0_intc 9>,
  128. <&cpu1_intc 11>,
  129. <&cpu1_intc 9>;
  130. reg = <0x0 0xc000000 0x0 0x4000000>;
  131. reg-names = "control";
  132. riscv,max-priority = <7>;
  133. riscv,ndev = <127>;
  134. };
  135. clkgen: clock-controller@11800000 {
  136. compatible = "starfive,jh7100-clkgen";
  137. reg = <0x0 0x11800000 0x0 0x10000>;
  138. clocks = <&osc_sys>, <&osc_aud>;
  139. clock-names = "osc_sys", "osc_aud";
  140. #clock-cells = <1>;
  141. };
  142. uart0: serial@11870000 {
  143. compatible = "snps,dw-apb-uart";
  144. interrupts = <92>;
  145. reg = <0x0 0x11870000 0x0 0x10000>;
  146. reg-io-width = <4>;
  147. reg-shift = <2>;
  148. clocks = <&clkgen JH7100_CLK_UART0_CORE>,
  149. <&clkgen JH7100_CLK_UART0_APB>;
  150. clock-names = "baudclk", "apb_pclk";
  151. current-clock = <74250000>;
  152. current-speed = <115200>;
  153. status = "disabled";
  154. };
  155. uart1: serial@11880000 {
  156. compatible = "snps,dw-apb-uart";
  157. interrupts = <93>;
  158. reg = <0x0 0x11880000 0x0 0x10000>;
  159. reg-io-width = <4>;
  160. reg-shift = <2>;
  161. clocks = <&clkgen JH7100_CLK_UART1_CORE>,
  162. <&clkgen JH7100_CLK_UART1_APB>;
  163. clock-names = "baudclk", "apb_pclk";
  164. current-clock = <74250000>;
  165. current-speed = <115200>;
  166. status = "disabled";
  167. };
  168. uart2: serial@12430000 {
  169. compatible = "snps,dw-apb-uart";
  170. interrupts = <72>;
  171. reg = <0x0 0x12430000 0x0 0x10000>;
  172. reg-io-width = <4>;
  173. reg-shift = <2>;
  174. clocks = <&clkgen JH7100_CLK_UART2_CORE>,
  175. <&clkgen JH7100_CLK_UART2_APB>;
  176. clock-names = "baudclk", "apb_pclk";
  177. current-clock = <100000000>;
  178. current-speed = <115200>;
  179. status = "disabled";
  180. };
  181. uart3: serial@12440000 {
  182. compatible = "snps,dw-apb-uart";
  183. interrupts = <73>;
  184. reg = <0x0 0x12440000 0x0 0x10000>;
  185. reg-io-width = <4>;
  186. reg-shift = <2>;
  187. clocks = <&clkgen JH7100_CLK_UART3_CORE>,
  188. <&clkgen JH7100_CLK_UART3_APB>;
  189. clock-names = "baudclk", "apb_pclk";
  190. current-clock = <100000000>;
  191. current-speed = <115200>;
  192. status = "disabled";
  193. };
  194. dma2p: dma-controller@100b0000 {
  195. compatible = "snps,axi-dma-1.01a";
  196. reg = <0x0 0x100b0000 0x0 0x10000>;
  197. clocks = <&clkgen JH7100_CLK_SGDMA2P_AXI>,
  198. <&clkgen JH7100_CLK_SGDMA2P_AHB>;
  199. clock-names = "core-clk", "cfgr-clk";
  200. interrupts = <2>;
  201. #dma-cells = <1>;
  202. dma-channels = <4>;
  203. snps,dma-masters = <1>;
  204. snps,data-width = <4>;
  205. snps,block-size = <4096 4096 4096 4096>;
  206. snps,priority = <0 1 2 3>;
  207. snps,axi-max-burst-len = <128>;
  208. status = "okay";
  209. };
  210. dma1p: dma-controller@10500000 {
  211. compatible = "snps,axi-dma-1.01a";
  212. reg = <0x0 0x10500000 0x0 0x10000>;
  213. clocks = <&clkgen JH7100_CLK_SGDMA1P_AXI>,
  214. <&clkgen JH7100_CLK_SGDMA1P_BUS>;
  215. clock-names = "core-clk", "cfgr-clk";
  216. interrupts = <1>;
  217. #dma-cells = <1>;
  218. dma-channels = <16>;
  219. snps,dma-masters = <1>;
  220. snps,data-width = <3>;
  221. snps,block-size = <4096 4096 4096 4096 4096 4096 4096 4096 4096 4096 4096 4096 4096 4096 4096 4096>;
  222. snps,priority = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15>;
  223. snps,axi-max-burst-len = <64>;
  224. status = "okay";
  225. };
  226. usb3: usb@104c0000 {
  227. compatible = "cdns,usb3";
  228. reg = <0x0 0x104c0000 0x0 0x10000>, // memory area for HOST registers
  229. <0x0 0x104d0000 0x0 0x10000>, // memory area for DEVICE registers
  230. <0x0 0x104e0000 0x0 0x10000>; // memory area for OTG/DRD registers
  231. reg-names = "otg", "xhci", "dev";
  232. interrupts = <44>, <52>, <43>;
  233. interrupt-names = "host", "peripheral", "otg";
  234. phy-names = "cdns3,usb3-phy", "cdns3,usb2-phy";
  235. maximum-speed = "super-speed";
  236. status = "disabled";
  237. };
  238. gpio: gpio@11910000 {
  239. compatible = "starfive,jh7100-gpio";
  240. reg = <0x0 0x11910000 0x0 0x10000>;
  241. clocks = <&clkgen JH7100_CLK_GPIO_APB>;
  242. gpio-controller;
  243. #gpio-cells = <2>;
  244. interrupt-controller;
  245. #interrupt-cells = <2>;
  246. interrupts = <32>;
  247. };
  248. i2c0: i2c@118b0000 {
  249. #address-cells = <1>;
  250. #size-cells = <0>;
  251. compatible = "snps,designware-i2c";
  252. reg = <0x0 0x118b0000 0x0 0x10000>;
  253. interrupts = <96>;
  254. clocks = <&clkgen JH7100_CLK_I2C0_CORE>,
  255. <&clkgen JH7100_CLK_I2C0_APB>;
  256. clock-names = "ref", "pclk";
  257. status = "disabled";
  258. };
  259. i2c1: i2c@118c0000 {
  260. #address-cells = <1>;
  261. #size-cells = <0>;
  262. compatible = "snps,designware-i2c";
  263. reg = <0x0 0x118c0000 0x0 0x10000>;
  264. interrupts = <97>;
  265. clocks = <&clkgen JH7100_CLK_I2C1_CORE>,
  266. <&clkgen JH7100_CLK_I2C1_APB>;
  267. clock-names = "ref", "pclk";
  268. status = "disabled";
  269. };
  270. i2c2: i2c@12450000 {
  271. #address-cells = <1>;
  272. #size-cells = <0>;
  273. compatible = "snps,designware-i2c";
  274. reg = <0x0 0x12450000 0x0 0x10000>;
  275. interrupts = <74>;
  276. clocks = <&clkgen JH7100_CLK_I2C2_CORE>,
  277. <&clkgen JH7100_CLK_I2C2_APB>;
  278. clock-names = "ref", "pclk";
  279. status = "disabled";
  280. };
  281. i2c3: i2c@12460000 {
  282. #address-cells = <1>;
  283. #size-cells = <0>;
  284. compatible = "snps,designware-i2c";
  285. reg = <0x0 0x12460000 0x0 0x10000>;
  286. interrupts = <75>;
  287. clocks = <&clkgen JH7100_CLK_I2C3_CORE>,
  288. <&clkgen JH7100_CLK_I2C3_APB>;
  289. clock-names = "ref", "pclk";
  290. status = "disabled";
  291. };
  292. trng: trng@118d0000 {
  293. compatible = "starfive,vic-rng";
  294. reg = <0x0 0x118d0000 0x0 0x10000>;
  295. interrupts = <98>;
  296. clocks = <&clkgen JH7100_CLK_TRNG_APB>;
  297. };
  298. crypto: crypto@100d0000 {
  299. compatible = "starfive,vic-sec";
  300. reg = <0x0 0x100d0000 0x0 0x20000>,
  301. <0x0 0x11800234 0x0 0xc>;
  302. reg-names = "secmem", "secclk";
  303. interrupts = <31>;
  304. clocks = <&clkgen JH7100_CLK_SEC_AHB>;
  305. };
  306. /* gmac device configuration */
  307. stmmac_axi_setup: stmmac-axi-config {
  308. snps,wr_osr_lmt = <0xf>;
  309. snps,rd_osr_lmt = <0xf>;
  310. snps,blen = <256 128 64 32 0 0 0>;
  311. };
  312. gmac: ethernet@10020000 {
  313. compatible = "snps,dwmac";
  314. reg = <0x0 0x10020000 0x0 0x10000>;
  315. interrupts = <6 7>;
  316. interrupt-names = "macirq", "eth_wake_irq";
  317. max-frame-size = <9000>;
  318. phy-mode = "rgmii-txid";
  319. snps,multicast-filter-bins = <256>;
  320. snps,perfect-filter-entries = <128>;
  321. rx-fifo-depth = <32768>;
  322. tx-fifo-depth = <16384>;
  323. clocks = <&clkgen JH7100_CLK_GMAC_AHB>,
  324. <&clkgen JH7100_CLK_GMAC_AHB>,
  325. <&clkgen JH7100_CLK_GMAC_PTP_REF>;
  326. clock-names = "stmmaceth", "pclk", "ptp_ref";
  327. snps,fixed-burst;
  328. snps,no-pbl-x8 = <1>;
  329. /*snps,force_sf_dma_mode;*/
  330. snps,force_thresh_dma_mode;
  331. snps,axi-config = <&stmmac_axi_setup>;
  332. };
  333. nvdla@11940000 {
  334. compatible = "nvidia,nvdla_os_initial";
  335. interrupts = <22>;
  336. memory-region = <&nvdla_reserved>;
  337. reg = <0x0 0x11940000 0x0 0x40000>;
  338. status = "okay";
  339. };
  340. jpu: coadj12@11900000 {
  341. compatible = "cm,codaj12-jpu-1";
  342. reg = <0x0 0x11900000 0x0 0x300>;
  343. memory-region = <&jpu_reserved>;
  344. interrupts = <24>;
  345. clocks = <&clkgen JH7100_CLK_JPEG_APB>;
  346. clock-names = "jpege";
  347. reg-names = "control";
  348. status = "okay";
  349. };
  350. vpu_dec: vpu_dec@118f0000 {
  351. compatible = "c&m,cm511-vpu";
  352. reg = <0 0x118f0000 0 0x10000>;
  353. //memory-region = <&vpu_reserved>;
  354. interrupts = <23>;
  355. clocks = <&clkgen JH7100_CLK_VP6_CORE>;
  356. clock-names = "vcodec";
  357. status = "okay";
  358. };
  359. vpu_enc: vpu_enc@118e0000 {
  360. compatible = "cm,cm521-vpu";
  361. reg = <0x0 0x118e0000 0x0 0x4000>;
  362. interrupts = <26>;
  363. clocks = <&clkgen JH7100_CLK_VP6_CORE>;
  364. clock-names = "vcodec";
  365. reg-names = "control";
  366. };
  367. ptc: pwm@12490000 {
  368. compatible = "starfive,pwm0";
  369. reg = <0x0 0x12490000 0x0 0x10000>;
  370. reg-names = "control";
  371. sifive,approx-period = <100000000>;
  372. clocks = <&clkgen JH7100_CLK_PWM_APB>;
  373. #pwm-cells = <3>;
  374. sifive,npwm = <8>;
  375. };
  376. qspi: spi@11860000 {
  377. compatible = "cdns,qspi-nor";
  378. #address-cells = <1>;
  379. #size-cells = <0>;
  380. reg = <0x0 0x11860000 0x0 0x10000>,
  381. <0x0 0x20000000 0x0 0x20000000>;
  382. interrupts = <3>;
  383. clocks = <&clkgen JH7100_CLK_QSPI_AHB>;
  384. cdns,fifo-depth = <256>;
  385. cdns,fifo-width = <4>;
  386. cdns,trigger-address = <0x0>;
  387. status = "disabled";
  388. spi-max-frequency = <250000000>;
  389. };
  390. spi0: spi@11890000 {
  391. compatible = "snps,dw-apb-ssi";
  392. #address-cells = <1>;
  393. #size-cells = <0>;
  394. interrupts = <94>;
  395. reg = <0x0 0x11890000 0x0 0x10000>;
  396. clocks = <&clkgen JH7100_CLK_SPI0_CORE>,
  397. <&clkgen JH7100_CLK_SPI0_APB>;
  398. clock-names = "ssi_clk", "pclk";
  399. status = "disabled";
  400. };
  401. spi1: spi@118a0000 {
  402. compatible = "snps,dw-apb-ssi";
  403. #address-cells = <1>;
  404. #size-cells = <0>;
  405. interrupts = <95>;
  406. reg = <0x0 0x118a0000 0x0 0x10000>;
  407. clocks = <&clkgen JH7100_CLK_SPI1_CORE>,
  408. <&clkgen JH7100_CLK_SPI1_APB>;
  409. clock-names = "ssi_clk", "pclk";
  410. status = "disabled";
  411. };
  412. spi2: spi@12410000 {
  413. compatible = "snps,dw-apb-ssi";
  414. #address-cells = <1>;
  415. #size-cells = <0>;
  416. interrupts = <70>;
  417. reg = <0x0 0x12410000 0x0 0x10000>;
  418. clocks = <&clkgen JH7100_CLK_SPI2_CORE>,
  419. <&clkgen JH7100_CLK_SPI2_APB>;
  420. clock-names = "ssi_clk", "pclk";
  421. status = "disabled";
  422. };
  423. spi3: spi@12420000 {
  424. compatible = "snps,dw-apb-ssi";
  425. #address-cells = <1>;
  426. #size-cells = <0>;
  427. interrupts = <71>;
  428. reg = <0x0 0x12420000 0x0 0x10000>;
  429. clocks = <&clkgen JH7100_CLK_SPI3_CORE>,
  430. <&clkgen JH7100_CLK_SPI3_APB>;
  431. clock-names = "ssi_clk", "pclk";
  432. status = "disabled";
  433. };
  434. xrp@f0000000 {
  435. compatible = "cdns,xrp";
  436. reg = <0x0 0xf0000000 0x0 0x01ffffff>,
  437. <0x10 0x72000000 0x0 0x00001000>,
  438. <0x10 0x72001000 0x0 0x00fff000>,
  439. <0x0 0x124b0000 0x0 0x00010000>;
  440. clocks = <&clkgen JH7100_CLK_VP6_CORE>;
  441. firmware-name = "vp6_elf";
  442. dsp-irq = <19 20>;
  443. dsp-irq-src = <0x20 0x21>;
  444. intc-irq-mode = <1>;
  445. intc-irq = <0 1>;
  446. interrupts = <27 28>;
  447. #address-cells = <1>;
  448. #size-cells = <1>;
  449. ranges = <0x40000000 0x0 0x40000000 0x01000000>,
  450. <0xb0000000 0x10 0x70000000 0x3000000>;
  451. dsp@0 {
  452. };
  453. };
  454. sdio0: mmc@10000000 {
  455. compatible = "snps,dw-mshc";
  456. reg = <0x0 0x10000000 0x0 0x10000>;
  457. interrupts = <4>;
  458. clocks = <&clkgen JH7100_CLK_SDIO0_AHB>,
  459. <&clkgen JH7100_CLK_SDIO0_CCLKINT>;
  460. clock-names = "biu", "ciu";
  461. clock-frequency = <100000000>;
  462. data-addr = <0>;
  463. fifo-depth = <32>;
  464. fifo-watermark-aligned;
  465. status = "disabled";
  466. };
  467. sdio1: mmc@10010000 {
  468. compatible = "snps,dw-mshc";
  469. reg = <0x0 0x10010000 0x0 0x10000>;
  470. interrupts = <5>;
  471. clocks = <&clkgen JH7100_CLK_SDIO1_AHB>,
  472. <&clkgen JH7100_CLK_SDIO1_CCLKINT>;
  473. clock-names = "biu", "ciu";
  474. clock-frequency = <100000000>;
  475. data-addr = <0>;
  476. fifo-depth = <32>;
  477. fifo-watermark-aligned;
  478. status = "disabled";
  479. };
  480. sfivefb: sfivefb@12000000 {
  481. compatible = "starfive,vpp-lcdc";
  482. interrupts = <101>, <103>;
  483. interrupt-names = "lcdc_irq", "vpp1_irq";
  484. reg = <0x0 0x12000000 0x0 0x10000>,
  485. <0x0 0x12100000 0x0 0x10000>,
  486. <0x0 0x12040000 0x0 0x10000>,
  487. <0x0 0x12080000 0x0 0x10000>,
  488. <0x0 0x120c0000 0x0 0x10000>,
  489. <0x0 0x12240000 0x0 0x10000>,
  490. <0x0 0x12250000 0x0 0x10000>,
  491. <0x0 0x12260000 0x0 0x10000>;
  492. reg-names = "lcdc", "dsitx", "vpp0", "vpp1", "vpp2", "clk", "rst", "sys";
  493. memory-region = <&sffb_reserved>;
  494. #if 0 // FIXME uart clocks can't be right for lcdc
  495. clocks = <&clkgen JH7100_CLK_UART>,
  496. <&clkgen JH7100_CLK_APB2>;
  497. #endif
  498. clock-names = "baudclk", "apb_pclk";
  499. ddr-format = <WIN_FMT_RGB565>;/*LCDC win_format*/
  500. status = "disabled";
  501. };
  502. vin_sysctl: vin_sysctl@19800000 {
  503. compatible = "starfive,stf-vin";
  504. reg = <0x0 0x19800000 0x0 0x10000>,
  505. <0x0 0x19810000 0x0 0x10000>,
  506. <0x0 0x19820000 0x0 0x10000>,
  507. <0x0 0x19830000 0x0 0x10000>,
  508. <0x0 0x19840000 0x0 0x10000>,
  509. <0x0 0x19870000 0x0 0x30000>,
  510. <0x0 0x198a0000 0x0 0x30000>,
  511. <0x0 0x11800000 0x0 0x10000>,
  512. <0x0 0x11840000 0x0 0x10000>,
  513. <0x0 0x11858000 0x0 0x10000>;
  514. reg-names = "mipi0", "vclk", "vrst", "mipi1", "sctrl",
  515. "isp0", "isp1", "tclk", "trst", "iopad";
  516. interrupts = <119 109>;
  517. memory-region = <&vin_reserved>;
  518. /*defaule config for imx219 vin&isp*/
  519. format = <SRC_CSI2RX_VIN_ISP>;
  520. frame-width = <800>;
  521. frame-height =<480>;
  522. isp0_enable;
  523. csi-lane = <2>;
  524. csi-dlane-swaps = /bits/ 8 <1>,/bits/ 8 <2>,/bits/ 8 <3>,/bits/ 8 <4>;
  525. csi-dlane-pn-swaps = /bits/ 8 <0>,/bits/ 8 <0>,/bits/ 8 <0>,/bits/ 8 <0>;
  526. csi-clane-swap = /bits/ 8 <0>;
  527. csi-clane-pn-swap = /bits/ 8 <0>;
  528. csi-mipiID = <0>;
  529. csi-width = <1920>;
  530. csi-height = <1080>;
  531. csi-dt = <0x2b>;
  532. };
  533. sfctemp: tmon@124a0000 {
  534. compatible = "starfive,jh7100-temp";
  535. reg = <0x0 0x124a0000 0x0 0x10000>;
  536. #thermal-sensor-cells = <0>;
  537. interrupts = <122>;
  538. };
  539. thermal-zones {
  540. cpu-thermal {
  541. polling-delay-passive = <250>;
  542. polling-delay = <15000>;
  543. thermal-sensors = <&sfctemp>;
  544. cooling-maps {
  545. };
  546. trips {
  547. cpu_alert0: cpu_alert0 {
  548. /* milliCelsius */
  549. temperature = <75000>;
  550. hysteresis = <2000>;
  551. type = "passive";
  552. };
  553. cpu_crit: cpu_crit {
  554. /* milliCelsius */
  555. temperature = <90000>;
  556. hysteresis = <2000>;
  557. type = "critical";
  558. };
  559. };
  560. };
  561. };
  562. otp: otp@11810000 {
  563. compatible = "starfive,fu740-otp";
  564. reg = <0x0 0x11810000 0x0 0x10000>;
  565. fuse-count = <0x200>;
  566. clocks = <&clkgen JH7100_CLK_OTP_APB>;
  567. };
  568. };
  569. };