zynqmp.c 13 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2014 - 2015 Xilinx, Inc.
  4. * Michal Simek <michal.simek@xilinx.com>
  5. */
  6. #include <common.h>
  7. #include <cpu_func.h>
  8. #include <debug_uart.h>
  9. #include <env.h>
  10. #include <init.h>
  11. #include <sata.h>
  12. #include <ahci.h>
  13. #include <scsi.h>
  14. #include <malloc.h>
  15. #include <wdt.h>
  16. #include <asm/arch/clk.h>
  17. #include <asm/arch/hardware.h>
  18. #include <asm/arch/sys_proto.h>
  19. #include <asm/arch/psu_init_gpl.h>
  20. #include <asm/io.h>
  21. #include <dm/device.h>
  22. #include <dm/uclass.h>
  23. #include <usb.h>
  24. #include <dwc3-uboot.h>
  25. #include <zynqmppl.h>
  26. #include <zynqmp_firmware.h>
  27. #include <g_dnl.h>
  28. #include <linux/sizes.h>
  29. #include "../common/board.h"
  30. #include "pm_cfg_obj.h"
  31. DECLARE_GLOBAL_DATA_PTR;
  32. #if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
  33. !defined(CONFIG_SPL_BUILD)
  34. static xilinx_desc zynqmppl = XILINX_ZYNQMP_DESC;
  35. static const struct {
  36. u32 id;
  37. u32 ver;
  38. char *name;
  39. bool evexists;
  40. } zynqmp_devices[] = {
  41. {
  42. .id = 0x10,
  43. .name = "3eg",
  44. },
  45. {
  46. .id = 0x10,
  47. .ver = 0x2c,
  48. .name = "3cg",
  49. },
  50. {
  51. .id = 0x11,
  52. .name = "2eg",
  53. },
  54. {
  55. .id = 0x11,
  56. .ver = 0x2c,
  57. .name = "2cg",
  58. },
  59. {
  60. .id = 0x20,
  61. .name = "5ev",
  62. .evexists = 1,
  63. },
  64. {
  65. .id = 0x20,
  66. .ver = 0x100,
  67. .name = "5eg",
  68. .evexists = 1,
  69. },
  70. {
  71. .id = 0x20,
  72. .ver = 0x12c,
  73. .name = "5cg",
  74. .evexists = 1,
  75. },
  76. {
  77. .id = 0x21,
  78. .name = "4ev",
  79. .evexists = 1,
  80. },
  81. {
  82. .id = 0x21,
  83. .ver = 0x100,
  84. .name = "4eg",
  85. .evexists = 1,
  86. },
  87. {
  88. .id = 0x21,
  89. .ver = 0x12c,
  90. .name = "4cg",
  91. .evexists = 1,
  92. },
  93. {
  94. .id = 0x30,
  95. .name = "7ev",
  96. .evexists = 1,
  97. },
  98. {
  99. .id = 0x30,
  100. .ver = 0x100,
  101. .name = "7eg",
  102. .evexists = 1,
  103. },
  104. {
  105. .id = 0x30,
  106. .ver = 0x12c,
  107. .name = "7cg",
  108. .evexists = 1,
  109. },
  110. {
  111. .id = 0x38,
  112. .name = "9eg",
  113. },
  114. {
  115. .id = 0x38,
  116. .ver = 0x2c,
  117. .name = "9cg",
  118. },
  119. {
  120. .id = 0x39,
  121. .name = "6eg",
  122. },
  123. {
  124. .id = 0x39,
  125. .ver = 0x2c,
  126. .name = "6cg",
  127. },
  128. {
  129. .id = 0x40,
  130. .name = "11eg",
  131. },
  132. { /* For testing purpose only */
  133. .id = 0x50,
  134. .ver = 0x2c,
  135. .name = "15cg",
  136. },
  137. {
  138. .id = 0x50,
  139. .name = "15eg",
  140. },
  141. {
  142. .id = 0x58,
  143. .name = "19eg",
  144. },
  145. {
  146. .id = 0x59,
  147. .name = "17eg",
  148. },
  149. {
  150. .id = 0x61,
  151. .name = "21dr",
  152. },
  153. {
  154. .id = 0x63,
  155. .name = "23dr",
  156. },
  157. {
  158. .id = 0x65,
  159. .name = "25dr",
  160. },
  161. {
  162. .id = 0x64,
  163. .name = "27dr",
  164. },
  165. {
  166. .id = 0x60,
  167. .name = "28dr",
  168. },
  169. {
  170. .id = 0x62,
  171. .name = "29dr",
  172. },
  173. {
  174. .id = 0x66,
  175. .name = "39dr",
  176. },
  177. {
  178. .id = 0x7b,
  179. .name = "48dr",
  180. },
  181. {
  182. .id = 0x7e,
  183. .name = "49dr",
  184. },
  185. };
  186. #endif
  187. int chip_id(unsigned char id)
  188. {
  189. struct pt_regs regs;
  190. int val = -EINVAL;
  191. if (current_el() != 3) {
  192. regs.regs[0] = ZYNQMP_SIP_SVC_CSU_DMA_CHIPID;
  193. regs.regs[1] = 0;
  194. regs.regs[2] = 0;
  195. regs.regs[3] = 0;
  196. smc_call(&regs);
  197. /*
  198. * SMC returns:
  199. * regs[0][31:0] = status of the operation
  200. * regs[0][63:32] = CSU.IDCODE register
  201. * regs[1][31:0] = CSU.version register
  202. * regs[1][63:32] = CSU.IDCODE2 register
  203. */
  204. switch (id) {
  205. case IDCODE:
  206. regs.regs[0] = upper_32_bits(regs.regs[0]);
  207. regs.regs[0] &= ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK |
  208. ZYNQMP_CSU_IDCODE_SVD_MASK;
  209. regs.regs[0] >>= ZYNQMP_CSU_IDCODE_SVD_SHIFT;
  210. val = regs.regs[0];
  211. break;
  212. case VERSION:
  213. regs.regs[1] = lower_32_bits(regs.regs[1]);
  214. regs.regs[1] &= ZYNQMP_CSU_SILICON_VER_MASK;
  215. val = regs.regs[1];
  216. break;
  217. case IDCODE2:
  218. regs.regs[1] = lower_32_bits(regs.regs[1]);
  219. regs.regs[1] >>= ZYNQMP_CSU_VERSION_EMPTY_SHIFT;
  220. val = regs.regs[1];
  221. break;
  222. default:
  223. printf("%s, Invalid Req:0x%x\n", __func__, id);
  224. }
  225. } else {
  226. switch (id) {
  227. case IDCODE:
  228. val = readl(ZYNQMP_CSU_IDCODE_ADDR);
  229. val &= ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK |
  230. ZYNQMP_CSU_IDCODE_SVD_MASK;
  231. val >>= ZYNQMP_CSU_IDCODE_SVD_SHIFT;
  232. break;
  233. case VERSION:
  234. val = readl(ZYNQMP_CSU_VER_ADDR);
  235. val &= ZYNQMP_CSU_SILICON_VER_MASK;
  236. break;
  237. default:
  238. printf("%s, Invalid Req:0x%x\n", __func__, id);
  239. }
  240. }
  241. return val;
  242. }
  243. #define ZYNQMP_VERSION_SIZE 9
  244. #define ZYNQMP_PL_STATUS_BIT 9
  245. #define ZYNQMP_IPDIS_VCU_BIT 8
  246. #define ZYNQMP_PL_STATUS_MASK BIT(ZYNQMP_PL_STATUS_BIT)
  247. #define ZYNQMP_CSU_VERSION_MASK ~(ZYNQMP_PL_STATUS_MASK)
  248. #define ZYNQMP_CSU_VCUDIS_VER_MASK ZYNQMP_CSU_VERSION_MASK & \
  249. ~BIT(ZYNQMP_IPDIS_VCU_BIT)
  250. #define MAX_VARIANTS_EV 3
  251. #if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
  252. !defined(CONFIG_SPL_BUILD)
  253. static char *zynqmp_get_silicon_idcode_name(void)
  254. {
  255. u32 i, id, ver, j;
  256. char *buf;
  257. static char name[ZYNQMP_VERSION_SIZE];
  258. id = chip_id(IDCODE);
  259. ver = chip_id(IDCODE2);
  260. for (i = 0; i < ARRAY_SIZE(zynqmp_devices); i++) {
  261. if (zynqmp_devices[i].id == id) {
  262. if (zynqmp_devices[i].evexists &&
  263. !(ver & ZYNQMP_PL_STATUS_MASK))
  264. break;
  265. if (zynqmp_devices[i].ver == (ver &
  266. ZYNQMP_CSU_VERSION_MASK))
  267. break;
  268. }
  269. }
  270. if (i >= ARRAY_SIZE(zynqmp_devices))
  271. return "unknown";
  272. strncat(name, "zu", 2);
  273. if (!zynqmp_devices[i].evexists ||
  274. (ver & ZYNQMP_PL_STATUS_MASK)) {
  275. strncat(name, zynqmp_devices[i].name,
  276. ZYNQMP_VERSION_SIZE - 3);
  277. return name;
  278. }
  279. /*
  280. * Here we are means, PL not powered up and ev variant
  281. * exists. So, we need to ignore VCU disable bit(8) in
  282. * version and findout if its CG or EG/EV variant.
  283. */
  284. for (j = 0; j < MAX_VARIANTS_EV; j++, i++) {
  285. if ((zynqmp_devices[i].ver & ~BIT(ZYNQMP_IPDIS_VCU_BIT)) ==
  286. (ver & ZYNQMP_CSU_VCUDIS_VER_MASK)) {
  287. strncat(name, zynqmp_devices[i].name,
  288. ZYNQMP_VERSION_SIZE - 3);
  289. break;
  290. }
  291. }
  292. if (j >= MAX_VARIANTS_EV)
  293. return "unknown";
  294. if (strstr(name, "eg") || strstr(name, "ev")) {
  295. buf = strstr(name, "e");
  296. *buf = '\0';
  297. }
  298. return name;
  299. }
  300. #endif
  301. int board_early_init_f(void)
  302. {
  303. #if defined(CONFIG_ZYNQMP_PSU_INIT_ENABLED)
  304. int ret;
  305. ret = psu_init();
  306. if (ret)
  307. return ret;
  308. /* Delay is required for clocks to be propagated */
  309. udelay(1000000);
  310. #endif
  311. #ifdef CONFIG_DEBUG_UART
  312. /* Uart debug for sure */
  313. debug_uart_init();
  314. puts("Debug uart enabled\n"); /* or printch() */
  315. #endif
  316. return 0;
  317. }
  318. static int multi_boot(void)
  319. {
  320. u32 multiboot;
  321. multiboot = readl(&csu_base->multi_boot);
  322. printf("Multiboot:\t%x\n", multiboot);
  323. return 0;
  324. }
  325. int board_init(void)
  326. {
  327. #if defined(CONFIG_ZYNQMP_FIRMWARE)
  328. struct udevice *dev;
  329. uclass_get_device_by_name(UCLASS_FIRMWARE, "zynqmp-power", &dev);
  330. if (!dev)
  331. panic("PMU Firmware device not found - Enable it");
  332. #endif
  333. #if defined(CONFIG_SPL_BUILD)
  334. /* Check *at build time* if the filename is an non-empty string */
  335. if (sizeof(CONFIG_ZYNQMP_SPL_PM_CFG_OBJ_FILE) > 1)
  336. zynqmp_pmufw_load_config_object(zynqmp_pm_cfg_obj,
  337. zynqmp_pm_cfg_obj_size);
  338. #endif
  339. printf("EL Level:\tEL%d\n", current_el());
  340. #if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
  341. !defined(CONFIG_SPL_BUILD) || (defined(CONFIG_SPL_FPGA_SUPPORT) && \
  342. defined(CONFIG_SPL_BUILD))
  343. if (current_el() != 3) {
  344. zynqmppl.name = zynqmp_get_silicon_idcode_name();
  345. printf("Chip ID:\t%s\n", zynqmppl.name);
  346. fpga_init();
  347. fpga_add(fpga_xilinx, &zynqmppl);
  348. }
  349. #endif
  350. if (current_el() == 3)
  351. multi_boot();
  352. return 0;
  353. }
  354. int board_early_init_r(void)
  355. {
  356. u32 val;
  357. if (current_el() != 3)
  358. return 0;
  359. val = readl(&crlapb_base->timestamp_ref_ctrl);
  360. val &= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT;
  361. if (!val) {
  362. val = readl(&crlapb_base->timestamp_ref_ctrl);
  363. val |= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT;
  364. writel(val, &crlapb_base->timestamp_ref_ctrl);
  365. /* Program freq register in System counter */
  366. writel(zynqmp_get_system_timer_freq(),
  367. &iou_scntr_secure->base_frequency_id_register);
  368. /* And enable system counter */
  369. writel(ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN,
  370. &iou_scntr_secure->counter_control_register);
  371. }
  372. return 0;
  373. }
  374. unsigned long do_go_exec(ulong (*entry)(int, char * const []), int argc,
  375. char * const argv[])
  376. {
  377. int ret = 0;
  378. if (current_el() > 1) {
  379. smp_kick_all_cpus();
  380. dcache_disable();
  381. armv8_switch_to_el1(0x0, 0, 0, 0, (unsigned long)entry,
  382. ES_TO_AARCH64);
  383. } else {
  384. printf("FAIL: current EL is not above EL1\n");
  385. ret = EINVAL;
  386. }
  387. return ret;
  388. }
  389. #if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE)
  390. int dram_init_banksize(void)
  391. {
  392. int ret;
  393. ret = fdtdec_setup_memory_banksize();
  394. if (ret)
  395. return ret;
  396. mem_map_fill();
  397. return 0;
  398. }
  399. int dram_init(void)
  400. {
  401. if (fdtdec_setup_mem_size_base() != 0)
  402. return -EINVAL;
  403. return 0;
  404. }
  405. #else
  406. int dram_init_banksize(void)
  407. {
  408. #if defined(CONFIG_NR_DRAM_BANKS)
  409. gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
  410. gd->bd->bi_dram[0].size = get_effective_memsize();
  411. #endif
  412. mem_map_fill();
  413. return 0;
  414. }
  415. int dram_init(void)
  416. {
  417. gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
  418. CONFIG_SYS_SDRAM_SIZE);
  419. return 0;
  420. }
  421. #endif
  422. void reset_cpu(ulong addr)
  423. {
  424. }
  425. #if defined(CONFIG_BOARD_LATE_INIT)
  426. static const struct {
  427. u32 bit;
  428. const char *name;
  429. } reset_reasons[] = {
  430. { RESET_REASON_DEBUG_SYS, "DEBUG" },
  431. { RESET_REASON_SOFT, "SOFT" },
  432. { RESET_REASON_SRST, "SRST" },
  433. { RESET_REASON_PSONLY, "PS-ONLY" },
  434. { RESET_REASON_PMU, "PMU" },
  435. { RESET_REASON_INTERNAL, "INTERNAL" },
  436. { RESET_REASON_EXTERNAL, "EXTERNAL" },
  437. {}
  438. };
  439. static int reset_reason(void)
  440. {
  441. u32 reg;
  442. int i, ret;
  443. const char *reason = NULL;
  444. ret = zynqmp_mmio_read((ulong)&crlapb_base->reset_reason, &reg);
  445. if (ret)
  446. return -EINVAL;
  447. puts("Reset reason:\t");
  448. for (i = 0; i < ARRAY_SIZE(reset_reasons); i++) {
  449. if (reg & reset_reasons[i].bit) {
  450. reason = reset_reasons[i].name;
  451. printf("%s ", reset_reasons[i].name);
  452. break;
  453. }
  454. }
  455. puts("\n");
  456. env_set("reset_reason", reason);
  457. ret = zynqmp_mmio_write((ulong)&crlapb_base->reset_reason, ~0, ~0);
  458. if (ret)
  459. return -EINVAL;
  460. return ret;
  461. }
  462. static int set_fdtfile(void)
  463. {
  464. char *compatible, *fdtfile;
  465. const char *suffix = ".dtb";
  466. const char *vendor = "xilinx/";
  467. if (env_get("fdtfile"))
  468. return 0;
  469. compatible = (char *)fdt_getprop(gd->fdt_blob, 0, "compatible", NULL);
  470. if (compatible) {
  471. debug("Compatible: %s\n", compatible);
  472. /* Discard vendor prefix */
  473. strsep(&compatible, ",");
  474. fdtfile = calloc(1, strlen(vendor) + strlen(compatible) +
  475. strlen(suffix) + 1);
  476. if (!fdtfile)
  477. return -ENOMEM;
  478. sprintf(fdtfile, "%s%s%s", vendor, compatible, suffix);
  479. env_set("fdtfile", fdtfile);
  480. free(fdtfile);
  481. }
  482. return 0;
  483. }
  484. int board_late_init(void)
  485. {
  486. u32 reg = 0;
  487. u8 bootmode;
  488. struct udevice *dev;
  489. int bootseq = -1;
  490. int bootseq_len = 0;
  491. int env_targets_len = 0;
  492. const char *mode;
  493. char *new_targets;
  494. char *env_targets;
  495. int ret;
  496. ulong initrd_hi;
  497. #if defined(CONFIG_USB_ETHER) && !defined(CONFIG_USB_GADGET_DOWNLOAD)
  498. usb_ether_init();
  499. #endif
  500. if (!(gd->flags & GD_FLG_ENV_DEFAULT)) {
  501. debug("Saved variables - Skipping\n");
  502. return 0;
  503. }
  504. ret = set_fdtfile();
  505. if (ret)
  506. return ret;
  507. ret = zynqmp_mmio_read((ulong)&crlapb_base->boot_mode, &reg);
  508. if (ret)
  509. return -EINVAL;
  510. if (reg >> BOOT_MODE_ALT_SHIFT)
  511. reg >>= BOOT_MODE_ALT_SHIFT;
  512. bootmode = reg & BOOT_MODES_MASK;
  513. puts("Bootmode: ");
  514. switch (bootmode) {
  515. case USB_MODE:
  516. puts("USB_MODE\n");
  517. mode = "usb";
  518. env_set("modeboot", "usb_dfu_spl");
  519. break;
  520. case JTAG_MODE:
  521. puts("JTAG_MODE\n");
  522. mode = "jtag pxe dhcp";
  523. env_set("modeboot", "jtagboot");
  524. break;
  525. case QSPI_MODE_24BIT:
  526. case QSPI_MODE_32BIT:
  527. mode = "qspi0";
  528. puts("QSPI_MODE\n");
  529. env_set("modeboot", "qspiboot");
  530. break;
  531. case EMMC_MODE:
  532. puts("EMMC_MODE\n");
  533. if (uclass_get_device_by_name(UCLASS_MMC,
  534. "mmc@ff160000", &dev) &&
  535. uclass_get_device_by_name(UCLASS_MMC,
  536. "sdhci@ff160000", &dev)) {
  537. puts("Boot from EMMC but without SD0 enabled!\n");
  538. return -1;
  539. }
  540. debug("mmc0 device found at %p, seq %d\n", dev, dev->seq);
  541. mode = "mmc";
  542. bootseq = dev->seq;
  543. break;
  544. case SD_MODE:
  545. puts("SD_MODE\n");
  546. if (uclass_get_device_by_name(UCLASS_MMC,
  547. "mmc@ff160000", &dev) &&
  548. uclass_get_device_by_name(UCLASS_MMC,
  549. "sdhci@ff160000", &dev)) {
  550. puts("Boot from SD0 but without SD0 enabled!\n");
  551. return -1;
  552. }
  553. debug("mmc0 device found at %p, seq %d\n", dev, dev->seq);
  554. mode = "mmc";
  555. bootseq = dev->seq;
  556. env_set("modeboot", "sdboot");
  557. break;
  558. case SD1_LSHFT_MODE:
  559. puts("LVL_SHFT_");
  560. /* fall through */
  561. case SD_MODE1:
  562. puts("SD_MODE1\n");
  563. if (uclass_get_device_by_name(UCLASS_MMC,
  564. "mmc@ff170000", &dev) &&
  565. uclass_get_device_by_name(UCLASS_MMC,
  566. "sdhci@ff170000", &dev)) {
  567. puts("Boot from SD1 but without SD1 enabled!\n");
  568. return -1;
  569. }
  570. debug("mmc1 device found at %p, seq %d\n", dev, dev->seq);
  571. mode = "mmc";
  572. bootseq = dev->seq;
  573. env_set("modeboot", "sdboot");
  574. break;
  575. case NAND_MODE:
  576. puts("NAND_MODE\n");
  577. mode = "nand0";
  578. env_set("modeboot", "nandboot");
  579. break;
  580. default:
  581. mode = "";
  582. printf("Invalid Boot Mode:0x%x\n", bootmode);
  583. break;
  584. }
  585. if (bootseq >= 0) {
  586. bootseq_len = snprintf(NULL, 0, "%i", bootseq);
  587. debug("Bootseq len: %x\n", bootseq_len);
  588. }
  589. /*
  590. * One terminating char + one byte for space between mode
  591. * and default boot_targets
  592. */
  593. env_targets = env_get("boot_targets");
  594. if (env_targets)
  595. env_targets_len = strlen(env_targets);
  596. new_targets = calloc(1, strlen(mode) + env_targets_len + 2 +
  597. bootseq_len);
  598. if (!new_targets)
  599. return -ENOMEM;
  600. if (bootseq >= 0)
  601. sprintf(new_targets, "%s%x %s", mode, bootseq,
  602. env_targets ? env_targets : "");
  603. else
  604. sprintf(new_targets, "%s %s", mode,
  605. env_targets ? env_targets : "");
  606. env_set("boot_targets", new_targets);
  607. initrd_hi = gd->start_addr_sp - CONFIG_STACK_SIZE;
  608. initrd_hi = round_down(initrd_hi, SZ_16M);
  609. env_set_addr("initrd_high", (void *)initrd_hi);
  610. reset_reason();
  611. return board_late_init_xilinx();
  612. }
  613. #endif
  614. int checkboard(void)
  615. {
  616. puts("Board: Xilinx ZynqMP\n");
  617. return 0;
  618. }