tlb.c 3.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2013 Keymile AG
  4. * Valentin Longchamp <valentin.longchamp@keymile.com>
  5. *
  6. * Copyright 2008-2011 Freescale Semiconductor, Inc.
  7. *
  8. * (C) Copyright 2000
  9. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  10. */
  11. #include <common.h>
  12. #include <asm/mmu.h>
  13. struct fsl_e_tlb_entry tlb_table[] = {
  14. /* TLB 0 - for temp stack in cache */
  15. SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
  16. CONFIG_SYS_INIT_RAM_ADDR_PHYS,
  17. MAS3_SW|MAS3_SR, 0,
  18. 0, 0, BOOKE_PAGESZ_4K, 0),
  19. SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
  20. CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
  21. MAS3_SW|MAS3_SR, 0,
  22. 0, 0, BOOKE_PAGESZ_4K, 0),
  23. SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
  24. CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
  25. MAS3_SW|MAS3_SR, 0,
  26. 0, 0, BOOKE_PAGESZ_4K, 0),
  27. SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
  28. CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
  29. MAS3_SW|MAS3_SR, 0,
  30. 0, 0, BOOKE_PAGESZ_4K, 0),
  31. /* TLB 1 */
  32. /* *I*G - L3SRAM. When L3 is used as 1M SRAM, the address of the
  33. * SRAM is at 0xfff00000, it covered the 0xfffff000.
  34. */
  35. SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
  36. MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  37. 0, 0, BOOKE_PAGESZ_1M, 1),
  38. /* *I*G* - CCSRBAR */
  39. SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
  40. MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  41. 0, 1, BOOKE_PAGESZ_16M, 1),
  42. /* QRIO */
  43. SET_TLB_ENTRY(1, CONFIG_SYS_QRIO_BASE, CONFIG_SYS_QRIO_BASE_PHYS,
  44. MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  45. 0, 2, BOOKE_PAGESZ_64K, 1),
  46. /* *I*G* - PCI1 */
  47. SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
  48. MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  49. 0, 3, BOOKE_PAGESZ_512M, 1),
  50. /* *I*G* - PCI3 */
  51. SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT, CONFIG_SYS_PCIE3_MEM_PHYS,
  52. MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  53. 0, 4, BOOKE_PAGESZ_512M, 1),
  54. /* *I*G* - PCI1&3 I/O */
  55. SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
  56. MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  57. 0, 6, BOOKE_PAGESZ_128K, 1),
  58. #ifdef CONFIG_SYS_LBAPP1_BASE_PHYS
  59. /* LBAPP1 */
  60. SET_TLB_ENTRY(1, CONFIG_SYS_LBAPP1_BASE, CONFIG_SYS_LBAPP1_BASE_PHYS,
  61. MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  62. 0, 7, BOOKE_PAGESZ_256M, 1),
  63. #endif
  64. #ifdef CONFIG_SYS_LBAPP2_BASE_PHYS
  65. /* LBAPP2 */
  66. SET_TLB_ENTRY(1, CONFIG_SYS_LBAPP2_BASE, CONFIG_SYS_LBAPP2_BASE_PHYS,
  67. MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  68. 0, 8, BOOKE_PAGESZ_256M, 1),
  69. #endif
  70. /* Bman/Qman */
  71. #ifdef CONFIG_SYS_BMAN_MEM_PHYS
  72. SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS,
  73. MAS3_SW|MAS3_SR, 0,
  74. 0, 9, BOOKE_PAGESZ_1M, 1),
  75. SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x00100000,
  76. CONFIG_SYS_BMAN_MEM_PHYS + 0x00100000,
  77. MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  78. 0, 10, BOOKE_PAGESZ_1M, 1),
  79. #endif
  80. #ifdef CONFIG_SYS_QMAN_MEM_PHYS
  81. SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS,
  82. MAS3_SW|MAS3_SR, 0,
  83. 0, 11, BOOKE_PAGESZ_1M, 1),
  84. SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x00100000,
  85. CONFIG_SYS_QMAN_MEM_PHYS + 0x00100000,
  86. MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  87. 0, 12, BOOKE_PAGESZ_1M, 1),
  88. #endif
  89. #ifdef CONFIG_SYS_DCSRBAR_PHYS
  90. SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS,
  91. MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  92. 0, 13, BOOKE_PAGESZ_4M, 1),
  93. #endif
  94. #ifdef CONFIG_SYS_NAND_BASE
  95. /*
  96. * *I*G - NAND
  97. * entry 14 and 15 has been used hard coded, they will be disabled
  98. * in cpu_init_f, so we use entry 16 for nand.
  99. */
  100. SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
  101. MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  102. 0, 16, BOOKE_PAGESZ_32K, 1),
  103. #endif
  104. };
  105. int num_tlb_entries = ARRAY_SIZE(tlb_table);