kmp204x.c 6.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2013 Keymile AG
  4. * Valentin Longchamp <valentin.longchamp@keymile.com>
  5. *
  6. * Copyright 2011,2012 Freescale Semiconductor, Inc.
  7. */
  8. #include <common.h>
  9. #include <command.h>
  10. #include <env.h>
  11. #include <fdt_support.h>
  12. #include <image.h>
  13. #include <init.h>
  14. #include <netdev.h>
  15. #include <linux/compiler.h>
  16. #include <asm/mmu.h>
  17. #include <asm/processor.h>
  18. #include <asm/cache.h>
  19. #include <asm/immap_85xx.h>
  20. #include <asm/fsl_law.h>
  21. #include <asm/fsl_serdes.h>
  22. #include <asm/fsl_portals.h>
  23. #include <asm/fsl_liodn.h>
  24. #include <fm_eth.h>
  25. #include "../common/common.h"
  26. #include "../common/qrio.h"
  27. #include "kmp204x.h"
  28. static uchar ivm_content[CONFIG_SYS_IVM_EEPROM_MAX_LEN];
  29. int checkboard(void)
  30. {
  31. printf("Board: Keymile %s\n", CONFIG_SYS_CONFIG_NAME);
  32. return 0;
  33. }
  34. #define ZL30158_RST 8
  35. #define BFTIC4_RST 0
  36. #define RSTRQSR1_WDT_RR 0x00200000
  37. #define RSTRQSR1_SW_RR 0x00100000
  38. int board_early_init_f(void)
  39. {
  40. ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  41. bool cpuwd_flag = false;
  42. /* configure mode for uP reset request */
  43. qrio_uprstreq(UPREQ_CORE_RST);
  44. /* board only uses the DDR_MCK0, so disable the DDR_MCK1/2/3 */
  45. setbits_be32(&gur->ddrclkdr, 0x001f000f);
  46. /* set reset reason according CPU register */
  47. if ((gur->rstrqsr1 & (RSTRQSR1_WDT_RR | RSTRQSR1_SW_RR)) ==
  48. RSTRQSR1_WDT_RR)
  49. cpuwd_flag = true;
  50. qrio_cpuwd_flag(cpuwd_flag);
  51. /* clear CPU bits by writing 1 */
  52. setbits_be32(&gur->rstrqsr1, RSTRQSR1_WDT_RR | RSTRQSR1_SW_RR);
  53. /* set the BFTIC's prstcfg to reset at power-up and unit reset only */
  54. qrio_prstcfg(BFTIC4_RST, PRSTCFG_POWUP_UNIT_RST);
  55. /* and enable WD on it */
  56. qrio_wdmask(BFTIC4_RST, true);
  57. /* set the ZL30138's prstcfg to reset at power-up only */
  58. qrio_prstcfg(ZL30158_RST, PRSTCFG_POWUP_RST);
  59. /* and take it out of reset as soon as possible (needed for Hooper) */
  60. qrio_prst(ZL30158_RST, false, false);
  61. return 0;
  62. }
  63. int board_early_init_r(void)
  64. {
  65. int ret = 0;
  66. /* Flush d-cache and invalidate i-cache of any FLASH data */
  67. flush_dcache();
  68. invalidate_icache();
  69. set_liodns();
  70. setup_qbman_portals();
  71. ret = trigger_fpga_config();
  72. if (ret)
  73. printf("error triggering PCIe FPGA config\n");
  74. /* enable the Unit LED (red) & Boot LED (on) */
  75. qrio_set_leds();
  76. /* enable Application Buffer */
  77. qrio_enable_app_buffer();
  78. return 0;
  79. }
  80. unsigned long get_board_sys_clk(unsigned long dummy)
  81. {
  82. return 66666666;
  83. }
  84. #define ETH_FRONT_PHY_RST 15
  85. #define QSFP2_RST 11
  86. #define QSFP1_RST 10
  87. #define ZL30343_RST 9
  88. int misc_init_f(void)
  89. {
  90. /* configure QRIO pis for i2c deblocking */
  91. i2c_deblock_gpio_cfg();
  92. /* configure the front phy's prstcfg and take it out of reset */
  93. qrio_prstcfg(ETH_FRONT_PHY_RST, PRSTCFG_POWUP_UNIT_CORE_RST);
  94. qrio_prst(ETH_FRONT_PHY_RST, false, false);
  95. /* set the ZL30343 prstcfg to reset at power-up only */
  96. qrio_prstcfg(ZL30343_RST, PRSTCFG_POWUP_RST);
  97. /* and enable the WD on it */
  98. qrio_wdmask(ZL30343_RST, true);
  99. /* set the QSFPs' prstcfg to reset at power-up and unit rst only */
  100. qrio_prstcfg(QSFP1_RST, PRSTCFG_POWUP_UNIT_RST);
  101. qrio_prstcfg(QSFP2_RST, PRSTCFG_POWUP_UNIT_RST);
  102. /* and enable the WD on them */
  103. qrio_wdmask(QSFP1_RST, true);
  104. qrio_wdmask(QSFP2_RST, true);
  105. return 0;
  106. }
  107. #define NUM_SRDS_BANKS 2
  108. int misc_init_r(void)
  109. {
  110. serdes_corenet_t *regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
  111. u32 expected[NUM_SRDS_BANKS] = {SRDS_PLLCR0_RFCK_SEL_100,
  112. SRDS_PLLCR0_RFCK_SEL_125};
  113. unsigned int i;
  114. /* check SERDES reference clocks */
  115. for (i = 0; i < NUM_SRDS_BANKS; i++) {
  116. u32 actual = in_be32(&regs->bank[i].pllcr0);
  117. actual &= SRDS_PLLCR0_RFCK_SEL_MASK;
  118. if (actual != expected[i]) {
  119. printf("Warning: SERDES bank %u expects reference \
  120. clock %sMHz, but actual is %sMHz\n", i + 1,
  121. serdes_clock_to_string(expected[i]),
  122. serdes_clock_to_string(actual));
  123. }
  124. }
  125. ivm_read_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN,
  126. CONFIG_PIGGY_MAC_ADDRESS_OFFSET);
  127. return 0;
  128. }
  129. #if defined(CONFIG_HUSH_INIT_VAR)
  130. int hush_init_var(void)
  131. {
  132. ivm_analyze_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN);
  133. return 0;
  134. }
  135. #endif
  136. #if defined(CONFIG_LAST_STAGE_INIT)
  137. int last_stage_init(void)
  138. {
  139. #if defined(CONFIG_KMCOGE4)
  140. /* on KMCOGE4, the BFTIC4 is on the LBAPP2 */
  141. struct bfticu_iomap *bftic4 =
  142. (struct bfticu_iomap *)CONFIG_SYS_LBAPP2_BASE;
  143. u8 dip_switch = in_8((u8 *)&(bftic4->mswitch)) & BFTICU_DIPSWITCH_MASK;
  144. if (dip_switch != 0) {
  145. /* start bootloader */
  146. puts("DIP: Enabled\n");
  147. env_set("actual_bank", "0");
  148. }
  149. #endif
  150. set_km_env();
  151. return 0;
  152. }
  153. #endif
  154. #ifdef CONFIG_SYS_DPAA_FMAN
  155. void fdt_fixup_fman_mac_addresses(void *blob)
  156. {
  157. int node, i, ret;
  158. char *tmp, *end;
  159. unsigned char mac_addr[6];
  160. /* get the mac addr from env */
  161. tmp = env_get("ethaddr");
  162. if (!tmp) {
  163. printf("ethaddr env variable not defined\n");
  164. return;
  165. }
  166. for (i = 0; i < 6; i++) {
  167. mac_addr[i] = tmp ? simple_strtoul(tmp, &end, 16) : 0;
  168. if (tmp)
  169. tmp = (*end) ? end+1 : end;
  170. }
  171. /* find the correct fdt ethernet path and correct it */
  172. node = fdt_path_offset(blob, "/soc/fman/ethernet@e8000");
  173. if (node < 0) {
  174. printf("no /soc/fman/ethernet path offset\n");
  175. return;
  176. }
  177. ret = fdt_setprop(blob, node, "local-mac-address", &mac_addr, 6);
  178. if (ret) {
  179. printf("error setting local-mac-address property\n");
  180. return;
  181. }
  182. }
  183. #endif
  184. int ft_board_setup(void *blob, struct bd_info *bd)
  185. {
  186. phys_addr_t base;
  187. phys_size_t size;
  188. ft_cpu_setup(blob, bd);
  189. base = env_get_bootm_low();
  190. size = env_get_bootm_size();
  191. fdt_fixup_memory(blob, (u64)base, (u64)size);
  192. #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB)
  193. fsl_fdt_fixup_dr_usb(blob, bd);
  194. #endif
  195. #ifdef CONFIG_PCI
  196. pci_of_setup(blob, bd);
  197. #endif
  198. fdt_fixup_liodn(blob);
  199. #ifdef CONFIG_SYS_DPAA_FMAN
  200. fdt_fixup_fman_ethernet(blob);
  201. fdt_fixup_fman_mac_addresses(blob);
  202. #endif
  203. return 0;
  204. }
  205. #if defined(CONFIG_POST)
  206. /* DIC26_SELFTEST GPIO used to start factory test sw */
  207. #define SELFTEST_PORT QRIO_GPIO_A
  208. #define SELFTEST_PIN 31
  209. int post_hotkeys_pressed(void)
  210. {
  211. qrio_gpio_direction_input(SELFTEST_PORT, SELFTEST_PIN);
  212. return qrio_get_gpio(SELFTEST_PORT, SELFTEST_PIN);
  213. }
  214. #endif