ddr.c 1.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2013 Keymile AG
  4. * Valentin Longchamp <valentin.longchamp@keymile.com>
  5. *
  6. * Copyright 2009-2011 Freescale Semiconductor, Inc.
  7. */
  8. #include <common.h>
  9. #include <i2c.h>
  10. #include <hwconfig.h>
  11. #include <init.h>
  12. #include <log.h>
  13. #include <asm/global_data.h>
  14. #include <asm/mmu.h>
  15. #include <fsl_ddr_sdram.h>
  16. #include <fsl_ddr_dimm_params.h>
  17. DECLARE_GLOBAL_DATA_PTR;
  18. void fsl_ddr_board_options(memctl_options_t *popts,
  19. dimm_params_t *pdimm,
  20. unsigned int ctrl_num)
  21. {
  22. if (ctrl_num) {
  23. printf("Wrong parameter for controller number %d", ctrl_num);
  24. return;
  25. }
  26. /* automatic calibration for nb of cycles between read and DQS pre */
  27. popts->cpo_override = 0xFF;
  28. /* 1/2 clk delay between wr command and data strobe */
  29. popts->write_data_delay = 4;
  30. /* clk lauched 1/2 applied cylcle after address command */
  31. popts->clk_adjust = 4;
  32. /* 1T timing: command/address held for only 1 cycle */
  33. popts->twot_en = 0;
  34. /* we have only one module, half str should be OK */
  35. popts->half_strength_driver_enable = 1;
  36. /* wrlvl values overridden as recommended by ddr init func */
  37. popts->wrlvl_override = 1;
  38. popts->wrlvl_sample = 0xf;
  39. popts->wrlvl_start = 0x6;
  40. /* Enable ZQ calibration */
  41. popts->zq_en = 1;
  42. /* DHC_EN =1, ODT = 75 Ohm */
  43. popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR_ODT_75ohm;
  44. }
  45. int dram_init(void)
  46. {
  47. phys_size_t dram_size = 0;
  48. puts("Initializing with SPD\n");
  49. dram_size = fsl_ddr_sdram();
  50. dram_size = setup_ddr_tlbs(dram_size / 0x100000);
  51. dram_size *= 0x100000;
  52. debug(" DDR: ");
  53. gd->ram_size = dram_size;
  54. return 0;
  55. }