Kconfig 14 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491
  1. #
  2. # I2C subsystem configuration
  3. #
  4. menu "I2C support"
  5. config DM_I2C
  6. bool "Enable Driver Model for I2C drivers"
  7. depends on DM
  8. help
  9. Enable driver model for I2C. The I2C uclass interface: probe, read,
  10. write and speed, is implemented with the bus drivers operations,
  11. which provide methods for bus setting and data transfer. Each chip
  12. device (bus child) info is kept as parent platdata. The interface
  13. is defined in include/i2c.h.
  14. config I2C_CROS_EC_TUNNEL
  15. tristate "Chrome OS EC tunnel I2C bus"
  16. depends on CROS_EC
  17. help
  18. This provides an I2C bus that will tunnel i2c commands through to
  19. the other side of the Chrome OS EC to the I2C bus connected there.
  20. This will work whatever the interface used to talk to the EC (SPI,
  21. I2C or LPC). Some Chromebooks use this when the hardware design
  22. does not allow direct access to the main PMIC from the AP.
  23. config I2C_CROS_EC_LDO
  24. bool "Provide access to LDOs on the Chrome OS EC"
  25. depends on CROS_EC
  26. ---help---
  27. On many Chromebooks the main PMIC is inaccessible to the AP. This is
  28. often dealt with by using an I2C pass-through interface provided by
  29. the EC. On some unfortunate models (e.g. Spring) the pass-through
  30. is not available, and an LDO message is available instead. This
  31. option enables a driver which provides very basic access to those
  32. regulators, via the EC. We implement this as an I2C bus which
  33. emulates just the TPS65090 messages we know about. This is done to
  34. avoid duplicating the logic in the TPS65090 regulator driver for
  35. enabling/disabling an LDO.
  36. config I2C_SET_DEFAULT_BUS_NUM
  37. bool "Set default I2C bus number"
  38. depends on DM_I2C
  39. help
  40. Set default number of I2C bus to be accessed. This option provides
  41. behaviour similar to old (i.e. pre DM) I2C bus driver.
  42. config I2C_DEFAULT_BUS_NUMBER
  43. hex "I2C default bus number"
  44. depends on I2C_SET_DEFAULT_BUS_NUM
  45. default 0x0
  46. help
  47. Number of default I2C bus to use
  48. config DM_I2C_GPIO
  49. bool "Enable Driver Model for software emulated I2C bus driver"
  50. depends on DM_I2C && DM_GPIO
  51. help
  52. Enable the i2c bus driver emulation by using the GPIOs. The bus GPIO
  53. configuration is given by the device tree. Kernel-style device tree
  54. bindings are supported.
  55. Binding info: doc/device-tree-bindings/i2c/i2c-gpio.txt
  56. config SYS_I2C_AT91
  57. bool "Atmel I2C driver"
  58. depends on DM_I2C && ARCH_AT91
  59. help
  60. Add support for the Atmel I2C driver. A serious problem is that there
  61. is no documented way to issue repeated START conditions for more than
  62. two messages, as needed to support combined I2C messages. Use the
  63. i2c-gpio driver unless your system can cope with this limitation.
  64. Binding info: doc/device-tree-bindings/i2c/i2c-at91.txt
  65. config SYS_I2C_IPROC
  66. bool "Broadcom I2C driver"
  67. depends on DM_I2C
  68. help
  69. Broadcom I2C driver.
  70. Add support for Broadcom I2C driver.
  71. Say yes here to to enable the Broadco I2C driver.
  72. config SYS_I2C_FSL
  73. bool "Freescale I2C bus driver"
  74. depends on DM_I2C
  75. help
  76. Add support for Freescale I2C busses as used on MPC8240, MPC8245, and
  77. MPC85xx processors.
  78. config SYS_I2C_CADENCE
  79. tristate "Cadence I2C Controller"
  80. depends on DM_I2C && (ARCH_ZYNQ || ARM64)
  81. help
  82. Say yes here to select Cadence I2C Host Controller. This controller is
  83. e.g. used by Xilinx Zynq.
  84. config SYS_I2C_CA
  85. tristate "Cortina-Access I2C Controller"
  86. depends on DM_I2C && CORTINA_PLATFORM
  87. default n
  88. help
  89. Add support for the Cortina Access I2C host controller.
  90. Say yes here to select Cortina-Access I2C Host Controller.
  91. config SYS_I2C_DAVINCI
  92. bool "Davinci I2C Controller"
  93. depends on (ARCH_KEYSTONE || ARCH_DAVINCI)
  94. help
  95. Say yes here to add support for Davinci and Keystone I2C controller
  96. config SYS_I2C_DW
  97. bool "Designware I2C Controller"
  98. default n
  99. help
  100. Say yes here to select the Designware I2C Host Controller. This
  101. controller is used in various SoCs, e.g. the ST SPEAr, Altera
  102. SoCFPGA, Synopsys ARC700 and some Intel x86 SoCs.
  103. config SYS_I2C_DW_ENABLE_STATUS_UNSUPPORTED
  104. bool "DW I2C Enable Status Register not supported"
  105. depends on SYS_I2C_DW && (TARGET_SPEAR300 || TARGET_SPEAR310 || \
  106. TARGET_SPEAR320 || TARGET_SPEAR600 || TARGET_X600)
  107. default y
  108. help
  109. Some versions of the Designware I2C controller do not support the
  110. enable status register. This config option can be enabled in such
  111. cases.
  112. config SYS_I2C_ASPEED
  113. bool "Aspeed I2C Controller"
  114. depends on DM_I2C && ARCH_ASPEED
  115. help
  116. Say yes here to select Aspeed I2C Host Controller. The driver
  117. supports AST2500 and AST2400 controllers, but is very limited.
  118. Only single master mode is supported and only byte-by-byte
  119. synchronous reads and writes are supported, no Pool Buffers or DMA.
  120. config SYS_I2C_INTEL
  121. bool "Intel I2C/SMBUS driver"
  122. depends on DM_I2C
  123. help
  124. Add support for the Intel SMBUS driver. So far this driver is just
  125. a stub which perhaps some basic init. There is no implementation of
  126. the I2C API meaning that any I2C operations will immediately fail
  127. for now.
  128. config SYS_I2C_IMX_LPI2C
  129. bool "NXP i.MX LPI2C driver"
  130. help
  131. Add support for the NXP i.MX LPI2C driver.
  132. config SYS_I2C_MESON
  133. bool "Amlogic Meson I2C driver"
  134. depends on DM_I2C && ARCH_MESON
  135. help
  136. Add support for the I2C controller available in Amlogic Meson
  137. SoCs. The controller supports programmable bus speed including
  138. standard (100kbits/s) and fast (400kbit/s) speed and allows the
  139. software to define a flexible format of the bit streams. It has an
  140. internal buffer holding up to 8 bytes for transfers and supports
  141. both 7-bit and 10-bit addresses.
  142. config SYS_I2C_MXC
  143. bool "NXP MXC I2C driver"
  144. help
  145. Add support for the NXP I2C driver. This supports up to four bus
  146. channels and operating on standard mode up to 100 kbits/s and fast
  147. mode up to 400 kbits/s.
  148. # These settings are not used with DM_I2C, however SPL doesn't use
  149. # DM_I2C even if DM_I2C is enabled, and so might use these settings even
  150. # when main u-boot does not!
  151. if SYS_I2C_MXC && (!DM_I2C || SPL)
  152. config SYS_I2C_MXC_I2C1
  153. bool "NXP MXC I2C1"
  154. help
  155. Add support for NXP MXC I2C Controller 1.
  156. Required for SoCs which have I2C MXC controller 1 eg LS1088A, LS2080A
  157. config SYS_I2C_MXC_I2C2
  158. bool "NXP MXC I2C2"
  159. help
  160. Add support for NXP MXC I2C Controller 2.
  161. Required for SoCs which have I2C MXC controller 2 eg LS1088A, LS2080A
  162. config SYS_I2C_MXC_I2C3
  163. bool "NXP MXC I2C3"
  164. help
  165. Add support for NXP MXC I2C Controller 3.
  166. Required for SoCs which have I2C MXC controller 3 eg LS1088A, LS2080A
  167. config SYS_I2C_MXC_I2C4
  168. bool "NXP MXC I2C4"
  169. help
  170. Add support for NXP MXC I2C Controller 4.
  171. Required for SoCs which have I2C MXC controller 4 eg LS1088A, LS2080A
  172. config SYS_I2C_MXC_I2C5
  173. bool "NXP MXC I2C5"
  174. help
  175. Add support for NXP MXC I2C Controller 5.
  176. Required for SoCs which have I2C MXC controller 5 eg LX2160A
  177. config SYS_I2C_MXC_I2C6
  178. bool "NXP MXC I2C6"
  179. help
  180. Add support for NXP MXC I2C Controller 6.
  181. Required for SoCs which have I2C MXC controller 6 eg LX2160A
  182. config SYS_I2C_MXC_I2C7
  183. bool "NXP MXC I2C7"
  184. help
  185. Add support for NXP MXC I2C Controller 7.
  186. Required for SoCs which have I2C MXC controller 7 eg LX2160A
  187. config SYS_I2C_MXC_I2C8
  188. bool "NXP MXC I2C8"
  189. help
  190. Add support for NXP MXC I2C Controller 8.
  191. Required for SoCs which have I2C MXC controller 8 eg LX2160A
  192. endif
  193. if SYS_I2C_MXC_I2C1
  194. config SYS_MXC_I2C1_SPEED
  195. int "I2C Channel 1 speed"
  196. default 40000000 if TARGET_LS2080A_SIMU || TARGET_LS2080A_EMU
  197. default 100000
  198. help
  199. MXC I2C Channel 1 speed
  200. config SYS_MXC_I2C1_SLAVE
  201. int "I2C1 Slave"
  202. default 0
  203. help
  204. MXC I2C1 Slave
  205. endif
  206. if SYS_I2C_MXC_I2C2
  207. config SYS_MXC_I2C2_SPEED
  208. int "I2C Channel 2 speed"
  209. default 40000000 if TARGET_LS2080A_SIMU || TARGET_LS2080A_EMU
  210. default 100000
  211. help
  212. MXC I2C Channel 2 speed
  213. config SYS_MXC_I2C2_SLAVE
  214. int "I2C2 Slave"
  215. default 0
  216. help
  217. MXC I2C2 Slave
  218. endif
  219. if SYS_I2C_MXC_I2C3
  220. config SYS_MXC_I2C3_SPEED
  221. int "I2C Channel 3 speed"
  222. default 100000
  223. help
  224. MXC I2C Channel 3 speed
  225. config SYS_MXC_I2C3_SLAVE
  226. int "I2C3 Slave"
  227. default 0
  228. help
  229. MXC I2C3 Slave
  230. endif
  231. if SYS_I2C_MXC_I2C4
  232. config SYS_MXC_I2C4_SPEED
  233. int "I2C Channel 4 speed"
  234. default 100000
  235. help
  236. MXC I2C Channel 4 speed
  237. config SYS_MXC_I2C4_SLAVE
  238. int "I2C4 Slave"
  239. default 0
  240. help
  241. MXC I2C4 Slave
  242. endif
  243. if SYS_I2C_MXC_I2C5
  244. config SYS_MXC_I2C5_SPEED
  245. int "I2C Channel 5 speed"
  246. default 100000
  247. help
  248. MXC I2C Channel 5 speed
  249. config SYS_MXC_I2C5_SLAVE
  250. int "I2C5 Slave"
  251. default 0
  252. help
  253. MXC I2C5 Slave
  254. endif
  255. if SYS_I2C_MXC_I2C6
  256. config SYS_MXC_I2C6_SPEED
  257. int "I2C Channel 6 speed"
  258. default 100000
  259. help
  260. MXC I2C Channel 6 speed
  261. config SYS_MXC_I2C6_SLAVE
  262. int "I2C6 Slave"
  263. default 0
  264. help
  265. MXC I2C6 Slave
  266. endif
  267. if SYS_I2C_MXC_I2C7
  268. config SYS_MXC_I2C7_SPEED
  269. int "I2C Channel 7 speed"
  270. default 100000
  271. help
  272. MXC I2C Channel 7 speed
  273. config SYS_MXC_I2C7_SLAVE
  274. int "I2C7 Slave"
  275. default 0
  276. help
  277. MXC I2C7 Slave
  278. endif
  279. if SYS_I2C_MXC_I2C8
  280. config SYS_MXC_I2C8_SPEED
  281. int "I2C Channel 8 speed"
  282. default 100000
  283. help
  284. MXC I2C Channel 8 speed
  285. config SYS_MXC_I2C8_SLAVE
  286. int "I2C8 Slave"
  287. default 0
  288. help
  289. MXC I2C8 Slave
  290. endif
  291. config SYS_I2C_OMAP24XX
  292. bool "TI OMAP2+ I2C driver"
  293. depends on ARCH_OMAP2PLUS || ARCH_K3
  294. help
  295. Add support for the OMAP2+ I2C driver.
  296. if SYS_I2C_OMAP24XX
  297. config SYS_OMAP24_I2C_SLAVE
  298. int "I2C Slave addr channel 0"
  299. default 1
  300. help
  301. OMAP24xx I2C Slave address channel 0
  302. config SYS_OMAP24_I2C_SPEED
  303. int "I2C Slave channel 0 speed"
  304. default 100000
  305. help
  306. OMAP24xx Slave speed channel 0
  307. endif
  308. config SYS_I2C_RCAR_I2C
  309. bool "Renesas RCar I2C driver"
  310. depends on (RCAR_GEN3 || RCAR_GEN2) && DM_I2C
  311. help
  312. Support for Renesas RCar I2C controller.
  313. config SYS_I2C_RCAR_IIC
  314. bool "Renesas RCar Gen3 IIC driver"
  315. depends on (RCAR_GEN3 || RCAR_GEN2) && DM_I2C
  316. help
  317. Support for Renesas RCar Gen3 IIC controller.
  318. config SYS_I2C_ROCKCHIP
  319. bool "Rockchip I2C driver"
  320. depends on DM_I2C
  321. help
  322. Add support for the Rockchip I2C driver. This is used with various
  323. Rockchip parts such as RK3126, RK3128, RK3036 and RK3288. All chips
  324. have several I2C ports and all are provided, controlled by the
  325. device tree.
  326. config SYS_I2C_SANDBOX
  327. bool "Sandbox I2C driver"
  328. depends on SANDBOX && DM_I2C
  329. help
  330. Enable I2C support for sandbox. This is an emulation of a real I2C
  331. bus. Devices can be attached to the bus using the device tree
  332. which specifies the driver to use. See sandbox.dts as an example.
  333. config SYS_I2C_OCTEON
  334. bool "Octeon II/III/TX/TX2 I2C driver"
  335. depends on (ARCH_OCTEON || ARCH_OCTEONTX || ARCH_OCTEONTX2) && DM_I2C
  336. default y
  337. help
  338. Add support for the Marvell Octeon I2C driver. This is used with
  339. various Octeon parts such as Octeon II/III and OcteonTX/TX2. All
  340. chips have several I2C ports and all are provided, controlled by
  341. the device tree.
  342. config SYS_I2C_S3C24X0
  343. bool "Samsung I2C driver"
  344. depends on ARCH_EXYNOS4 && DM_I2C
  345. help
  346. Support for Samsung I2C controller as Samsung SoCs.
  347. config SYS_I2C_STM32F7
  348. bool "STMicroelectronics STM32F7 I2C support"
  349. depends on (STM32F7 || STM32H7 || ARCH_STM32MP) && DM_I2C
  350. help
  351. Enable this option to add support for STM32 I2C controller
  352. introduced with STM32F7/H7 SoCs. This I2C controller supports :
  353. _ Slave and master modes
  354. _ Multimaster capability
  355. _ Standard-mode (up to 100 kHz)
  356. _ Fast-mode (up to 400 kHz)
  357. _ Fast-mode Plus (up to 1 MHz)
  358. _ 7-bit and 10-bit addressing mode
  359. _ Multiple 7-bit slave addresses (2 addresses, 1 with configurable mask)
  360. _ All 7-bit addresses acknowledge mode
  361. _ General call
  362. _ Programmable setup and hold times
  363. _ Easy to use event management
  364. _ Optional clock stretching
  365. _ Software reset
  366. config SYS_I2C_TEGRA
  367. bool "NVIDIA Tegra internal I2C controller"
  368. depends on ARCH_TEGRA
  369. help
  370. Support for NVIDIA I2C controller available in Tegra SoCs.
  371. config SYS_I2C_UNIPHIER
  372. bool "UniPhier I2C driver"
  373. depends on ARCH_UNIPHIER && DM_I2C
  374. default y
  375. help
  376. Support for UniPhier I2C controller driver. This I2C controller
  377. is used on PH1-LD4, PH1-sLD8 or older UniPhier SoCs.
  378. config SYS_I2C_UNIPHIER_F
  379. bool "UniPhier FIFO-builtin I2C driver"
  380. depends on ARCH_UNIPHIER && DM_I2C
  381. default y
  382. help
  383. Support for UniPhier FIFO-builtin I2C controller driver.
  384. This I2C controller is used on PH1-Pro4 or newer UniPhier SoCs.
  385. config SYS_I2C_VERSATILE
  386. bool "Arm Ltd Versatile I2C bus driver"
  387. depends on DM_I2C && (TARGET_VEXPRESS_CA15_TC2 || TARGET_VEXPRESS64_JUNO)
  388. help
  389. Add support for the Arm Ltd Versatile Express I2C driver. The I2C host
  390. controller is present in the development boards manufactured by Arm Ltd.
  391. config SYS_I2C_MVTWSI
  392. bool "Marvell I2C driver"
  393. depends on DM_I2C
  394. help
  395. Support for Marvell I2C controllers as used on the orion5x and
  396. kirkwood SoC families.
  397. config TEGRA186_BPMP_I2C
  398. bool "Enable Tegra186 BPMP-based I2C driver"
  399. depends on TEGRA186_BPMP
  400. help
  401. Support for Tegra I2C controllers managed by the BPMP (Boot and
  402. Power Management Processor). On Tegra186, some I2C controllers are
  403. directly controlled by the main CPU, whereas others are controlled
  404. by the BPMP, and can only be accessed by the main CPU via IPC
  405. requests to the BPMP. This driver covers the latter case.
  406. config SYS_I2C_BUS_MAX
  407. int "Max I2C busses"
  408. depends on ARCH_KEYSTONE || ARCH_OMAP2PLUS || ARCH_SOCFPGA
  409. default 2 if TI816X
  410. default 3 if OMAP34XX || AM33XX || AM43XX || ARCH_KEYSTONE
  411. default 4 if ARCH_SOCFPGA || OMAP44XX || TI814X
  412. default 5 if OMAP54XX
  413. help
  414. Define the maximum number of available I2C buses.
  415. config SYS_I2C_XILINX_XIIC
  416. bool "Xilinx AXI I2C driver"
  417. depends on DM_I2C
  418. help
  419. Support for Xilinx AXI I2C controller.
  420. config SYS_I2C_IHS
  421. bool "gdsys IHS I2C driver"
  422. depends on DM_I2C
  423. help
  424. Support for gdsys IHS I2C driver on FPGA bus.
  425. source "drivers/i2c/muxes/Kconfig"
  426. endmenu