spl.c 5.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (c) 2016 Google, Inc
  4. */
  5. #include <common.h>
  6. #include <cpu_func.h>
  7. #include <debug_uart.h>
  8. #include <dm.h>
  9. #include <hang.h>
  10. #include <image.h>
  11. #include <init.h>
  12. #include <irq_func.h>
  13. #include <log.h>
  14. #include <malloc.h>
  15. #include <spl.h>
  16. #include <syscon.h>
  17. #include <asm/cpu.h>
  18. #include <asm/cpu_common.h>
  19. #include <asm/mrccache.h>
  20. #include <asm/mtrr.h>
  21. #include <asm/pci.h>
  22. #include <asm/processor.h>
  23. #include <asm/spl.h>
  24. #include <asm-generic/sections.h>
  25. DECLARE_GLOBAL_DATA_PTR;
  26. __weak int arch_cpu_init_dm(void)
  27. {
  28. return 0;
  29. }
  30. #ifdef CONFIG_TPL
  31. static int set_max_freq(void)
  32. {
  33. if (cpu_get_burst_mode_state() == BURST_MODE_UNAVAILABLE) {
  34. /*
  35. * Burst Mode has been factory-configured as disabled and is not
  36. * available in this physical processor package
  37. */
  38. debug("Burst Mode is factory-disabled\n");
  39. return -ENOENT;
  40. }
  41. /* Enable burst mode */
  42. cpu_set_burst_mode(true);
  43. /* Enable speed step */
  44. cpu_set_eist(true);
  45. /* Set P-State ratio */
  46. cpu_set_p_state_to_turbo_ratio();
  47. return 0;
  48. }
  49. #endif
  50. static int x86_spl_init(void)
  51. {
  52. #ifndef CONFIG_TPL
  53. /*
  54. * TODO(sjg@chromium.org): We use this area of RAM for the stack
  55. * and global_data in SPL. Once U-Boot starts up and releocates it
  56. * is not needed. We could make this a CONFIG option or perhaps
  57. * place it immediately below CONFIG_SYS_TEXT_BASE.
  58. */
  59. __maybe_unused char *ptr = (char *)0x110000;
  60. #else
  61. struct udevice *punit;
  62. #endif
  63. int ret;
  64. debug("%s starting\n", __func__);
  65. if (IS_ENABLED(TPL))
  66. ret = x86_cpu_reinit_f();
  67. else
  68. ret = x86_cpu_init_f();
  69. ret = spl_init();
  70. if (ret) {
  71. debug("%s: spl_init() failed\n", __func__);
  72. return ret;
  73. }
  74. ret = arch_cpu_init();
  75. if (ret) {
  76. debug("%s: arch_cpu_init() failed\n", __func__);
  77. return ret;
  78. }
  79. #ifndef CONFIG_TPL
  80. ret = arch_cpu_init_dm();
  81. if (ret) {
  82. debug("%s: arch_cpu_init_dm() failed\n", __func__);
  83. return ret;
  84. }
  85. #endif
  86. preloader_console_init();
  87. #ifndef CONFIG_TPL
  88. ret = print_cpuinfo();
  89. if (ret) {
  90. debug("%s: print_cpuinfo() failed\n", __func__);
  91. return ret;
  92. }
  93. #endif
  94. ret = dram_init();
  95. if (ret) {
  96. debug("%s: dram_init() failed\n", __func__);
  97. return ret;
  98. }
  99. if (IS_ENABLED(CONFIG_ENABLE_MRC_CACHE)) {
  100. ret = mrccache_spl_save();
  101. if (ret)
  102. debug("%s: Failed to write to mrccache (err=%d)\n",
  103. __func__, ret);
  104. }
  105. #ifndef CONFIG_SYS_COREBOOT
  106. memset(&__bss_start, 0, (ulong)&__bss_end - (ulong)&__bss_start);
  107. # ifndef CONFIG_TPL
  108. /* TODO(sjg@chromium.org): Consider calling cpu_init_r() here */
  109. ret = interrupt_init();
  110. if (ret) {
  111. debug("%s: interrupt_init() failed\n", __func__);
  112. return ret;
  113. }
  114. /*
  115. * The stack grows down from ptr. Put the global data at ptr. This
  116. * will only be used for SPL. Once SPL loads U-Boot proper it will
  117. * set up its own stack.
  118. */
  119. gd->new_gd = (struct global_data *)ptr;
  120. memcpy(gd->new_gd, gd, sizeof(*gd));
  121. arch_setup_gd(gd->new_gd);
  122. gd->start_addr_sp = (ulong)ptr;
  123. /* Cache the SPI flash. Otherwise copying the code to RAM takes ages */
  124. ret = mtrr_add_request(MTRR_TYPE_WRBACK,
  125. (1ULL << 32) - CONFIG_XIP_ROM_SIZE,
  126. CONFIG_XIP_ROM_SIZE);
  127. if (ret) {
  128. debug("%s: SPI cache setup failed (err=%d)\n", __func__, ret);
  129. return ret;
  130. }
  131. mtrr_commit(true);
  132. # else
  133. ret = syscon_get_by_driver_data(X86_SYSCON_PUNIT, &punit);
  134. if (ret)
  135. debug("Could not find PUNIT (err=%d)\n", ret);
  136. ret = set_max_freq();
  137. if (ret)
  138. debug("Failed to set CPU frequency (err=%d)\n", ret);
  139. # endif
  140. #endif
  141. return 0;
  142. }
  143. void board_init_f(ulong flags)
  144. {
  145. int ret;
  146. ret = x86_spl_init();
  147. if (ret) {
  148. printf("x86_spl_init: error %d\n", ret);
  149. hang();
  150. }
  151. #if IS_ENABLED(CONFIG_TPL) || IS_ENABLED(CONFIG_SYS_COREBOOT)
  152. gd->bd = malloc(sizeof(*gd->bd));
  153. if (!gd->bd) {
  154. printf("Out of memory for bd_info size %x\n", sizeof(*gd->bd));
  155. hang();
  156. }
  157. board_init_r(gd, 0);
  158. #else
  159. /* Uninit CAR and jump to board_init_f_r() */
  160. board_init_f_r_trampoline(gd->start_addr_sp);
  161. #endif
  162. }
  163. void board_init_f_r(void)
  164. {
  165. init_cache_f_r();
  166. gd->flags &= ~GD_FLG_SERIAL_READY;
  167. debug("cache status %d\n", dcache_status());
  168. board_init_r(gd, 0);
  169. }
  170. u32 spl_boot_device(void)
  171. {
  172. return BOOT_DEVICE_SPI_MMAP;
  173. }
  174. int spl_start_uboot(void)
  175. {
  176. return 0;
  177. }
  178. void spl_board_announce_boot_device(void)
  179. {
  180. printf("SPI flash");
  181. }
  182. static int spl_board_load_image(struct spl_image_info *spl_image,
  183. struct spl_boot_device *bootdev)
  184. {
  185. spl_image->size = CONFIG_SYS_MONITOR_LEN;
  186. spl_image->entry_point = CONFIG_SYS_TEXT_BASE;
  187. spl_image->load_addr = CONFIG_SYS_TEXT_BASE;
  188. spl_image->os = IH_OS_U_BOOT;
  189. spl_image->name = "U-Boot";
  190. if (!IS_ENABLED(CONFIG_SYS_COREBOOT)) {
  191. /*
  192. * Copy U-Boot from ROM
  193. * TODO(sjg@chromium.org): Figure out a way to get the text base
  194. * correctly here, and in the device-tree binman definition.
  195. *
  196. * Also consider using FIT so we get the correct image length
  197. * and parameters.
  198. */
  199. memcpy((char *)spl_image->load_addr, (char *)0xfff00000,
  200. 0x100000);
  201. }
  202. debug("Loading to %lx\n", spl_image->load_addr);
  203. return 0;
  204. }
  205. SPL_LOAD_IMAGE_METHOD("SPI", 5, BOOT_DEVICE_SPI_MMAP, spl_board_load_image);
  206. int spl_spi_load_image(void)
  207. {
  208. return -EPERM;
  209. }
  210. #ifdef CONFIG_X86_RUN_64BIT
  211. void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
  212. {
  213. int ret;
  214. printf("Jumping to 64-bit U-Boot: Note many features are missing\n");
  215. ret = cpu_jump_to_64bit_uboot(spl_image->entry_point);
  216. debug("ret=%d\n", ret);
  217. hang();
  218. }
  219. #endif
  220. void spl_board_init(void)
  221. {
  222. #ifndef CONFIG_TPL
  223. preloader_console_init();
  224. #endif
  225. }