intel_gnvs.h 3.1 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * Copyright (C) 2019 Intel Corporation.
  4. *
  5. * Taken from coreboot intelblocks/nvs.h
  6. * Copyright 2019 Google LLC
  7. */
  8. #ifndef _INTEL_GNVS_H_
  9. #define _INTEL_GNVS_H_
  10. #include <linux/bitops.h>
  11. /*
  12. * The chromeos_acpi portion of ACPI GNVS is assumed to live from offset
  13. * 0x100 - 0x1000. When defining acpi_global_nvs, use check_member
  14. * to ensure that it is properly aligned:
  15. *
  16. * check_member(acpi_global_nvs, chromeos, GNVS_CHROMEOS_ACPI_OFFSET);
  17. */
  18. #define GNVS_CHROMEOS_ACPI_OFFSET 0x100
  19. enum {
  20. BOOT_REASON_OTHER = 0,
  21. BOOT_REASON_S3DIAG = 9
  22. };
  23. enum {
  24. CHSW_RECOVERY_X86 = BIT(1),
  25. CHSW_RECOVERY_EC = BIT(2),
  26. CHSW_DEVELOPER_SWITCH = BIT(5),
  27. CHSW_FIRMWARE_WP = BIT(9),
  28. };
  29. enum {
  30. RECOVERY_REASON_NONE = 0,
  31. RECOVERY_REASON_ME = 1
  32. };
  33. enum {
  34. ACTIVE_ECFW_RO = 0,
  35. ACTIVE_ECFW_RW = 1
  36. };
  37. enum {
  38. BINF_RECOVERY = 0,
  39. BINF_RW_A = 1,
  40. BINF_RW_B = 2
  41. };
  42. enum {
  43. FIRMWARE_TYPE_AUTO_DETECT = -1,
  44. FIRMWARE_TYPE_RECOVERY = 0,
  45. FIRMWARE_TYPE_NORMAL = 1,
  46. FIRMWARE_TYPE_DEVELOPER = 2,
  47. FIRMWARE_TYPE_NETBOOT = 3,
  48. FIRMWARE_TYPE_LEGACY = 4,
  49. };
  50. struct __packed chromeos_acpi_gnvs {
  51. /* ChromeOS-specific */
  52. u32 boot_reason; /* 00 boot reason */
  53. u32 active_main_fw; /* 04 (0=recovery, 1=A, 2=B) */
  54. u32 activeec_fw; /* 08 (0=RO, 1=RW) */
  55. u16 switches; /* 0c CHSW */
  56. u8 hwid[256]; /* 0e HWID */
  57. u8 fwid[64]; /* 10e FWID */
  58. u8 frid[64]; /* 14e FRID - 275 */
  59. u32 main_fw_type; /* 18e (2 = developer mode) */
  60. u32 recovery_reason; /* 192 recovery reason */
  61. u32 fmap_base; /* 196 fmap base address */
  62. u8 vdat[3072]; /* 19a VDAT space filled by verified boot */
  63. u32 fwid_ptr; /* d9a smbios bios version */
  64. u32 mehh[8]; /* d9e management engine hash */
  65. u32 ramoops_base; /* dbe ramoops base address */
  66. u32 ramoops_len; /* dc2 ramoops length */
  67. u32 vpd_ro_base; /* dc6 pointer to RO_VPD */
  68. u32 vpd_ro_size; /* dca size of RO_VPD */
  69. u32 vpd_rw_base; /* dce pointer to RW_VPD */
  70. u32 vpd_rw_size; /* dd2 size of RW_VPD */
  71. u8 pad[298]; /* dd6-eff */
  72. };
  73. struct __packed acpi_global_nvs {
  74. /* Miscellaneous */
  75. u8 pcnt; /* 0x00 - Processor Count */
  76. u8 ppcm; /* 0x01 - Max PPC State */
  77. u8 lids; /* 0x02 - LID State */
  78. u8 pwrs; /* 0x03 - AC Power State */
  79. u8 dpte; /* 0x04 - Enable DPTF */
  80. u32 cbmc; /* 0x05 - 0x08 - coreboot Memory Console */
  81. u64 pm1i; /* 0x09 - 0x10 - System Wake Source - PM1 Index */
  82. u64 gpei; /* 0x11 - 0x18 - GPE Wake Source */
  83. u64 nhla; /* 0x19 - 0x20 - NHLT Address */
  84. u32 nhll; /* 0x21 - 0x24 - NHLT Length */
  85. u32 prt0; /* 0x25 - 0x28 - PERST_0 Address */
  86. u8 scdp; /* 0x29 - SD_CD GPIO portid */
  87. u8 scdo; /* 0x2a - GPIO pad offset relative to the community */
  88. u8 uior; /* 0x2b - UART debug controller init on S3 resume */
  89. u8 ecps; /* 0x2c - SGX Enabled status */
  90. u64 emna; /* 0x2d - 0x34 EPC base address */
  91. u64 elng; /* 0x35 - 0x3C EPC Length */
  92. u8 unused1[0x100 - 0x3d]; /* Pad out to 256 bytes */
  93. #ifdef CONFIG_CHROMEOS
  94. /* ChromeOS-specific (0x100 - 0xfff) */
  95. struct chromeos_acpi_gnvs chromeos;
  96. #else
  97. u8 unused2[0x1000 - 0x100]; /* Pad out to 4096 bytes */
  98. #endif
  99. };
  100. check_member(acpi_global_nvs, chromeos, GNVS_CHROMEOS_ACPI_OFFSET);
  101. #endif /* _INTEL_GNVS_H_ */