spl.c 4.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright 2019 Google LLC
  4. */
  5. #define LOG_CATEGORY LOGC_BOOT
  6. #include <common.h>
  7. #include <binman_sym.h>
  8. #include <bootstage.h>
  9. #include <dm.h>
  10. #include <image.h>
  11. #include <log.h>
  12. #include <malloc.h>
  13. #include <spi.h>
  14. #include <spl.h>
  15. #include <spi_flash.h>
  16. #include <asm/fast_spi.h>
  17. #include <asm/spl.h>
  18. #include <asm/arch/cpu.h>
  19. #include <asm/arch/iomap.h>
  20. #include <dm/device-internal.h>
  21. #include <dm/uclass-internal.h>
  22. /* This reads the next phase from mapped SPI flash */
  23. static int rom_load_image(struct spl_image_info *spl_image,
  24. struct spl_boot_device *bootdev)
  25. {
  26. ulong spl_pos = spl_get_image_pos();
  27. ulong spl_size = spl_get_image_size();
  28. struct udevice *dev;
  29. ulong map_base;
  30. size_t map_size;
  31. uint offset;
  32. int ret;
  33. spl_image->size = CONFIG_SYS_MONITOR_LEN; /* We don't know SPL size */
  34. spl_image->entry_point = spl_get_image_text_base();
  35. spl_image->load_addr = spl_image->entry_point;
  36. spl_image->os = IH_OS_U_BOOT;
  37. spl_image->name = "U-Boot";
  38. log_debug("Reading from mapped SPI %lx, size %lx\n", spl_pos, spl_size);
  39. if (CONFIG_IS_ENABLED(SPI_FLASH_SUPPORT)) {
  40. ret = uclass_find_first_device(UCLASS_SPI_FLASH, &dev);
  41. if (ret)
  42. return log_msg_ret("spi_flash", ret);
  43. if (!dev)
  44. return log_msg_ret("spi_flash dev", -ENODEV);
  45. ret = dm_spi_get_mmap(dev, &map_base, &map_size, &offset);
  46. if (ret)
  47. return log_msg_ret("mmap", ret);
  48. } else {
  49. ret = fast_spi_get_bios_mmap(PCH_DEV_SPI, &map_base, &map_size,
  50. &offset);
  51. if (ret)
  52. return ret;
  53. }
  54. spl_pos += map_base & ~0xff000000;
  55. log_debug(", base %lx, pos %lx, load %lx\n", map_base, spl_pos,
  56. spl_image->load_addr);
  57. bootstage_start(BOOTSTAGE_ID_ACCUM_MMAP_SPI, "mmap_spi");
  58. memcpy((void *)spl_image->load_addr, (void *)spl_pos, spl_size);
  59. cpu_flush_l1d_to_l2();
  60. bootstage_accum(BOOTSTAGE_ID_ACCUM_MMAP_SPI);
  61. return 0;
  62. }
  63. SPL_LOAD_IMAGE_METHOD("Mapped SPI", 2, BOOT_DEVICE_SPI_MMAP, rom_load_image);
  64. #if CONFIG_IS_ENABLED(SPI_FLASH_SUPPORT)
  65. static int apl_flash_std_read(struct udevice *dev, u32 offset, size_t len,
  66. void *buf)
  67. {
  68. struct spi_flash *flash = dev_get_uclass_priv(dev);
  69. struct mtd_info *mtd = &flash->mtd;
  70. size_t retlen;
  71. return log_ret(mtd->_read(mtd, offset, len, &retlen, buf));
  72. }
  73. static int apl_flash_probe(struct udevice *dev)
  74. {
  75. return spi_flash_std_probe(dev);
  76. }
  77. static const struct dm_spi_flash_ops apl_flash_ops = {
  78. .read = apl_flash_std_read,
  79. };
  80. static const struct udevice_id apl_flash_ids[] = {
  81. { .compatible = "jedec,spi-nor" },
  82. { }
  83. };
  84. U_BOOT_DRIVER(winbond_w25q128fw) = {
  85. .name = "winbond_w25q128fw",
  86. .id = UCLASS_SPI_FLASH,
  87. .of_match = apl_flash_ids,
  88. .probe = apl_flash_probe,
  89. .priv_auto = sizeof(struct spi_nor),
  90. .ops = &apl_flash_ops,
  91. };
  92. /* This uses a SPI flash device to read the next phase */
  93. static int spl_fast_spi_load_image(struct spl_image_info *spl_image,
  94. struct spl_boot_device *bootdev)
  95. {
  96. ulong spl_pos = spl_get_image_pos();
  97. ulong spl_size = spl_get_image_size();
  98. struct udevice *dev;
  99. int ret;
  100. ret = uclass_first_device_err(UCLASS_SPI_FLASH, &dev);
  101. if (ret)
  102. return ret;
  103. spl_image->size = CONFIG_SYS_MONITOR_LEN; /* We don't know SPL size */
  104. spl_image->entry_point = spl_phase() == PHASE_TPL ?
  105. CONFIG_SPL_TEXT_BASE : CONFIG_SYS_TEXT_BASE;
  106. spl_image->load_addr = spl_image->entry_point;
  107. spl_image->os = IH_OS_U_BOOT;
  108. spl_image->name = "U-Boot";
  109. spl_pos &= ~0xff000000;
  110. log_debug("Reading from flash %lx, size %lx\n", spl_pos, spl_size);
  111. ret = spi_flash_read_dm(dev, spl_pos, spl_size,
  112. (void *)spl_image->load_addr);
  113. cpu_flush_l1d_to_l2();
  114. if (ret)
  115. return ret;
  116. return 0;
  117. }
  118. SPL_LOAD_IMAGE_METHOD("Fast SPI", 1, BOOT_DEVICE_FAST_SPI,
  119. spl_fast_spi_load_image);
  120. void board_boot_order(u32 *spl_boot_list)
  121. {
  122. bool use_spi_flash = IS_ENABLED(CONFIG_APL_BOOT_FROM_FAST_SPI_FLASH);
  123. if (use_spi_flash) {
  124. spl_boot_list[0] = BOOT_DEVICE_FAST_SPI;
  125. spl_boot_list[1] = BOOT_DEVICE_SPI_MMAP;
  126. } else {
  127. spl_boot_list[0] = BOOT_DEVICE_SPI_MMAP;
  128. spl_boot_list[1] = BOOT_DEVICE_FAST_SPI;
  129. }
  130. }
  131. #else
  132. void board_boot_order(u32 *spl_boot_list)
  133. {
  134. spl_boot_list[0] = BOOT_DEVICE_SPI_MMAP;
  135. }
  136. #endif