cpld.c 4.6 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * ULCB board CPLD access support
  4. *
  5. * Copyright (C) 2017 Renesas Electronics Corporation
  6. * Copyright (C) 2017 Cogent Embedded, Inc.
  7. */
  8. #include <common.h>
  9. #include <command.h>
  10. #include <asm/gpio.h>
  11. #include <asm/io.h>
  12. #include <dm.h>
  13. #include <errno.h>
  14. #include <linux/err.h>
  15. #include <sysreset.h>
  16. #define CPLD_ADDR_MODE 0x00 /* RW */
  17. #define CPLD_ADDR_MUX 0x02 /* RW */
  18. #define CPLD_ADDR_DIPSW6 0x08 /* R */
  19. #define CPLD_ADDR_RESET 0x80 /* RW */
  20. #define CPLD_ADDR_VERSION 0xFF /* R */
  21. struct renesas_ulcb_sysreset_priv {
  22. struct gpio_desc miso;
  23. struct gpio_desc mosi;
  24. struct gpio_desc sck;
  25. struct gpio_desc sstbz;
  26. };
  27. static u32 cpld_read(struct udevice *dev, u8 addr)
  28. {
  29. struct renesas_ulcb_sysreset_priv *priv = dev_get_priv(dev);
  30. u32 data = 0;
  31. int i;
  32. for (i = 0; i < 8; i++) {
  33. dm_gpio_set_value(&priv->mosi, !!(addr & 0x80)); /* MSB first */
  34. dm_gpio_set_value(&priv->sck, 1);
  35. addr <<= 1;
  36. dm_gpio_set_value(&priv->sck, 0);
  37. }
  38. dm_gpio_set_value(&priv->mosi, 0); /* READ */
  39. dm_gpio_set_value(&priv->sstbz, 0);
  40. dm_gpio_set_value(&priv->sck, 1);
  41. dm_gpio_set_value(&priv->sck, 0);
  42. dm_gpio_set_value(&priv->sstbz, 1);
  43. for (i = 0; i < 32; i++) {
  44. dm_gpio_set_value(&priv->sck, 1);
  45. data <<= 1;
  46. data |= dm_gpio_get_value(&priv->miso); /* MSB first */
  47. dm_gpio_set_value(&priv->sck, 0);
  48. }
  49. return data;
  50. }
  51. static void cpld_write(struct udevice *dev, u8 addr, u32 data)
  52. {
  53. struct renesas_ulcb_sysreset_priv *priv = dev_get_priv(dev);
  54. int i;
  55. for (i = 0; i < 32; i++) {
  56. dm_gpio_set_value(&priv->mosi, data & (1 << 31)); /* MSB first */
  57. dm_gpio_set_value(&priv->sck, 1);
  58. data <<= 1;
  59. dm_gpio_set_value(&priv->sck, 0);
  60. }
  61. for (i = 0; i < 8; i++) {
  62. dm_gpio_set_value(&priv->mosi, addr & 0x80); /* MSB first */
  63. dm_gpio_set_value(&priv->sck, 1);
  64. addr <<= 1;
  65. dm_gpio_set_value(&priv->sck, 0);
  66. }
  67. dm_gpio_set_value(&priv->mosi, 1); /* WRITE */
  68. dm_gpio_set_value(&priv->sstbz, 0);
  69. dm_gpio_set_value(&priv->sck, 1);
  70. dm_gpio_set_value(&priv->sck, 0);
  71. dm_gpio_set_value(&priv->sstbz, 1);
  72. }
  73. static int do_cpld(struct cmd_tbl *cmdtp, int flag, int argc,
  74. char *const argv[])
  75. {
  76. struct udevice *dev;
  77. u32 addr, val;
  78. int ret;
  79. ret = uclass_get_device_by_driver(UCLASS_SYSRESET,
  80. DM_DRIVER_GET(sysreset_renesas_ulcb),
  81. &dev);
  82. if (ret)
  83. return ret;
  84. if (argc == 2 && strcmp(argv[1], "info") == 0) {
  85. printf("CPLD version:\t\t\t0x%08x\n",
  86. cpld_read(dev, CPLD_ADDR_VERSION));
  87. printf("H3 Mode setting (MD0..28):\t0x%08x\n",
  88. cpld_read(dev, CPLD_ADDR_MODE));
  89. printf("Multiplexer settings:\t\t0x%08x\n",
  90. cpld_read(dev, CPLD_ADDR_MUX));
  91. printf("DIPSW (SW6):\t\t\t0x%08x\n",
  92. cpld_read(dev, CPLD_ADDR_DIPSW6));
  93. return 0;
  94. }
  95. if (argc < 3)
  96. return CMD_RET_USAGE;
  97. addr = hextoul(argv[2], NULL);
  98. if (!(addr == CPLD_ADDR_VERSION || addr == CPLD_ADDR_MODE ||
  99. addr == CPLD_ADDR_MUX || addr == CPLD_ADDR_DIPSW6 ||
  100. addr == CPLD_ADDR_RESET)) {
  101. printf("Invalid CPLD register address\n");
  102. return CMD_RET_USAGE;
  103. }
  104. if (argc == 3 && strcmp(argv[1], "read") == 0) {
  105. printf("0x%x\n", cpld_read(dev, addr));
  106. } else if (argc == 4 && strcmp(argv[1], "write") == 0) {
  107. val = hextoul(argv[3], NULL);
  108. cpld_write(dev, addr, val);
  109. }
  110. return 0;
  111. }
  112. U_BOOT_CMD(
  113. cpld, 4, 1, do_cpld,
  114. "CPLD access",
  115. "info\n"
  116. "cpld read addr\n"
  117. "cpld write addr val\n"
  118. );
  119. static int renesas_ulcb_sysreset_request(struct udevice *dev, enum sysreset_t type)
  120. {
  121. cpld_write(dev, CPLD_ADDR_RESET, 1);
  122. return -EINPROGRESS;
  123. }
  124. static int renesas_ulcb_sysreset_probe(struct udevice *dev)
  125. {
  126. struct renesas_ulcb_sysreset_priv *priv = dev_get_priv(dev);
  127. if (gpio_request_by_name(dev, "gpio-miso", 0, &priv->miso,
  128. GPIOD_IS_IN))
  129. return -EINVAL;
  130. if (gpio_request_by_name(dev, "gpio-sck", 0, &priv->sck,
  131. GPIOD_IS_OUT))
  132. return -EINVAL;
  133. if (gpio_request_by_name(dev, "gpio-sstbz", 0, &priv->sstbz,
  134. GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE))
  135. return -EINVAL;
  136. if (gpio_request_by_name(dev, "gpio-mosi", 0, &priv->mosi,
  137. GPIOD_IS_OUT))
  138. return -EINVAL;
  139. /* PULL-UP on MISO line */
  140. setbits_le32(PFC_PUEN5, PUEN_SSI_SDATA4);
  141. /* Dummy read */
  142. cpld_read(dev, CPLD_ADDR_VERSION);
  143. return 0;
  144. }
  145. static struct sysreset_ops renesas_ulcb_sysreset = {
  146. .request = renesas_ulcb_sysreset_request,
  147. };
  148. static const struct udevice_id renesas_ulcb_sysreset_ids[] = {
  149. { .compatible = "renesas,ulcb-cpld" },
  150. { }
  151. };
  152. U_BOOT_DRIVER(sysreset_renesas_ulcb) = {
  153. .name = "renesas_ulcb_sysreset",
  154. .id = UCLASS_SYSRESET,
  155. .ops = &renesas_ulcb_sysreset,
  156. .probe = renesas_ulcb_sysreset_probe,
  157. .of_match = renesas_ulcb_sysreset_ids,
  158. .priv_auto = sizeof(struct renesas_ulcb_sysreset_priv),
  159. };