m53menlo.c 14 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Menlosystems M53Menlo board
  4. *
  5. * Copyright (C) 2012-2017 Marek Vasut <marex@denx.de>
  6. * Copyright (C) 2014-2017 Olaf Mandel <o.mandel@menlosystems.com>
  7. */
  8. #include <common.h>
  9. #include <dm.h>
  10. #include <init.h>
  11. #include <malloc.h>
  12. #include <asm/global_data.h>
  13. #include <asm/io.h>
  14. #include <asm/arch/imx-regs.h>
  15. #include <asm/arch/sys_proto.h>
  16. #include <asm/arch/crm_regs.h>
  17. #include <asm/arch/clock.h>
  18. #include <asm/arch/iomux-mx53.h>
  19. #include <asm/mach-imx/mx5_video.h>
  20. #include <asm/mach-imx/video.h>
  21. #include <asm/gpio.h>
  22. #include <asm/spl.h>
  23. #include <env.h>
  24. #include <fdt_support.h>
  25. #include <fsl_esdhc_imx.h>
  26. #include <gzip.h>
  27. #include <i2c.h>
  28. #include <ipu_pixfmt.h>
  29. #include <linux/bitops.h>
  30. #include <linux/errno.h>
  31. #include <linux/fb.h>
  32. #include <mmc.h>
  33. #include <netdev.h>
  34. #include <spl.h>
  35. #include <splash.h>
  36. #include <usb/ehci-ci.h>
  37. #include <video_console.h>
  38. DECLARE_GLOBAL_DATA_PTR;
  39. static u32 mx53_dram_size[2];
  40. ulong board_get_usable_ram_top(ulong total_size)
  41. {
  42. /*
  43. * WARNING: We must override get_effective_memsize() function here
  44. * to report only the size of the first DRAM bank. This is to make
  45. * U-Boot relocator place U-Boot into valid memory, that is, at the
  46. * end of the first DRAM bank. If we did not override this function
  47. * like so, U-Boot would be placed at the address of the first DRAM
  48. * bank + total DRAM size - sizeof(uboot), which in the setup where
  49. * each DRAM bank contains 512MiB of DRAM would result in placing
  50. * U-Boot into invalid memory area close to the end of the first
  51. * DRAM bank.
  52. */
  53. return PHYS_SDRAM_2 + mx53_dram_size[1];
  54. }
  55. int dram_init(void)
  56. {
  57. mx53_dram_size[0] = get_ram_size((void *)PHYS_SDRAM_1, 1 << 30);
  58. mx53_dram_size[1] = get_ram_size((void *)PHYS_SDRAM_2, 1 << 30);
  59. gd->ram_size = mx53_dram_size[0] + mx53_dram_size[1];
  60. return 0;
  61. }
  62. int dram_init_banksize(void)
  63. {
  64. gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
  65. gd->bd->bi_dram[0].size = mx53_dram_size[0];
  66. gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
  67. gd->bd->bi_dram[1].size = mx53_dram_size[1];
  68. return 0;
  69. }
  70. static void setup_iomux_uart(void)
  71. {
  72. static const iomux_v3_cfg_t uart_pads[] = {
  73. MX53_PAD_PATA_DMACK__UART1_RXD_MUX,
  74. MX53_PAD_PATA_DIOW__UART1_TXD_MUX,
  75. };
  76. imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
  77. }
  78. static void setup_iomux_fec(void)
  79. {
  80. static const iomux_v3_cfg_t fec_pads[] = {
  81. /* MDIO pads */
  82. NEW_PAD_CTRL(MX53_PAD_FEC_MDIO__FEC_MDIO, PAD_CTL_HYS |
  83. PAD_CTL_DSE_HIGH | PAD_CTL_PUS_22K_UP | PAD_CTL_ODE),
  84. NEW_PAD_CTRL(MX53_PAD_FEC_MDC__FEC_MDC, PAD_CTL_DSE_HIGH),
  85. /* FEC 0 pads */
  86. NEW_PAD_CTRL(MX53_PAD_FEC_CRS_DV__FEC_RX_DV,
  87. PAD_CTL_HYS | PAD_CTL_PKE),
  88. NEW_PAD_CTRL(MX53_PAD_FEC_REF_CLK__FEC_TX_CLK,
  89. PAD_CTL_HYS | PAD_CTL_PKE),
  90. NEW_PAD_CTRL(MX53_PAD_FEC_RX_ER__FEC_RX_ER,
  91. PAD_CTL_HYS | PAD_CTL_PKE),
  92. NEW_PAD_CTRL(MX53_PAD_FEC_TX_EN__FEC_TX_EN, PAD_CTL_DSE_HIGH),
  93. NEW_PAD_CTRL(MX53_PAD_FEC_RXD0__FEC_RDATA_0,
  94. PAD_CTL_HYS | PAD_CTL_PKE),
  95. NEW_PAD_CTRL(MX53_PAD_FEC_RXD1__FEC_RDATA_1,
  96. PAD_CTL_HYS | PAD_CTL_PKE),
  97. NEW_PAD_CTRL(MX53_PAD_FEC_TXD0__FEC_TDATA_0, PAD_CTL_DSE_HIGH),
  98. NEW_PAD_CTRL(MX53_PAD_FEC_TXD1__FEC_TDATA_1, PAD_CTL_DSE_HIGH),
  99. /* FEC 1 pads */
  100. NEW_PAD_CTRL(MX53_PAD_KEY_COL0__FEC_RDATA_3,
  101. PAD_CTL_HYS | PAD_CTL_PKE),
  102. NEW_PAD_CTRL(MX53_PAD_KEY_ROW0__FEC_TX_ER,
  103. PAD_CTL_HYS | PAD_CTL_PKE),
  104. NEW_PAD_CTRL(MX53_PAD_KEY_COL1__FEC_RX_CLK,
  105. PAD_CTL_HYS | PAD_CTL_PKE),
  106. NEW_PAD_CTRL(MX53_PAD_KEY_ROW1__FEC_COL,
  107. PAD_CTL_HYS | PAD_CTL_PKE),
  108. NEW_PAD_CTRL(MX53_PAD_KEY_COL2__FEC_RDATA_2,
  109. PAD_CTL_HYS | PAD_CTL_PKE),
  110. NEW_PAD_CTRL(MX53_PAD_KEY_ROW2__FEC_TDATA_2, PAD_CTL_DSE_HIGH),
  111. NEW_PAD_CTRL(MX53_PAD_KEY_COL3__FEC_CRS,
  112. PAD_CTL_HYS | PAD_CTL_PKE),
  113. NEW_PAD_CTRL(MX53_PAD_GPIO_19__FEC_TDATA_3, PAD_CTL_DSE_HIGH),
  114. };
  115. imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
  116. }
  117. #ifdef CONFIG_FSL_ESDHC_IMX
  118. struct fsl_esdhc_cfg esdhc_cfg = {
  119. MMC_SDHC1_BASE_ADDR,
  120. };
  121. int board_mmc_getcd(struct mmc *mmc)
  122. {
  123. imx_iomux_v3_setup_pad(MX53_PAD_GPIO_1__GPIO1_1);
  124. gpio_direction_input(IMX_GPIO_NR(1, 1));
  125. return !gpio_get_value(IMX_GPIO_NR(1, 1));
  126. }
  127. #define SD_CMD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
  128. PAD_CTL_PUS_100K_UP)
  129. #define SD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | \
  130. PAD_CTL_DSE_HIGH)
  131. int board_mmc_init(struct bd_info *bis)
  132. {
  133. static const iomux_v3_cfg_t sd1_pads[] = {
  134. NEW_PAD_CTRL(MX53_PAD_SD1_CMD__ESDHC1_CMD, SD_CMD_PAD_CTRL),
  135. NEW_PAD_CTRL(MX53_PAD_SD1_CLK__ESDHC1_CLK, SD_PAD_CTRL),
  136. NEW_PAD_CTRL(MX53_PAD_SD1_DATA0__ESDHC1_DAT0, SD_PAD_CTRL),
  137. NEW_PAD_CTRL(MX53_PAD_SD1_DATA1__ESDHC1_DAT1, SD_PAD_CTRL),
  138. NEW_PAD_CTRL(MX53_PAD_SD1_DATA2__ESDHC1_DAT2, SD_PAD_CTRL),
  139. NEW_PAD_CTRL(MX53_PAD_SD1_DATA3__ESDHC1_DAT3, SD_PAD_CTRL),
  140. };
  141. esdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
  142. imx_iomux_v3_setup_multiple_pads(sd1_pads, ARRAY_SIZE(sd1_pads));
  143. return fsl_esdhc_initialize(bis, &esdhc_cfg);
  144. }
  145. #endif
  146. static void enable_lvds_clock(struct display_info_t const *dev, const u8 hclk)
  147. {
  148. static struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)MXC_CCM_BASE;
  149. int ret;
  150. /* For ETM0430G0DH6 model, this must be enabled before the clock. */
  151. gpio_direction_output(IMX_GPIO_NR(6, 0), 1);
  152. /*
  153. * Set LVDS clock to 33.28 MHz for the display. The PLL4 is set to
  154. * 233 MHz, divided by 7 by setting CCM_CSCMR2 LDB_DI0_IPU_DIV=1 .
  155. */
  156. ret = mxc_set_clock(MXC_HCLK, hclk, MXC_LDB_CLK);
  157. if (ret)
  158. puts("IPU: Failed to configure LDB clock\n");
  159. /* Configure CCM_CSCMR2 */
  160. clrsetbits_le32(&mxc_ccm->cscmr2,
  161. (0x7 << 26) | BIT(10) | BIT(8),
  162. (0x5 << 26) | BIT(10) | BIT(8));
  163. /* Configure LDB_CTRL */
  164. writel(0x201, 0x53fa8008);
  165. }
  166. static void enable_lvds_etm0430g0dh6(struct display_info_t const *dev)
  167. {
  168. gpio_request(IMX_GPIO_NR(6, 0), "LCD");
  169. /* For ETM0430G0DH6 model, this must be enabled before the clock. */
  170. gpio_direction_output(IMX_GPIO_NR(6, 0), 1);
  171. /*
  172. * Set LVDS clock to 9 MHz for the display. The PLL4 is set to
  173. * 63 MHz, divided by 7 by setting CCM_CSCMR2 LDB_DI0_IPU_DIV=1 .
  174. */
  175. enable_lvds_clock(dev, 63);
  176. }
  177. static void enable_lvds_etm0700g0dh6(struct display_info_t const *dev)
  178. {
  179. gpio_request(IMX_GPIO_NR(6, 0), "LCD");
  180. /*
  181. * Set LVDS clock to 33.28 MHz for the display. The PLL4 is set to
  182. * 233 MHz, divided by 7 by setting CCM_CSCMR2 LDB_DI0_IPU_DIV=1 .
  183. */
  184. enable_lvds_clock(dev, 233);
  185. /* For ETM0700G0DH6 model, this may be enabled after the clock. */
  186. gpio_direction_output(IMX_GPIO_NR(6, 0), 1);
  187. }
  188. static const char *lvds_compat_string;
  189. static int detect_lvds(struct display_info_t const *dev)
  190. {
  191. u8 touchid[23];
  192. u8 *touchptr = &touchid[0];
  193. int ret;
  194. ret = i2c_set_bus_num(0);
  195. if (ret)
  196. return 0;
  197. /* Touchscreen is at address 0x38, ID register is 0xbb. */
  198. ret = i2c_read(0x38, 0xbb, 1, touchid, sizeof(touchid));
  199. if (ret)
  200. return 0;
  201. /* EP0430 prefixes the response with 0xbb, skip it. */
  202. if (*touchptr == 0xbb)
  203. touchptr++;
  204. /* Skip the 'EP' prefix. */
  205. touchptr += 2;
  206. ret = !memcmp(touchptr, &dev->mode.name[7], 4);
  207. if (ret)
  208. lvds_compat_string = dev->mode.name;
  209. return ret;
  210. }
  211. void board_preboot_os(void)
  212. {
  213. /* Power off the LCD to prevent awful color flicker */
  214. gpio_direction_output(IMX_GPIO_NR(6, 0), 0);
  215. }
  216. int ft_board_setup(void *blob, struct bd_info *bd)
  217. {
  218. if (lvds_compat_string)
  219. do_fixup_by_path_string(blob, "/panel", "compatible",
  220. lvds_compat_string);
  221. return 0;
  222. }
  223. struct display_info_t const displays[] = {
  224. {
  225. .bus = 0,
  226. .addr = 0,
  227. .detect = detect_lvds,
  228. .enable = enable_lvds_etm0430g0dh6,
  229. .pixfmt = IPU_PIX_FMT_RGB666,
  230. .mode = {
  231. .name = "edt,etm0430g0dh6",
  232. .refresh = 60,
  233. .xres = 480,
  234. .yres = 272,
  235. .pixclock = 111111, /* picosecond (9 MHz) */
  236. .left_margin = 2,
  237. .right_margin = 2,
  238. .upper_margin = 2,
  239. .lower_margin = 2,
  240. .hsync_len = 41,
  241. .vsync_len = 10,
  242. .sync = 0x40000000,
  243. .vmode = FB_VMODE_NONINTERLACED
  244. }
  245. }, {
  246. .bus = 0,
  247. .addr = 0,
  248. .detect = detect_lvds,
  249. .enable = enable_lvds_etm0700g0dh6,
  250. .pixfmt = IPU_PIX_FMT_RGB666,
  251. .mode = {
  252. .name = "edt,etm0700g0dh6",
  253. .refresh = 60,
  254. .xres = 800,
  255. .yres = 480,
  256. .pixclock = 30048, /* picosecond (33.28 MHz) */
  257. .left_margin = 40,
  258. .right_margin = 88,
  259. .upper_margin = 10,
  260. .lower_margin = 33,
  261. .hsync_len = 128,
  262. .vsync_len = 2,
  263. .sync = FB_SYNC_EXT,
  264. .vmode = FB_VMODE_NONINTERLACED
  265. }
  266. }
  267. };
  268. size_t display_count = ARRAY_SIZE(displays);
  269. #ifdef CONFIG_SPLASH_SCREEN
  270. static struct splash_location default_splash_locations[] = {
  271. {
  272. .name = "mmc_fs",
  273. .storage = SPLASH_STORAGE_MMC,
  274. .flags = SPLASH_STORAGE_FS,
  275. .devpart = "0:1",
  276. },
  277. };
  278. int splash_screen_prepare(void)
  279. {
  280. return splash_source_load(default_splash_locations,
  281. ARRAY_SIZE(default_splash_locations));
  282. }
  283. #endif
  284. int board_late_init(void)
  285. {
  286. #if defined(CONFIG_VIDEO_IPUV3)
  287. struct udevice *dev;
  288. int xpos, ypos, ret;
  289. char *s;
  290. void *dst;
  291. ulong addr, len;
  292. splash_get_pos(&xpos, &ypos);
  293. s = env_get("splashimage");
  294. if (!s)
  295. return 0;
  296. addr = hextoul(s, NULL);
  297. dst = malloc(CONFIG_SYS_VIDEO_LOGO_MAX_SIZE);
  298. if (!dst)
  299. return -ENOMEM;
  300. ret = splash_screen_prepare();
  301. if (ret < 0)
  302. goto splasherr;
  303. len = CONFIG_SYS_VIDEO_LOGO_MAX_SIZE;
  304. ret = gunzip(dst + 2, CONFIG_SYS_VIDEO_LOGO_MAX_SIZE - 2,
  305. (uchar *)addr, &len);
  306. if (ret) {
  307. printf("Error: no valid bmp or bmp.gz image at %lx\n", addr);
  308. goto splasherr;
  309. }
  310. ret = uclass_get_device(UCLASS_VIDEO, 0, &dev);
  311. if (ret)
  312. goto splasherr;
  313. ret = video_bmp_display(dev, (ulong)dst + 2, xpos, ypos, true);
  314. if (ret)
  315. goto splasherr;
  316. return 0;
  317. splasherr:
  318. free(dst);
  319. #endif
  320. return 0;
  321. }
  322. #define I2C_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | \
  323. PAD_CTL_PUS_100K_UP | PAD_CTL_ODE)
  324. static void setup_iomux_i2c(void)
  325. {
  326. static const iomux_v3_cfg_t i2c_pads[] = {
  327. /* I2C1 */
  328. NEW_PAD_CTRL(MX53_PAD_EIM_D28__I2C1_SDA, I2C_PAD_CTRL),
  329. NEW_PAD_CTRL(MX53_PAD_EIM_D21__I2C1_SCL, I2C_PAD_CTRL),
  330. /* I2C2 */
  331. NEW_PAD_CTRL(MX53_PAD_EIM_D16__I2C2_SDA, I2C_PAD_CTRL),
  332. NEW_PAD_CTRL(MX53_PAD_EIM_EB2__I2C2_SCL, I2C_PAD_CTRL),
  333. };
  334. imx_iomux_v3_setup_multiple_pads(i2c_pads, ARRAY_SIZE(i2c_pads));
  335. }
  336. static void setup_iomux_video(void)
  337. {
  338. static const iomux_v3_cfg_t lcd_pads[] = {
  339. MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3,
  340. MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK,
  341. MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2,
  342. MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1,
  343. MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0,
  344. };
  345. imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads));
  346. }
  347. static void setup_iomux_nand(void)
  348. {
  349. static const iomux_v3_cfg_t nand_pads[] = {
  350. NEW_PAD_CTRL(MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B,
  351. PAD_CTL_DSE_HIGH),
  352. NEW_PAD_CTRL(MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B,
  353. PAD_CTL_DSE_HIGH),
  354. NEW_PAD_CTRL(MX53_PAD_NANDF_CLE__EMI_NANDF_CLE,
  355. PAD_CTL_DSE_HIGH),
  356. NEW_PAD_CTRL(MX53_PAD_NANDF_ALE__EMI_NANDF_ALE,
  357. PAD_CTL_DSE_HIGH),
  358. NEW_PAD_CTRL(MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B,
  359. PAD_CTL_PUS_100K_UP),
  360. NEW_PAD_CTRL(MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0,
  361. PAD_CTL_PUS_100K_UP),
  362. NEW_PAD_CTRL(MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0,
  363. PAD_CTL_DSE_HIGH),
  364. NEW_PAD_CTRL(MX53_PAD_PATA_DATA0__EMI_NANDF_D_0,
  365. PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
  366. NEW_PAD_CTRL(MX53_PAD_PATA_DATA1__EMI_NANDF_D_1,
  367. PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
  368. NEW_PAD_CTRL(MX53_PAD_PATA_DATA2__EMI_NANDF_D_2,
  369. PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
  370. NEW_PAD_CTRL(MX53_PAD_PATA_DATA3__EMI_NANDF_D_3,
  371. PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
  372. NEW_PAD_CTRL(MX53_PAD_PATA_DATA4__EMI_NANDF_D_4,
  373. PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
  374. NEW_PAD_CTRL(MX53_PAD_PATA_DATA5__EMI_NANDF_D_5,
  375. PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
  376. NEW_PAD_CTRL(MX53_PAD_PATA_DATA6__EMI_NANDF_D_6,
  377. PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
  378. NEW_PAD_CTRL(MX53_PAD_PATA_DATA7__EMI_NANDF_D_7,
  379. PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
  380. };
  381. imx_iomux_v3_setup_multiple_pads(nand_pads, ARRAY_SIZE(nand_pads));
  382. }
  383. static void m53_set_clock(void)
  384. {
  385. int ret;
  386. const u32 ref_clk = MXC_HCLK;
  387. const u32 dramclk = 400;
  388. u32 cpuclk;
  389. gpio_request(IMX_GPIO_NR(4, 0), "CPUCLK");
  390. imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX53_PAD_GPIO_10__GPIO4_0,
  391. PAD_CTL_DSE_HIGH | PAD_CTL_PKE));
  392. gpio_direction_input(IMX_GPIO_NR(4, 0));
  393. /* GPIO10 selects modules' CPU speed, 1 = 1200MHz ; 0 = 800MHz */
  394. cpuclk = gpio_get_value(IMX_GPIO_NR(4, 0)) ? 1200 : 800;
  395. ret = mxc_set_clock(ref_clk, cpuclk, MXC_ARM_CLK);
  396. if (ret)
  397. printf("CPU: Switch CPU clock to %dMHz failed\n", cpuclk);
  398. ret = mxc_set_clock(ref_clk, dramclk, MXC_PERIPH_CLK);
  399. if (ret) {
  400. printf("CPU: Switch peripheral clock to %dMHz failed\n",
  401. dramclk);
  402. }
  403. ret = mxc_set_clock(ref_clk, dramclk, MXC_DDR_CLK);
  404. if (ret)
  405. printf("CPU: Switch DDR clock to %dMHz failed\n", dramclk);
  406. }
  407. static void m53_set_nand(void)
  408. {
  409. u32 i;
  410. /* NAND flash is muxed on ATA pins */
  411. setbits_le32(M4IF_BASE_ADDR + 0xc, M4IF_GENP_WEIM_MM_MASK);
  412. /* Wait for Grant/Ack sequence (see EIM_CSnGCR2:MUX16_BYP_GRANT) */
  413. for (i = 0x4; i < 0x94; i += 0x18) {
  414. clrbits_le32(WEIM_BASE_ADDR + i,
  415. WEIM_GCR2_MUX16_BYP_GRANT_MASK);
  416. }
  417. mxc_set_clock(0, 33, MXC_NFC_CLK);
  418. enable_nfc_clk(1);
  419. }
  420. int board_early_init_f(void)
  421. {
  422. setup_iomux_uart();
  423. setup_iomux_fec();
  424. setup_iomux_i2c();
  425. setup_iomux_nand();
  426. setup_iomux_video();
  427. m53_set_clock();
  428. mxc_set_sata_internal_clock();
  429. /* NAND clock @ 33MHz */
  430. m53_set_nand();
  431. return 0;
  432. }
  433. int board_init(void)
  434. {
  435. gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
  436. return 0;
  437. }
  438. int checkboard(void)
  439. {
  440. puts("Board: Menlosystems M53Menlo\n");
  441. return 0;
  442. }
  443. /*
  444. * NAND SPL
  445. */
  446. #ifdef CONFIG_SPL_BUILD
  447. void spl_board_init(void)
  448. {
  449. setup_iomux_nand();
  450. m53_set_clock();
  451. m53_set_nand();
  452. }
  453. u32 spl_boot_device(void)
  454. {
  455. return BOOT_DEVICE_NAND;
  456. }
  457. #endif