osd.c 11 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2010
  4. * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
  5. */
  6. #ifdef CONFIG_GDSYS_LEGACY_DRIVERS
  7. #include <common.h>
  8. #include <command.h>
  9. #include <i2c.h>
  10. #include <malloc.h>
  11. #include <linux/stringify.h>
  12. #include "ch7301.h"
  13. #include "dp501.h"
  14. #include <gdsys_fpga.h>
  15. #define ICS8N3QV01_I2C_ADDR 0x6E
  16. #define ICS8N3QV01_FREF 114285000
  17. #define ICS8N3QV01_FREF_LL 114285000LL
  18. #define ICS8N3QV01_F_DEFAULT_0 156250000LL
  19. #define ICS8N3QV01_F_DEFAULT_1 125000000LL
  20. #define ICS8N3QV01_F_DEFAULT_2 100000000LL
  21. #define ICS8N3QV01_F_DEFAULT_3 25175000LL
  22. #define SIL1178_MASTER_I2C_ADDRESS 0x38
  23. #define SIL1178_SLAVE_I2C_ADDRESS 0x39
  24. #define PIXCLK_640_480_60 25180000
  25. #define MAX_X_CHARS 53
  26. #define MAX_Y_CHARS 26
  27. #ifdef CONFIG_SYS_OSD_DH
  28. #define MAX_OSD_SCREEN 8
  29. #define OSD_DH_BASE 4
  30. #else
  31. #define MAX_OSD_SCREEN 4
  32. #endif
  33. #ifdef CONFIG_SYS_OSD_DH
  34. #define OSD_SET_REG(screen, fld, val) \
  35. do { \
  36. if (screen >= OSD_DH_BASE) \
  37. FPGA_SET_REG(screen - OSD_DH_BASE, osd1.fld, val); \
  38. else \
  39. FPGA_SET_REG(screen, osd0.fld, val); \
  40. } while (0)
  41. #else
  42. #define OSD_SET_REG(screen, fld, val) \
  43. FPGA_SET_REG(screen, osd0.fld, val)
  44. #endif
  45. #ifdef CONFIG_SYS_OSD_DH
  46. #define OSD_GET_REG(screen, fld, val) \
  47. do { \
  48. if (screen >= OSD_DH_BASE) \
  49. FPGA_GET_REG(screen - OSD_DH_BASE, osd1.fld, val); \
  50. else \
  51. FPGA_GET_REG(screen, osd0.fld, val); \
  52. } while (0)
  53. #else
  54. #define OSD_GET_REG(screen, fld, val) \
  55. FPGA_GET_REG(screen, osd0.fld, val)
  56. #endif
  57. unsigned int base_width;
  58. unsigned int base_height;
  59. size_t bufsize;
  60. u16 *buf;
  61. unsigned int osd_screen_mask = 0;
  62. #ifdef CONFIG_SYS_ICS8N3QV01_I2C
  63. int ics8n3qv01_i2c[] = CONFIG_SYS_ICS8N3QV01_I2C;
  64. #endif
  65. #ifdef CONFIG_SYS_SIL1178_I2C
  66. int sil1178_i2c[] = CONFIG_SYS_SIL1178_I2C;
  67. #endif
  68. #ifdef CONFIG_SYS_MPC92469AC
  69. static void mpc92469ac_calc_parameters(unsigned int fout,
  70. unsigned int *post_div, unsigned int *feedback_div)
  71. {
  72. unsigned int n = *post_div;
  73. unsigned int m = *feedback_div;
  74. unsigned int a;
  75. unsigned int b = 14745600 / 16;
  76. if (fout < 50169600)
  77. n = 8;
  78. else if (fout < 100339199)
  79. n = 4;
  80. else if (fout < 200678399)
  81. n = 2;
  82. else
  83. n = 1;
  84. a = fout * n + (b / 2); /* add b/2 for proper rounding */
  85. m = a / b;
  86. *post_div = n;
  87. *feedback_div = m;
  88. }
  89. static void mpc92469ac_set(unsigned screen, unsigned int fout)
  90. {
  91. unsigned int n;
  92. unsigned int m;
  93. unsigned int bitval = 0;
  94. mpc92469ac_calc_parameters(fout, &n, &m);
  95. switch (n) {
  96. case 1:
  97. bitval = 0x00;
  98. break;
  99. case 2:
  100. bitval = 0x01;
  101. break;
  102. case 4:
  103. bitval = 0x02;
  104. break;
  105. case 8:
  106. bitval = 0x03;
  107. break;
  108. }
  109. FPGA_SET_REG(screen, mpc3w_control, (bitval << 9) | m);
  110. }
  111. #endif
  112. #ifdef CONFIG_SYS_ICS8N3QV01_I2C
  113. static unsigned int ics8n3qv01_get_fout_calc(unsigned index)
  114. {
  115. unsigned long long n;
  116. unsigned long long mint;
  117. unsigned long long mfrac;
  118. u8 reg_a, reg_b, reg_c, reg_d, reg_f;
  119. unsigned long long fout_calc;
  120. if (index > 3)
  121. return 0;
  122. reg_a = i2c_reg_read(ICS8N3QV01_I2C_ADDR, 0 + index);
  123. reg_b = i2c_reg_read(ICS8N3QV01_I2C_ADDR, 4 + index);
  124. reg_c = i2c_reg_read(ICS8N3QV01_I2C_ADDR, 8 + index);
  125. reg_d = i2c_reg_read(ICS8N3QV01_I2C_ADDR, 12 + index);
  126. reg_f = i2c_reg_read(ICS8N3QV01_I2C_ADDR, 20 + index);
  127. mint = ((reg_a >> 1) & 0x1f) | (reg_f & 0x20);
  128. mfrac = ((reg_a & 0x01) << 17) | (reg_b << 9) | (reg_c << 1)
  129. | (reg_d >> 7);
  130. n = reg_d & 0x7f;
  131. fout_calc = (mint * ICS8N3QV01_FREF_LL
  132. + mfrac * ICS8N3QV01_FREF_LL / 262144LL
  133. + ICS8N3QV01_FREF_LL / 524288LL
  134. + n / 2)
  135. / n
  136. * 1000000
  137. / (1000000 - 100);
  138. return fout_calc;
  139. }
  140. static void ics8n3qv01_calc_parameters(unsigned int fout,
  141. unsigned int *_mint, unsigned int *_mfrac,
  142. unsigned int *_n)
  143. {
  144. unsigned int n;
  145. unsigned int foutiic;
  146. unsigned int fvcoiic;
  147. unsigned int mint;
  148. unsigned long long mfrac;
  149. n = (2215000000U + fout / 2) / fout;
  150. if ((n & 1) && (n > 5))
  151. n -= 1;
  152. foutiic = fout - (fout / 10000);
  153. fvcoiic = foutiic * n;
  154. mint = fvcoiic / 114285000;
  155. if ((mint < 17) || (mint > 63))
  156. printf("ics8n3qv01_calc_parameters: cannot determine mint\n");
  157. mfrac = ((unsigned long long)fvcoiic % 114285000LL) * 262144LL
  158. / 114285000LL;
  159. *_mint = mint;
  160. *_mfrac = mfrac;
  161. *_n = n;
  162. }
  163. static void ics8n3qv01_set(unsigned int fout)
  164. {
  165. unsigned int n;
  166. unsigned int mint;
  167. unsigned int mfrac;
  168. unsigned int fout_calc;
  169. unsigned long long fout_prog;
  170. long long off_ppm;
  171. u8 reg0, reg4, reg8, reg12, reg18, reg20;
  172. fout_calc = ics8n3qv01_get_fout_calc(1);
  173. off_ppm = (fout_calc - ICS8N3QV01_F_DEFAULT_1) * 1000000
  174. / ICS8N3QV01_F_DEFAULT_1;
  175. printf(" PLL is off by %lld ppm\n", off_ppm);
  176. fout_prog = (unsigned long long)fout * (unsigned long long)fout_calc
  177. / ICS8N3QV01_F_DEFAULT_1;
  178. ics8n3qv01_calc_parameters(fout_prog, &mint, &mfrac, &n);
  179. reg0 = i2c_reg_read(ICS8N3QV01_I2C_ADDR, 0) & 0xc0;
  180. reg0 |= (mint & 0x1f) << 1;
  181. reg0 |= (mfrac >> 17) & 0x01;
  182. i2c_reg_write(ICS8N3QV01_I2C_ADDR, 0, reg0);
  183. reg4 = mfrac >> 9;
  184. i2c_reg_write(ICS8N3QV01_I2C_ADDR, 4, reg4);
  185. reg8 = mfrac >> 1;
  186. i2c_reg_write(ICS8N3QV01_I2C_ADDR, 8, reg8);
  187. reg12 = mfrac << 7;
  188. reg12 |= n & 0x7f;
  189. i2c_reg_write(ICS8N3QV01_I2C_ADDR, 12, reg12);
  190. reg18 = i2c_reg_read(ICS8N3QV01_I2C_ADDR, 18) & 0x03;
  191. reg18 |= 0x20;
  192. i2c_reg_write(ICS8N3QV01_I2C_ADDR, 18, reg18);
  193. reg20 = i2c_reg_read(ICS8N3QV01_I2C_ADDR, 20) & 0x1f;
  194. reg20 |= mint & (1 << 5);
  195. i2c_reg_write(ICS8N3QV01_I2C_ADDR, 20, reg20);
  196. }
  197. #endif
  198. static int osd_write_videomem(unsigned screen, unsigned offset,
  199. u16 *data, size_t charcount)
  200. {
  201. unsigned int k;
  202. for (k = 0; k < charcount; ++k) {
  203. if (offset + k >= bufsize)
  204. return -1;
  205. #ifdef CONFIG_SYS_OSD_DH
  206. if (screen >= OSD_DH_BASE)
  207. FPGA_SET_REG(screen - OSD_DH_BASE,
  208. videomem1[offset + k], data[k]);
  209. else
  210. FPGA_SET_REG(screen, videomem0[offset + k], data[k]);
  211. #else
  212. FPGA_SET_REG(screen, videomem0[offset + k], data[k]);
  213. #endif
  214. }
  215. return charcount;
  216. }
  217. static int osd_print(struct cmd_tbl *cmdtp, int flag, int argc,
  218. char *const argv[])
  219. {
  220. unsigned screen;
  221. if (argc < 5) {
  222. cmd_usage(cmdtp);
  223. return 1;
  224. }
  225. for (screen = 0; screen < MAX_OSD_SCREEN; ++screen) {
  226. unsigned x;
  227. unsigned y;
  228. unsigned charcount;
  229. unsigned len;
  230. u8 color;
  231. unsigned int k;
  232. char *text;
  233. int res;
  234. if (!(osd_screen_mask & (1 << screen)))
  235. continue;
  236. x = hextoul(argv[1], NULL);
  237. y = hextoul(argv[2], NULL);
  238. color = hextoul(argv[3], NULL);
  239. text = argv[4];
  240. charcount = strlen(text);
  241. len = (charcount > bufsize) ? bufsize : charcount;
  242. for (k = 0; k < len; ++k)
  243. buf[k] = (text[k] << 8) | color;
  244. res = osd_write_videomem(screen, y * base_width + x, buf, len);
  245. if (res < 0)
  246. return res;
  247. OSD_SET_REG(screen, control, 0x0049);
  248. }
  249. return 0;
  250. }
  251. int osd_probe(unsigned screen)
  252. {
  253. u16 version;
  254. u16 features;
  255. int old_bus = i2c_get_bus_num();
  256. bool pixclock_present = false;
  257. bool output_driver_present = false;
  258. OSD_GET_REG(0, version, &version);
  259. OSD_GET_REG(0, features, &features);
  260. base_width = ((features & 0x3f00) >> 8) + 1;
  261. base_height = (features & 0x001f) + 1;
  262. bufsize = base_width * base_height;
  263. buf = malloc(sizeof(u16) * bufsize);
  264. if (!buf)
  265. return -1;
  266. #ifdef CONFIG_SYS_OSD_DH
  267. printf("OSD%d-%d: Digital-OSD version %01d.%02d, %d" "x%d characters\n",
  268. (screen >= OSD_DH_BASE) ? (screen - OSD_DH_BASE) : screen,
  269. (screen > 3) ? 1 : 0, version/100, version%100, base_width,
  270. base_height);
  271. #else
  272. printf("OSD%d: Digital-OSD version %01d.%02d, %d" "x%d characters\n",
  273. screen, version/100, version%100, base_width, base_height);
  274. #endif
  275. /* setup pixclock */
  276. #ifdef CONFIG_SYS_MPC92469AC
  277. pixclock_present = true;
  278. mpc92469ac_set(screen, PIXCLK_640_480_60);
  279. #endif
  280. #ifdef CONFIG_SYS_ICS8N3QV01_I2C
  281. i2c_set_bus_num(ics8n3qv01_i2c[screen]);
  282. if (!i2c_probe(ICS8N3QV01_I2C_ADDR)) {
  283. ics8n3qv01_set(PIXCLK_640_480_60);
  284. pixclock_present = true;
  285. }
  286. #endif
  287. if (!pixclock_present)
  288. printf(" no pixelclock found\n");
  289. /* setup output driver */
  290. #ifdef CONFIG_SYS_CH7301_I2C
  291. if (!ch7301_probe(screen, true))
  292. output_driver_present = true;
  293. #endif
  294. #ifdef CONFIG_SYS_SIL1178_I2C
  295. i2c_set_bus_num(sil1178_i2c[screen]);
  296. if (!i2c_probe(SIL1178_SLAVE_I2C_ADDRESS)) {
  297. if (i2c_reg_read(SIL1178_SLAVE_I2C_ADDRESS, 0x02) == 0x06) {
  298. /*
  299. * magic initialization sequence,
  300. * adapted from datasheet
  301. */
  302. i2c_reg_write(SIL1178_SLAVE_I2C_ADDRESS, 0x08, 0x36);
  303. i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x0f, 0x44);
  304. i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x0f, 0x4c);
  305. i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x0e, 0x10);
  306. i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x0a, 0x80);
  307. i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x09, 0x30);
  308. i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x0c, 0x89);
  309. i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x0d, 0x60);
  310. i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x08, 0x36);
  311. i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x08, 0x37);
  312. output_driver_present = true;
  313. }
  314. }
  315. #endif
  316. #ifdef CONFIG_SYS_DP501_I2C
  317. if (!dp501_probe(screen, true))
  318. output_driver_present = true;
  319. #endif
  320. if (!output_driver_present)
  321. printf(" no output driver found\n");
  322. OSD_SET_REG(screen, xy_size, ((32 - 1) << 8) | (16 - 1));
  323. OSD_SET_REG(screen, x_pos, 0x007f);
  324. OSD_SET_REG(screen, y_pos, 0x005f);
  325. if (pixclock_present && output_driver_present)
  326. osd_screen_mask |= 1 << screen;
  327. i2c_set_bus_num(old_bus);
  328. return 0;
  329. }
  330. int osd_write(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
  331. {
  332. unsigned screen;
  333. if ((argc < 4) || (strlen(argv[3]) % 4)) {
  334. cmd_usage(cmdtp);
  335. return 1;
  336. }
  337. for (screen = 0; screen < MAX_OSD_SCREEN; ++screen) {
  338. unsigned x;
  339. unsigned y;
  340. unsigned k;
  341. u16 buffer[base_width];
  342. char *rp;
  343. u16 *wp = buffer;
  344. unsigned count = (argc > 4) ?
  345. hextoul(argv[4], NULL) : 1;
  346. if (!(osd_screen_mask & (1 << screen)))
  347. continue;
  348. x = hextoul(argv[1], NULL);
  349. y = hextoul(argv[2], NULL);
  350. rp = argv[3];
  351. while (*rp) {
  352. char substr[5];
  353. memcpy(substr, rp, 4);
  354. substr[4] = 0;
  355. *wp = hextoul(substr, NULL);
  356. rp += 4;
  357. wp++;
  358. if (wp - buffer > base_width)
  359. break;
  360. }
  361. for (k = 0; k < count; ++k) {
  362. unsigned offset =
  363. y * base_width + x + k * (wp - buffer);
  364. osd_write_videomem(screen, offset, buffer,
  365. wp - buffer);
  366. }
  367. OSD_SET_REG(screen, control, 0x0049);
  368. }
  369. return 0;
  370. }
  371. int osd_size(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
  372. {
  373. unsigned screen;
  374. unsigned x;
  375. unsigned y;
  376. if (argc < 3) {
  377. cmd_usage(cmdtp);
  378. return 1;
  379. }
  380. x = hextoul(argv[1], NULL);
  381. y = hextoul(argv[2], NULL);
  382. if (!x || (x > 64) || (x > MAX_X_CHARS) ||
  383. !y || (y > 32) || (y > MAX_Y_CHARS)) {
  384. cmd_usage(cmdtp);
  385. return 1;
  386. }
  387. for (screen = 0; screen < MAX_OSD_SCREEN; ++screen) {
  388. if (!(osd_screen_mask & (1 << screen)))
  389. continue;
  390. OSD_SET_REG(screen, xy_size, ((x - 1) << 8) | (y - 1));
  391. OSD_SET_REG(screen, x_pos, 32767 * (640 - 12 * x) / 65535);
  392. OSD_SET_REG(screen, y_pos, 32767 * (480 - 18 * y) / 65535);
  393. }
  394. return 0;
  395. }
  396. U_BOOT_CMD(
  397. osdw, 5, 0, osd_write,
  398. "write 16-bit hex encoded buffer to osd memory",
  399. "pos_x pos_y buffer count\n"
  400. );
  401. U_BOOT_CMD(
  402. osdp, 5, 0, osd_print,
  403. "write ASCII buffer to osd memory",
  404. "pos_x pos_y color text\n"
  405. );
  406. U_BOOT_CMD(
  407. osdsize, 3, 0, osd_size,
  408. "set OSD XY size in characters",
  409. "size_x(max. " __stringify(MAX_X_CHARS)
  410. ") size_y(max. " __stringify(MAX_Y_CHARS) ")\n"
  411. );
  412. #endif /* CONFIG_GDSYS_LEGACY_DRIVERS */