p1_p2_rdb_pc.c 10 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2010-2011, 2013 Freescale Semiconductor, Inc.
  4. * Copyright 2020 NXP
  5. */
  6. #include <common.h>
  7. #include <command.h>
  8. #include <env.h>
  9. #include <hang.h>
  10. #include <hwconfig.h>
  11. #include <image.h>
  12. #include <init.h>
  13. #include <net.h>
  14. #include <pci.h>
  15. #include <i2c.h>
  16. #include <asm/processor.h>
  17. #include <asm/mmu.h>
  18. #include <asm/cache.h>
  19. #include <asm/immap_85xx.h>
  20. #include <asm/fsl_pci.h>
  21. #include <fsl_ddr_sdram.h>
  22. #include <asm/io.h>
  23. #include <asm/fsl_law.h>
  24. #include <asm/fsl_lbc.h>
  25. #include <asm/mp.h>
  26. #include <miiphy.h>
  27. #include <linux/delay.h>
  28. #include <linux/libfdt.h>
  29. #include <fdt_support.h>
  30. #include <fsl_mdio.h>
  31. #include <tsec.h>
  32. #include <vsc7385.h>
  33. #include <ioports.h>
  34. #include <asm/fsl_serdes.h>
  35. #include <netdev.h>
  36. #ifdef CONFIG_QE
  37. #define GPIO_GETH_SW_PORT 1
  38. #define GPIO_GETH_SW_PIN 29
  39. #define GPIO_GETH_SW_DATA (1 << (31 - GPIO_GETH_SW_PIN))
  40. #define GPIO_SLIC_PORT 1
  41. #define GPIO_SLIC_PIN 30
  42. #define GPIO_SLIC_DATA (1 << (31 - GPIO_SLIC_PIN))
  43. const qe_iop_conf_t qe_iop_conf_tab[] = {
  44. /* GPIO */
  45. {1, 1, 2, 0, 0}, /* GPIO7/PB1 - LOAD_DEFAULT_N */
  46. {0, 15, 1, 0, 0}, /* GPIO11/A15 - WDI */
  47. {GPIO_GETH_SW_PORT, GPIO_GETH_SW_PIN, 1, 0, 0}, /* RST_GETH_SW_N */
  48. {GPIO_SLIC_PORT, GPIO_SLIC_PIN, 1, 0, 0}, /* RST_SLIC_N */
  49. {0, 0, 0, 0, QE_IOP_TAB_END} /* END of table */
  50. };
  51. #endif
  52. struct cpld_data {
  53. u8 cpld_rev_major;
  54. u8 pcba_rev;
  55. u8 wd_cfg;
  56. u8 rst_bps_sw;
  57. u8 load_default_n;
  58. u8 rst_bps_wd;
  59. u8 bypass_enable;
  60. u8 bps_led;
  61. u8 status_led; /* offset: 0x8 */
  62. u8 fxo_led; /* offset: 0x9 */
  63. u8 fxs_led; /* offset: 0xa */
  64. u8 rev4[2];
  65. u8 system_rst; /* offset: 0xd */
  66. u8 bps_out;
  67. u8 rev5[3];
  68. u8 cpld_rev_minor;
  69. };
  70. #define CPLD_WD_CFG 0x03
  71. #define CPLD_RST_BSW 0x00
  72. #define CPLD_RST_BWD 0x00
  73. #define CPLD_BYPASS_EN 0x03
  74. #define CPLD_STATUS_LED 0x01
  75. #define CPLD_FXO_LED 0x01
  76. #define CPLD_FXS_LED 0x0F
  77. #define CPLD_SYS_RST 0x00
  78. void board_cpld_init(void)
  79. {
  80. struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
  81. out_8(&cpld_data->wd_cfg, CPLD_WD_CFG);
  82. out_8(&cpld_data->status_led, CPLD_STATUS_LED);
  83. out_8(&cpld_data->fxo_led, CPLD_FXO_LED);
  84. out_8(&cpld_data->fxs_led, CPLD_FXS_LED);
  85. out_8(&cpld_data->system_rst, CPLD_SYS_RST);
  86. }
  87. void board_gpio_init(void)
  88. {
  89. #ifdef CONFIG_QE
  90. ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  91. par_io_t *par_io = (par_io_t *) &(gur->qe_par_io);
  92. /* Enable VSC7385 switch */
  93. setbits_be32(&par_io[GPIO_GETH_SW_PORT].cpdat, GPIO_GETH_SW_DATA);
  94. /* Enable SLIC */
  95. setbits_be32(&par_io[GPIO_SLIC_PORT].cpdat, GPIO_SLIC_DATA);
  96. #else
  97. ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
  98. /*
  99. * GPIO10 DDR Reset, open drain
  100. * GPIO7 LOAD_DEFAULT_N Input
  101. * GPIO11 WDI (watchdog input)
  102. * GPIO12 Ethernet Switch Reset
  103. * GPIO13 SLIC Reset
  104. */
  105. setbits_be32(&pgpio->gpdir, 0x02130000);
  106. #if !defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_SPL)
  107. /* init DDR3 reset signal */
  108. setbits_be32(&pgpio->gpdir, 0x00200000);
  109. setbits_be32(&pgpio->gpodr, 0x00200000);
  110. clrbits_be32(&pgpio->gpdat, 0x00200000);
  111. udelay(1000);
  112. setbits_be32(&pgpio->gpdat, 0x00200000);
  113. udelay(1000);
  114. clrbits_be32(&pgpio->gpdir, 0x00200000);
  115. #endif
  116. #ifdef CONFIG_VSC7385_ENET
  117. /* reset VSC7385 Switch */
  118. setbits_be32(&pgpio->gpdir, 0x00080000);
  119. setbits_be32(&pgpio->gpdat, 0x00080000);
  120. #endif
  121. #ifdef CONFIG_SLIC
  122. /* reset SLIC */
  123. setbits_be32(&pgpio->gpdir, 0x00040000);
  124. setbits_be32(&pgpio->gpdat, 0x00040000);
  125. #endif
  126. #endif
  127. }
  128. int board_early_init_f(void)
  129. {
  130. ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  131. setbits_be32(&gur->pmuxcr,
  132. (MPC85xx_PMUXCR_SDHC_CD | MPC85xx_PMUXCR_SDHC_WP));
  133. clrbits_be32(&gur->sdhcdcr, SDHCDCR_CD_INV);
  134. clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_SD_DATA);
  135. setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_TDM_ENA);
  136. board_gpio_init();
  137. board_cpld_init();
  138. return 0;
  139. }
  140. int checkboard(void)
  141. {
  142. struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
  143. ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  144. u8 in, out, io_config, val;
  145. int bus_num = CONFIG_SYS_SPD_BUS_NUM;
  146. printf("Board: %s CPLD: V%d.%d PCBA: V%d.0\n", CONFIG_BOARDNAME,
  147. in_8(&cpld_data->cpld_rev_major) & 0x0F,
  148. in_8(&cpld_data->cpld_rev_minor) & 0x0F,
  149. in_8(&cpld_data->pcba_rev) & 0x0F);
  150. /* Initialize i2c early for rom_loc and flash bank information */
  151. #if CONFIG_IS_ENABLED(DM_I2C)
  152. struct udevice *dev;
  153. int ret;
  154. ret = i2c_get_chip_for_busnum(bus_num, CONFIG_SYS_I2C_PCA9557_ADDR,
  155. 1, &dev);
  156. if (ret) {
  157. printf("%s: Cannot find udev for a bus %d\n", __func__,
  158. bus_num);
  159. return -ENXIO;
  160. }
  161. if (dm_i2c_read(dev, 0, &in, 1) < 0 ||
  162. dm_i2c_read(dev, 1, &out, 1) < 0 ||
  163. dm_i2c_read(dev, 3, &io_config, 1) < 0) {
  164. printf("Error reading i2c boot information!\n");
  165. return 0; /* Don't want to hang() on this error */
  166. }
  167. #else /* Non DM I2C support - will be removed */
  168. i2c_set_bus_num(bus_num);
  169. if (i2c_read(CONFIG_SYS_I2C_PCA9557_ADDR, 0, 1, &in, 1) < 0 ||
  170. i2c_read(CONFIG_SYS_I2C_PCA9557_ADDR, 1, 1, &out, 1) < 0 ||
  171. i2c_read(CONFIG_SYS_I2C_PCA9557_ADDR, 3, 1, &io_config, 1) < 0) {
  172. printf("Error reading i2c boot information!\n");
  173. return 0; /* Don't want to hang() on this error */
  174. }
  175. #endif
  176. val = (in & io_config) | (out & (~io_config));
  177. puts("rom_loc: ");
  178. if ((val & (~__SW_BOOT_MASK)) == __SW_BOOT_SD) {
  179. puts("sd");
  180. #ifdef __SW_BOOT_SPI
  181. } else if ((val & (~__SW_BOOT_MASK)) == __SW_BOOT_SPI) {
  182. puts("spi");
  183. #endif
  184. #ifdef __SW_BOOT_NAND
  185. } else if ((val & (~__SW_BOOT_MASK)) == __SW_BOOT_NAND) {
  186. puts("nand");
  187. #endif
  188. #ifdef __SW_BOOT_PCIE
  189. } else if ((val & (~__SW_BOOT_MASK)) == __SW_BOOT_PCIE) {
  190. puts("pcie");
  191. #endif
  192. } else {
  193. if (val & 0x2)
  194. puts("nor lower bank");
  195. else
  196. puts("nor upper bank");
  197. }
  198. puts("\n");
  199. if (val & 0x1) {
  200. setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_SD_DATA);
  201. puts("SD/MMC : 8-bit Mode\n");
  202. puts("eSPI : Disabled\n");
  203. } else {
  204. puts("SD/MMC : 4-bit Mode\n");
  205. puts("eSPI : Enabled\n");
  206. }
  207. return 0;
  208. }
  209. #if defined(CONFIG_PCI) && !defined(CONFIG_DM_PCI)
  210. void pci_init_board(void)
  211. {
  212. fsl_pcie_init_board(0);
  213. }
  214. #endif
  215. int board_early_init_r(void)
  216. {
  217. const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
  218. int flash_esel = find_tlb_idx((void *)flashbase, 1);
  219. #ifdef CONFIG_VSC7385_ENET
  220. unsigned int vscfw_addr;
  221. char *tmp;
  222. #endif
  223. /*
  224. * Remap Boot flash region to caching-inhibited
  225. * so that flash can be erased properly.
  226. */
  227. /* Flush d-cache and invalidate i-cache of any FLASH data */
  228. flush_dcache();
  229. invalidate_icache();
  230. if (flash_esel == -1) {
  231. /* very unlikely unless something is messed up */
  232. puts("Error: Could not find TLB for FLASH BASE\n");
  233. flash_esel = 2; /* give our best effort to continue */
  234. } else {
  235. /* invalidate existing TLB entry for flash */
  236. disable_tlb(flash_esel);
  237. }
  238. set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */
  239. MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,/* perms, wimge */
  240. 0, flash_esel, BOOKE_PAGESZ_64M, 1);/* ts, esel, tsize, iprot */
  241. #ifdef CONFIG_VSC7385_ENET
  242. /* If a VSC7385 microcode image is present, then upload it. */
  243. tmp = env_get("vscfw_addr");
  244. if (tmp) {
  245. vscfw_addr = hextoul(tmp, NULL);
  246. printf("uploading VSC7385 microcode from %x\n", vscfw_addr);
  247. if (vsc7385_upload_firmware((void *)vscfw_addr,
  248. CONFIG_VSC7385_IMAGE_SIZE))
  249. puts("Failure uploading VSC7385 microcode.\n");
  250. } else {
  251. puts("No address specified for VSC7385 microcode.\n");
  252. }
  253. #endif
  254. return 0;
  255. }
  256. #ifndef CONFIG_DM_ETH
  257. int board_eth_init(struct bd_info *bis)
  258. {
  259. struct fsl_pq_mdio_info mdio_info;
  260. struct tsec_info_struct tsec_info[4];
  261. ccsr_gur_t *gur __attribute__((unused)) =
  262. (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  263. int num = 0;
  264. #ifdef CONFIG_TSEC1
  265. SET_STD_TSEC_INFO(tsec_info[num], 1);
  266. num++;
  267. #endif
  268. #ifdef CONFIG_TSEC2
  269. SET_STD_TSEC_INFO(tsec_info[num], 2);
  270. if (is_serdes_configured(SGMII_TSEC2)) {
  271. printf("eTSEC2 is in sgmii mode.\n");
  272. tsec_info[num].flags |= TSEC_SGMII;
  273. }
  274. num++;
  275. #endif
  276. #ifdef CONFIG_TSEC3
  277. SET_STD_TSEC_INFO(tsec_info[num], 3);
  278. num++;
  279. #endif
  280. if (!num) {
  281. printf("No TSECs initialized\n");
  282. return 0;
  283. }
  284. mdio_info.regs = TSEC_GET_MDIO_REGS_BASE(1);
  285. mdio_info.name = DEFAULT_MII_NAME;
  286. fsl_pq_mdio_init(bis, &mdio_info);
  287. tsec_eth_init(bis, tsec_info, num);
  288. #if defined(CONFIG_UEC_ETH)
  289. /* QE0 and QE3 need to be exposed for UCC1 and UCC5 Eth mode */
  290. setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE0);
  291. setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE3);
  292. uec_standard_init(bis);
  293. #endif
  294. return pci_eth_init(bis);
  295. }
  296. #endif
  297. #ifdef CONFIG_OF_BOARD_SETUP
  298. int ft_board_setup(void *blob, struct bd_info *bd)
  299. {
  300. phys_addr_t base;
  301. phys_size_t size;
  302. #if defined(CONFIG_TARGET_P1020RDB_PD) || defined(CONFIG_TARGET_P1020RDB_PC)
  303. const char *soc_usb_compat = "fsl-usb2-dr";
  304. int usb_err, usb1_off, usb2_off;
  305. #endif
  306. #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
  307. int err;
  308. #endif
  309. ft_cpu_setup(blob, bd);
  310. base = env_get_bootm_low();
  311. size = env_get_bootm_size();
  312. fdt_fixup_memory(blob, (u64)base, (u64)size);
  313. #if !defined(CONFIG_DM_PCI)
  314. FT_FSL_PCI_SETUP;
  315. #endif
  316. #ifdef CONFIG_QE
  317. do_fixup_by_compat(blob, "fsl,qe", "status", "okay",
  318. sizeof("okay"), 0);
  319. #endif
  320. #if defined(CONFIG_HAS_FSL_DR_USB)
  321. fsl_fdt_fixup_dr_usb(blob, bd);
  322. #endif
  323. #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
  324. /* Delete eLBC node as it is muxed with USB2 controller */
  325. if (hwconfig("usb2")) {
  326. const char *soc_elbc_compat = "fsl,p1020-elbc";
  327. int off = fdt_node_offset_by_compatible(blob, -1,
  328. soc_elbc_compat);
  329. if (off < 0) {
  330. printf("WARNING: could not find compatible node %s\n",
  331. soc_elbc_compat);
  332. return off;
  333. }
  334. err = fdt_del_node(blob, off);
  335. if (err < 0) {
  336. printf("WARNING: could not remove %s\n",
  337. soc_elbc_compat);
  338. return err;
  339. }
  340. return 0;
  341. }
  342. #endif
  343. #if defined(CONFIG_TARGET_P1020RDB_PD) || defined(CONFIG_TARGET_P1020RDB_PC)
  344. /* Delete USB2 node as it is muxed with eLBC */
  345. usb1_off = fdt_node_offset_by_compatible(blob, -1,
  346. soc_usb_compat);
  347. if (usb1_off < 0) {
  348. printf("WARNING: could not find compatible node %s\n",
  349. soc_usb_compat);
  350. return usb1_off;
  351. }
  352. usb2_off = fdt_node_offset_by_compatible(blob, usb1_off,
  353. soc_usb_compat);
  354. if (usb2_off < 0) {
  355. printf("WARNING: could not find compatible node %s\n",
  356. soc_usb_compat);
  357. return usb2_off;
  358. }
  359. usb_err = fdt_del_node(blob, usb2_off);
  360. if (usb_err < 0) {
  361. printf("WARNING: could not remove %s\n", soc_usb_compat);
  362. return usb_err;
  363. }
  364. #endif
  365. return 0;
  366. }
  367. #endif