eth_lx2162aqds.c 26 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967968969970971972973974975
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2020 NXP
  4. *
  5. */
  6. #include <common.h>
  7. #include <env.h>
  8. #include <fdt_support.h>
  9. #include <hwconfig.h>
  10. #include <command.h>
  11. #include <log.h>
  12. #include <net.h>
  13. #include <netdev.h>
  14. #include <malloc.h>
  15. #include <fsl_mdio.h>
  16. #include <miiphy.h>
  17. #include <phy.h>
  18. #include <fm_eth.h>
  19. #include <asm/io.h>
  20. #include <exports.h>
  21. #include <asm/global_data.h>
  22. #include <asm/arch/fsl_serdes.h>
  23. #include <fsl-mc/fsl_mc.h>
  24. #include <fsl-mc/ldpaa_wriop.h>
  25. #include <linux/libfdt.h>
  26. #include "../common/qixis.h"
  27. DECLARE_GLOBAL_DATA_PTR;
  28. #ifndef CONFIG_DM_ETH
  29. #define EMI_NONE 0
  30. #define EMI1 1 /* Mdio Bus 1 */
  31. #define EMI2 2 /* Mdio Bus 2 */
  32. #if defined(CONFIG_FSL_MC_ENET)
  33. enum io_slot {
  34. IO_SLOT_NONE = 0,
  35. IO_SLOT_1,
  36. IO_SLOT_2,
  37. IO_SLOT_3,
  38. IO_SLOT_4,
  39. IO_SLOT_5,
  40. IO_SLOT_6,
  41. IO_SLOT_7,
  42. IO_SLOT_8,
  43. EMI1_RGMII1,
  44. EMI1_RGMII2,
  45. IO_SLOT_MAX
  46. };
  47. struct lx2162a_qds_mdio {
  48. enum io_slot ioslot : 4;
  49. u8 realbusnum : 4;
  50. struct mii_dev *realbus;
  51. };
  52. /* structure explaining the phy configuration on 8 lanes of a serdes*/
  53. struct serdes_phy_config {
  54. u8 serdes; /* serdes protocol */
  55. struct phy_config {
  56. u8 dpmacid;
  57. /* -1 terminated array */
  58. int phy_address[WRIOP_MAX_PHY_NUM + 1];
  59. u8 mdio_bus;
  60. enum io_slot ioslot;
  61. } phy_config[SRDS_MAX_LANES];
  62. };
  63. /* Table defining the phy configuration on 8 lanes of a serdes.
  64. * Various assumptions have been made while defining this table.
  65. * e.g. for serdes1 protocol 19 it is being assumed that X-M11-USXGMII
  66. * card is being used for dpmac 3-4. (X-M12-XFI could also have been used)
  67. * And also that this card is connected to IO Slot 1 (could have been connected
  68. * to any of the 8 IO slots (IO slot 1 - IO slot 8)).
  69. * similarly, it is also being assumed that MDIO 1 is selected on X-M7-40G card
  70. * used in serdes1 protocol 19 (could have selected MDIO 2)
  71. * To override these settings "dpmac" environment variable can be used after
  72. * defining "dpmac_override" in hwconfig environment variable.
  73. * This table has limited serdes protocol entries. It can be expanded as per
  74. * requirement.
  75. */
  76. /*****************************************************************
  77. *| SERDES_1 PROTOCOL | IO_SLOT | CARD |
  78. ******************************************************************
  79. *| 2 | IO_SLOT_1 | M4-PCIE-SGMII |
  80. *| 3 | IO_SLOT_1 | M11-USXGMII |
  81. *| 15 | IO_SLOT_1 | M13-25G |
  82. *| 17 | IO_SLOT_1 | M13-25G |
  83. *| 18 | IO_SLOT_1 | M11-USXGMII |
  84. *| | IO_SLOT_6 | M13-25G |
  85. *| 20 | IO_SLOT_1 | M7-40G |
  86. *****************************************************************
  87. */
  88. static const struct serdes_phy_config serdes1_phy_config[] = {
  89. {1, {} },
  90. {2, {{WRIOP1_DPMAC3, {SGMII_CARD_PORT1_PHY_ADDR, -1},
  91. EMI1, IO_SLOT_1},
  92. {WRIOP1_DPMAC4, {SGMII_CARD_PORT2_PHY_ADDR, -1},
  93. EMI1, IO_SLOT_1},
  94. {WRIOP1_DPMAC5, {SGMII_CARD_PORT3_PHY_ADDR, -1},
  95. EMI1, IO_SLOT_1},
  96. {WRIOP1_DPMAC6, {SGMII_CARD_PORT4_PHY_ADDR, -1},
  97. EMI1, IO_SLOT_1} } },
  98. {3, {{WRIOP1_DPMAC3, {AQ_PHY_ADDR1, -1},
  99. EMI1, IO_SLOT_1},
  100. {WRIOP1_DPMAC4, {AQ_PHY_ADDR2, -1},
  101. EMI1, IO_SLOT_1},
  102. {WRIOP1_DPMAC5, {AQ_PHY_ADDR3, -1},
  103. EMI1, IO_SLOT_1},
  104. {WRIOP1_DPMAC6, {AQ_PHY_ADDR4, -1},
  105. EMI1, IO_SLOT_1} } },
  106. {15, {{WRIOP1_DPMAC1, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
  107. EMI1, IO_SLOT_1},
  108. {WRIOP1_DPMAC2, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
  109. EMI1, IO_SLOT_1} } },
  110. {17, {{WRIOP1_DPMAC3, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
  111. EMI1, IO_SLOT_1},
  112. {WRIOP1_DPMAC4, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
  113. EMI1, IO_SLOT_1},
  114. {WRIOP1_DPMAC5, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
  115. EMI1, IO_SLOT_1},
  116. {WRIOP1_DPMAC6, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
  117. EMI1, IO_SLOT_1} } },
  118. {18, {{WRIOP1_DPMAC3, {AQ_PHY_ADDR1, -1},
  119. EMI1, IO_SLOT_1},
  120. {WRIOP1_DPMAC4, {AQ_PHY_ADDR2, -1},
  121. EMI1, IO_SLOT_1},
  122. {WRIOP1_DPMAC5, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
  123. EMI1, IO_SLOT_6},
  124. {WRIOP1_DPMAC6, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
  125. EMI1, IO_SLOT_6} } },
  126. {20, {{WRIOP1_DPMAC1, {CORTINA_PHY_ADDR1, -1},
  127. EMI1, IO_SLOT_1} } }
  128. };
  129. /*****************************************************************
  130. *| SERDES_2 PROTOCOL | IO_SLOT | CARD |
  131. ******************************************************************
  132. *| 2 | IO_SLOT_7 | M4-PCIE-SGMII |
  133. *| | IO_SLOT_8 | M4-PCIE-SGMII |
  134. *| 3 | IO_SLOT_7 | M4-PCIE-SGMII |
  135. *| | IO_SLOT_8 | M4-PCIE-SGMII |
  136. *| 5 | IO_SLOT_7 | M4-PCIE-SGMII |
  137. *| 10 | IO_SLOT_7 | M4-PCIE-SGMII |
  138. *| | IO_SLOT_8 | M4-PCIE-SGMII |
  139. *| 11 | IO_SLOT_7 | M4-PCIE-SGMII |
  140. *| | IO_SLOT_8 | M4-PCIE-SGMII |
  141. *| 12 | IO_SLOT_7 | M4-PCIE-SGMII |
  142. *| | IO_SLOT_8 | M4-PCIE-SGMII |
  143. ******************************************************************
  144. */
  145. static const struct serdes_phy_config serdes2_phy_config[] = {
  146. {2, {} },
  147. {3, {} },
  148. {5, {} },
  149. {10, {{WRIOP1_DPMAC11, {SGMII_CARD_PORT1_PHY_ADDR, -1},
  150. EMI1, IO_SLOT_7},
  151. {WRIOP1_DPMAC12, {SGMII_CARD_PORT2_PHY_ADDR, -1},
  152. EMI1, IO_SLOT_7},
  153. {WRIOP1_DPMAC17, {SGMII_CARD_PORT3_PHY_ADDR, -1},
  154. EMI1, IO_SLOT_7},
  155. {WRIOP1_DPMAC18, {SGMII_CARD_PORT4_PHY_ADDR, -1},
  156. EMI1, IO_SLOT_7} } },
  157. {11, {{WRIOP1_DPMAC12, {SGMII_CARD_PORT2_PHY_ADDR, -1},
  158. EMI1, IO_SLOT_7},
  159. {WRIOP1_DPMAC17, {SGMII_CARD_PORT3_PHY_ADDR, -1},
  160. EMI1, IO_SLOT_7},
  161. {WRIOP1_DPMAC18, {SGMII_CARD_PORT4_PHY_ADDR, -1},
  162. EMI1, IO_SLOT_7},
  163. {WRIOP1_DPMAC16, {SGMII_CARD_PORT2_PHY_ADDR, -1},
  164. EMI1, IO_SLOT_8},
  165. {WRIOP1_DPMAC13, {SGMII_CARD_PORT3_PHY_ADDR, -1},
  166. EMI1, IO_SLOT_8},
  167. {WRIOP1_DPMAC14, {SGMII_CARD_PORT4_PHY_ADDR, -1},
  168. EMI1, IO_SLOT_8} } },
  169. {12, {{WRIOP1_DPMAC11, {SGMII_CARD_PORT1_PHY_ADDR, -1},
  170. EMI1, IO_SLOT_7},
  171. {WRIOP1_DPMAC12, {SGMII_CARD_PORT2_PHY_ADDR, -1},
  172. EMI1, IO_SLOT_7},
  173. {WRIOP1_DPMAC17, {SGMII_CARD_PORT3_PHY_ADDR, -1},
  174. EMI1, IO_SLOT_7},
  175. {WRIOP1_DPMAC18, {SGMII_CARD_PORT4_PHY_ADDR, -1},
  176. EMI1, IO_SLOT_7} } }
  177. };
  178. static inline
  179. const struct phy_config *get_phy_config(u8 serdes,
  180. const struct serdes_phy_config *table,
  181. u8 table_size)
  182. {
  183. int i;
  184. for (i = 0; i < table_size; i++) {
  185. if (table[i].serdes == serdes)
  186. return table[i].phy_config;
  187. }
  188. return NULL;
  189. }
  190. /* BRDCFG4 controls EMI routing for the board.
  191. * Bits Function
  192. * 7-6 EMI Interface #1 Primary Routing (CFG_MUX1_EMI1) (1.8V):
  193. * EMI1 00= On-board PHY #1
  194. * 01= On-board PHY #2
  195. * 10= (reserved)
  196. * 11= Slots 1..8 multiplexer and translator.
  197. * 5-3 EMI Interface #1 Secondary Routing (CFG_MUX2_EMI1) (2.5V):
  198. * EMI1X 000= Slot #1
  199. * 001= Slot #2
  200. * 010= Slot #3
  201. * 011= Slot #4
  202. * 100= Slot #5
  203. * 101= Slot #6
  204. * 110= Slot #7
  205. * 111= Slot #8
  206. * 2-0 EMI Interface #2 Routing (CFG_MUX_EMI2):
  207. * EMI2 000= Slot #1 (secondary EMI)
  208. * 001= Slot #2 (secondary EMI)
  209. * 010= Slot #3 (secondary EMI)
  210. * 011= Slot #4 (secondary EMI)
  211. * 100= Slot #5 (secondary EMI)
  212. * 101= Slot #6 (secondary EMI)
  213. * 110= Slot #7 (secondary EMI)
  214. * 111= Slot #8 (secondary EMI)
  215. */
  216. static int lx2162a_qds_get_mdio_mux_val(u8 realbusnum, enum io_slot ioslot)
  217. {
  218. switch (realbusnum) {
  219. case EMI1:
  220. switch (ioslot) {
  221. case EMI1_RGMII1:
  222. return 0;
  223. case EMI1_RGMII2:
  224. return 0x40;
  225. default:
  226. return (((ioslot - 1) << BRDCFG4_EMI1SEL_SHIFT) | 0xC0);
  227. }
  228. break;
  229. case EMI2:
  230. return ((ioslot - 1) << BRDCFG4_EMI2SEL_SHIFT);
  231. default:
  232. return -1;
  233. }
  234. }
  235. static void lx2162a_qds_mux_mdio(struct lx2162a_qds_mdio *priv)
  236. {
  237. u8 brdcfg4, mux_val, reg;
  238. brdcfg4 = QIXIS_READ(brdcfg[4]);
  239. reg = brdcfg4;
  240. mux_val = lx2162a_qds_get_mdio_mux_val(priv->realbusnum, priv->ioslot);
  241. switch (priv->realbusnum) {
  242. case EMI1:
  243. brdcfg4 &= ~BRDCFG4_EMI1SEL_MASK;
  244. brdcfg4 |= mux_val;
  245. break;
  246. case EMI2:
  247. brdcfg4 &= ~BRDCFG4_EMI2SEL_MASK;
  248. brdcfg4 |= mux_val;
  249. break;
  250. }
  251. if (brdcfg4 ^ reg)
  252. QIXIS_WRITE(brdcfg[4], brdcfg4);
  253. }
  254. static int lx2162a_qds_mdio_read(struct mii_dev *bus, int addr,
  255. int devad, int regnum)
  256. {
  257. struct lx2162a_qds_mdio *priv = bus->priv;
  258. lx2162a_qds_mux_mdio(priv);
  259. return priv->realbus->read(priv->realbus, addr, devad, regnum);
  260. }
  261. static int lx2162a_qds_mdio_write(struct mii_dev *bus, int addr, int devad,
  262. int regnum, u16 value)
  263. {
  264. struct lx2162a_qds_mdio *priv = bus->priv;
  265. lx2162a_qds_mux_mdio(priv);
  266. return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
  267. }
  268. static int lx2162a_qds_mdio_reset(struct mii_dev *bus)
  269. {
  270. struct lx2162a_qds_mdio *priv = bus->priv;
  271. return priv->realbus->reset(priv->realbus);
  272. }
  273. static struct mii_dev *lx2162a_qds_mdio_init(u8 realbusnum, enum io_slot ioslot)
  274. {
  275. struct lx2162a_qds_mdio *pmdio;
  276. struct mii_dev *bus;
  277. /*should be within MDIO_NAME_LEN*/
  278. char dummy_mdio_name[] = "LX2162A_QDS_MDIO1_IOSLOT1";
  279. if (realbusnum == EMI2) {
  280. if (ioslot < IO_SLOT_1 || ioslot > IO_SLOT_8) {
  281. printf("invalid ioslot %d\n", ioslot);
  282. return NULL;
  283. }
  284. } else if (realbusnum == EMI1) {
  285. if (ioslot < IO_SLOT_1 || ioslot > EMI1_RGMII2) {
  286. printf("invalid ioslot %d\n", ioslot);
  287. return NULL;
  288. }
  289. } else {
  290. printf("not supported real mdio bus %d\n", realbusnum);
  291. return NULL;
  292. }
  293. if (ioslot == EMI1_RGMII1)
  294. strcpy(dummy_mdio_name, "LX2162A_QDS_MDIO1_RGMII1");
  295. else if (ioslot == EMI1_RGMII2)
  296. strcpy(dummy_mdio_name, "LX2162A_QDS_MDIO1_RGMII2");
  297. else
  298. sprintf(dummy_mdio_name, "LX2162A_QDS_MDIO%d_IOSLOT%d",
  299. realbusnum, ioslot);
  300. bus = miiphy_get_dev_by_name(dummy_mdio_name);
  301. if (bus)
  302. return bus;
  303. bus = mdio_alloc();
  304. if (!bus) {
  305. printf("Failed to allocate %s bus\n", dummy_mdio_name);
  306. return NULL;
  307. }
  308. pmdio = malloc(sizeof(*pmdio));
  309. if (!pmdio) {
  310. printf("Failed to allocate %s private data\n", dummy_mdio_name);
  311. free(bus);
  312. return NULL;
  313. }
  314. switch (realbusnum) {
  315. case EMI1:
  316. pmdio->realbus =
  317. miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO1_NAME);
  318. break;
  319. case EMI2:
  320. pmdio->realbus =
  321. miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME);
  322. break;
  323. }
  324. if (!pmdio->realbus) {
  325. printf("No real mdio bus num %d found\n", realbusnum);
  326. free(bus);
  327. free(pmdio);
  328. return NULL;
  329. }
  330. pmdio->realbusnum = realbusnum;
  331. pmdio->ioslot = ioslot;
  332. bus->read = lx2162a_qds_mdio_read;
  333. bus->write = lx2162a_qds_mdio_write;
  334. bus->reset = lx2162a_qds_mdio_reset;
  335. strcpy(bus->name, dummy_mdio_name);
  336. bus->priv = pmdio;
  337. if (!mdio_register(bus))
  338. return bus;
  339. printf("No bus with name %s\n", dummy_mdio_name);
  340. free(bus);
  341. free(pmdio);
  342. return NULL;
  343. }
  344. static inline void do_phy_config(const struct phy_config *phy_config)
  345. {
  346. struct mii_dev *bus;
  347. int i, phy_num, phy_address;
  348. for (i = 0; i < SRDS_MAX_LANES; i++) {
  349. if (!phy_config[i].dpmacid)
  350. continue;
  351. for (phy_num = 0;
  352. phy_num < ARRAY_SIZE(phy_config[i].phy_address);
  353. phy_num++) {
  354. phy_address = phy_config[i].phy_address[phy_num];
  355. if (phy_address == -1)
  356. break;
  357. wriop_set_phy_address(phy_config[i].dpmacid,
  358. phy_num, phy_address);
  359. }
  360. /*Register the muxing front-ends to the MDIO buses*/
  361. bus = lx2162a_qds_mdio_init(phy_config[i].mdio_bus,
  362. phy_config[i].ioslot);
  363. if (!bus)
  364. printf("could not get bus for mdio %d ioslot %d\n",
  365. phy_config[i].mdio_bus,
  366. phy_config[i].ioslot);
  367. else
  368. wriop_set_mdio(phy_config[i].dpmacid, bus);
  369. }
  370. }
  371. static inline void do_dpmac_config(int dpmac, const char *arg_dpmacid,
  372. char *env_dpmac)
  373. {
  374. const char *ret;
  375. size_t len;
  376. u8 realbusnum, ioslot;
  377. struct mii_dev *bus;
  378. int phy_num;
  379. char *phystr = "phy00";
  380. /*search phy in dpmac arg*/
  381. for (phy_num = 0; phy_num < WRIOP_MAX_PHY_NUM; phy_num++) {
  382. sprintf(phystr, "phy%d", phy_num + 1);
  383. ret = hwconfig_subarg_f(arg_dpmacid, phystr, &len, env_dpmac);
  384. if (!ret) {
  385. /*look for phy instead of phy1*/
  386. if (!phy_num)
  387. ret = hwconfig_subarg_f(arg_dpmacid, "phy",
  388. &len, env_dpmac);
  389. if (!ret)
  390. continue;
  391. }
  392. if (len != 4 || strncmp(ret, "0x", 2))
  393. printf("invalid phy format in %s variable.\n"
  394. "specify phy%d for %s in hex format e.g. 0x12\n",
  395. env_dpmac, phy_num + 1, arg_dpmacid);
  396. else
  397. wriop_set_phy_address(dpmac, phy_num,
  398. hextoul(ret, NULL));
  399. }
  400. /*search mdio in dpmac arg*/
  401. ret = hwconfig_subarg_f(arg_dpmacid, "mdio", &len, env_dpmac);
  402. if (ret)
  403. realbusnum = *ret - '0';
  404. else
  405. realbusnum = EMI_NONE;
  406. if (realbusnum) {
  407. /*search io in dpmac arg*/
  408. ret = hwconfig_subarg_f(arg_dpmacid, "io", &len, env_dpmac);
  409. if (ret)
  410. ioslot = *ret - '0';
  411. else
  412. ioslot = IO_SLOT_NONE;
  413. /*Register the muxing front-ends to the MDIO buses*/
  414. bus = lx2162a_qds_mdio_init(realbusnum, ioslot);
  415. if (!bus)
  416. printf("could not get bus for mdio %d ioslot %d\n",
  417. realbusnum, ioslot);
  418. else
  419. wriop_set_mdio(dpmac, bus);
  420. }
  421. }
  422. #endif
  423. #endif /* !CONFIG_DM_ETH */
  424. int board_eth_init(struct bd_info *bis)
  425. {
  426. #ifndef CONFIG_DM_ETH
  427. #if defined(CONFIG_FSL_MC_ENET)
  428. struct memac_mdio_info mdio_info;
  429. struct memac_mdio_controller *regs;
  430. int i;
  431. const char *ret;
  432. char *env_dpmac;
  433. char dpmacid[] = "dpmac00", srds[] = "00_00_00";
  434. size_t len;
  435. struct mii_dev *bus;
  436. const struct phy_config *phy_config;
  437. struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
  438. u32 srds_s1, srds_s2;
  439. srds_s1 = in_le32(&gur->rcwsr[28]) &
  440. FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK;
  441. srds_s1 >>= FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
  442. srds_s2 = in_le32(&gur->rcwsr[28]) &
  443. FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK;
  444. srds_s2 >>= FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT;
  445. sprintf(srds, "%d_%d", srds_s1, srds_s2);
  446. regs = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO1;
  447. mdio_info.regs = regs;
  448. mdio_info.name = DEFAULT_WRIOP_MDIO1_NAME;
  449. /*Register the EMI 1*/
  450. fm_memac_mdio_init(bis, &mdio_info);
  451. regs = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO2;
  452. mdio_info.regs = regs;
  453. mdio_info.name = DEFAULT_WRIOP_MDIO2_NAME;
  454. /*Register the EMI 2*/
  455. fm_memac_mdio_init(bis, &mdio_info);
  456. /* "dpmac" environment variable can be used after
  457. * defining "dpmac_override" in hwconfig environment variable.
  458. */
  459. if (hwconfig("dpmac_override")) {
  460. env_dpmac = env_get("dpmac");
  461. if (env_dpmac) {
  462. ret = hwconfig_arg_f("srds", &len, env_dpmac);
  463. if (ret) {
  464. if (strncmp(ret, srds, strlen(srds))) {
  465. printf("SERDES configuration changed.\n"
  466. "previous: %.*s, current: %s.\n"
  467. "update dpmac variable.\n",
  468. (int)len, ret, srds);
  469. }
  470. } else {
  471. printf("SERDES configuration not found.\n"
  472. "Please add srds:%s in dpmac variable\n",
  473. srds);
  474. }
  475. for (i = WRIOP1_DPMAC1; i < NUM_WRIOP_PORTS; i++) {
  476. /* Look for dpmac1 to dpmac24(current max) arg
  477. * in dpmac environment variable
  478. */
  479. sprintf(dpmacid, "dpmac%d", i);
  480. ret = hwconfig_arg_f(dpmacid, &len, env_dpmac);
  481. if (ret)
  482. do_dpmac_config(i, dpmacid, env_dpmac);
  483. }
  484. } else {
  485. printf("Warning: environment dpmac not found.\n"
  486. "DPAA network interfaces may not work\n");
  487. }
  488. } else {
  489. /*Look for phy config for serdes1 in phy config table*/
  490. phy_config = get_phy_config(srds_s1, serdes1_phy_config,
  491. ARRAY_SIZE(serdes1_phy_config));
  492. if (!phy_config) {
  493. printf("%s WRIOP: Unsupported SerDes1 Protocol %d\n",
  494. __func__, srds_s1);
  495. } else {
  496. do_phy_config(phy_config);
  497. }
  498. phy_config = get_phy_config(srds_s2, serdes2_phy_config,
  499. ARRAY_SIZE(serdes2_phy_config));
  500. if (!phy_config) {
  501. printf("%s WRIOP: Unsupported SerDes2 Protocol %d\n",
  502. __func__, srds_s2);
  503. } else {
  504. do_phy_config(phy_config);
  505. }
  506. }
  507. if (wriop_get_enet_if(WRIOP1_DPMAC17) == PHY_INTERFACE_MODE_RGMII_ID) {
  508. wriop_set_phy_address(WRIOP1_DPMAC17, 0, RGMII_PHY_ADDR1);
  509. bus = lx2162a_qds_mdio_init(EMI1, EMI1_RGMII1);
  510. if (!bus)
  511. printf("could not get bus for RGMII1\n");
  512. else
  513. wriop_set_mdio(WRIOP1_DPMAC17, bus);
  514. }
  515. if (wriop_get_enet_if(WRIOP1_DPMAC18) == PHY_INTERFACE_MODE_RGMII_ID) {
  516. wriop_set_phy_address(WRIOP1_DPMAC18, 0, RGMII_PHY_ADDR2);
  517. bus = lx2162a_qds_mdio_init(EMI1, EMI1_RGMII2);
  518. if (!bus)
  519. printf("could not get bus for RGMII2\n");
  520. else
  521. wriop_set_mdio(WRIOP1_DPMAC18, bus);
  522. }
  523. cpu_eth_init(bis);
  524. #endif /* CONFIG_FMAN_ENET */
  525. #endif /* !CONFIG_DM_ETH */
  526. #ifdef CONFIG_PHY_AQUANTIA
  527. /*
  528. * Export functions to be used by AQ firmware
  529. * upload application
  530. */
  531. gd->jt->strcpy = strcpy;
  532. gd->jt->mdelay = mdelay;
  533. gd->jt->mdio_get_current_dev = mdio_get_current_dev;
  534. gd->jt->phy_find_by_mask = phy_find_by_mask;
  535. gd->jt->mdio_phydev_for_ethname = mdio_phydev_for_ethname;
  536. gd->jt->miiphy_set_current_dev = miiphy_set_current_dev;
  537. #endif
  538. #ifdef CONFIG_DM_ETH
  539. return 0;
  540. #else
  541. return pci_eth_init(bis);
  542. #endif
  543. }
  544. #if defined(CONFIG_RESET_PHY_R)
  545. void reset_phy(void)
  546. {
  547. #if defined(CONFIG_FSL_MC_ENET)
  548. mc_env_boot();
  549. #endif
  550. }
  551. #endif /* CONFIG_RESET_PHY_R */
  552. #ifndef CONFIG_DM_ETH
  553. #if defined(CONFIG_FSL_MC_ENET)
  554. int fdt_fixup_dpmac_phy_handle(void *fdt, int dpmac_id, int node_phandle)
  555. {
  556. int offset;
  557. int ret;
  558. char dpmac_str[] = "dpmacs@00";
  559. const char *phy_string;
  560. offset = fdt_path_offset(fdt, "/soc/fsl-mc/dpmacs");
  561. if (offset < 0)
  562. offset = fdt_path_offset(fdt, "/fsl-mc/dpmacs");
  563. if (offset < 0) {
  564. printf("dpmacs node not found in device tree\n");
  565. return offset;
  566. }
  567. sprintf(dpmac_str, "dpmac@%x", dpmac_id);
  568. debug("dpmac_str = %s\n", dpmac_str);
  569. offset = fdt_subnode_offset(fdt, offset, dpmac_str);
  570. if (offset < 0) {
  571. printf("%s node not found in device tree\n", dpmac_str);
  572. return offset;
  573. }
  574. phy_string = fdt_getprop(fdt, offset, "phy-connection-type", NULL);
  575. if (is_backplane_mode(phy_string)) {
  576. /* Backplane KR mode: skip fixups */
  577. printf("Interface %d in backplane KR mode\n", dpmac_id);
  578. return 0;
  579. }
  580. ret = fdt_appendprop_cell(fdt, offset, "phy-handle", node_phandle);
  581. if (ret)
  582. printf("%d@%s %d\n", __LINE__, __func__, ret);
  583. phy_string = phy_string_for_interface(wriop_get_enet_if(dpmac_id));
  584. ret = fdt_setprop_string(fdt, offset, "phy-connection-type",
  585. phy_string);
  586. if (ret)
  587. printf("%d@%s %d\n", __LINE__, __func__, ret);
  588. return ret;
  589. }
  590. int fdt_get_ioslot_offset(void *fdt, struct mii_dev *mii_dev, int fpga_offset)
  591. {
  592. char mdio_ioslot_str[] = "mdio@00";
  593. struct lx2162a_qds_mdio *priv;
  594. u64 reg;
  595. u32 phandle;
  596. int offset, mux_val;
  597. /*Test if the MDIO bus is real mdio bus or muxing front end ?*/
  598. if (strncmp(mii_dev->name, "LX2162A_QDS_MDIO",
  599. strlen("LX2162A_QDS_MDIO")))
  600. return -1;
  601. /*Get the real MDIO bus num and ioslot info from bus's priv data*/
  602. priv = mii_dev->priv;
  603. debug("real_bus_num = %d, ioslot = %d\n",
  604. priv->realbusnum, priv->ioslot);
  605. if (priv->realbusnum == EMI1)
  606. reg = CONFIG_SYS_FSL_WRIOP1_MDIO1;
  607. else
  608. reg = CONFIG_SYS_FSL_WRIOP1_MDIO2;
  609. offset = fdt_node_offset_by_compat_reg(fdt, "fsl,fman-memac-mdio", reg);
  610. if (offset < 0) {
  611. printf("mdio@%llx node not found in device tree\n", reg);
  612. return offset;
  613. }
  614. phandle = fdt_get_phandle(fdt, offset);
  615. phandle = cpu_to_fdt32(phandle);
  616. offset = fdt_node_offset_by_prop_value(fdt, -1, "mdio-parent-bus",
  617. &phandle, 4);
  618. if (offset < 0) {
  619. printf("mdio-mux-%d node not found in device tree\n",
  620. priv->realbusnum == EMI1 ? 1 : 2);
  621. return offset;
  622. }
  623. mux_val = lx2162a_qds_get_mdio_mux_val(priv->realbusnum, priv->ioslot);
  624. if (priv->realbusnum == EMI1)
  625. mux_val >>= BRDCFG4_EMI1SEL_SHIFT;
  626. else
  627. mux_val >>= BRDCFG4_EMI2SEL_SHIFT;
  628. sprintf(mdio_ioslot_str, "mdio@%x", (u8)mux_val);
  629. offset = fdt_subnode_offset(fdt, offset, mdio_ioslot_str);
  630. if (offset < 0) {
  631. printf("%s node not found in device tree\n", mdio_ioslot_str);
  632. return offset;
  633. }
  634. return offset;
  635. }
  636. int fdt_create_phy_node(void *fdt, int offset, u8 phyaddr, int *subnodeoffset,
  637. struct phy_device *phy_dev, int phandle)
  638. {
  639. char phy_node_name[] = "ethernet-phy@00";
  640. char phy_id_compatible_str[] = "ethernet-phy-id0000.0000,";
  641. int ret;
  642. sprintf(phy_node_name, "ethernet-phy@%x", phyaddr);
  643. debug("phy_node_name = %s\n", phy_node_name);
  644. *subnodeoffset = fdt_add_subnode(fdt, offset, phy_node_name);
  645. if (*subnodeoffset <= 0) {
  646. printf("Could not add subnode %s inside node %s err = %s\n",
  647. phy_node_name, fdt_get_name(fdt, offset, NULL),
  648. fdt_strerror(*subnodeoffset));
  649. return *subnodeoffset;
  650. }
  651. sprintf(phy_id_compatible_str, "ethernet-phy-id%04x.%04x,",
  652. phy_dev->phy_id >> 16, phy_dev->phy_id & 0xFFFF);
  653. debug("phy_id_compatible_str %s\n", phy_id_compatible_str);
  654. ret = fdt_setprop_string(fdt, *subnodeoffset, "compatible",
  655. phy_id_compatible_str);
  656. if (ret) {
  657. printf("%d@%s %d\n", __LINE__, __func__, ret);
  658. goto out;
  659. }
  660. if (phy_dev->is_c45) {
  661. ret = fdt_appendprop_string(fdt, *subnodeoffset, "compatible",
  662. "ethernet-phy-ieee802.3-c45");
  663. if (ret) {
  664. printf("%d@%s %d\n", __LINE__, __func__, ret);
  665. goto out;
  666. }
  667. } else {
  668. ret = fdt_appendprop_string(fdt, *subnodeoffset, "compatible",
  669. "ethernet-phy-ieee802.3-c22");
  670. if (ret) {
  671. printf("%d@%s %d\n", __LINE__, __func__, ret);
  672. goto out;
  673. }
  674. }
  675. ret = fdt_setprop_cell(fdt, *subnodeoffset, "reg", phyaddr);
  676. if (ret) {
  677. printf("%d@%s %d\n", __LINE__, __func__, ret);
  678. goto out;
  679. }
  680. ret = fdt_set_phandle(fdt, *subnodeoffset, phandle);
  681. if (ret) {
  682. printf("%d@%s %d\n", __LINE__, __func__, ret);
  683. goto out;
  684. }
  685. out:
  686. if (ret)
  687. fdt_del_node(fdt, *subnodeoffset);
  688. return ret;
  689. }
  690. #define is_rgmii(dpmac_id) \
  691. wriop_get_enet_if((dpmac_id)) == PHY_INTERFACE_MODE_RGMII_ID
  692. int fdt_fixup_board_phy(void *fdt)
  693. {
  694. int fpga_offset, offset, subnodeoffset;
  695. struct mii_dev *mii_dev;
  696. struct list_head *mii_devs, *entry;
  697. int ret, dpmac_id, phandle, i;
  698. struct phy_device *phy_dev;
  699. char ethname[ETH_NAME_LEN];
  700. phy_interface_t phy_iface;
  701. ret = 0;
  702. /* we know FPGA is connected to i2c0, therefore search path directly,
  703. * instead of compatible property, as it saves time
  704. */
  705. fpga_offset = fdt_path_offset(fdt, "/soc/i2c@2000000/fpga");
  706. if (fpga_offset < 0)
  707. fpga_offset = fdt_path_offset(fdt, "/i2c@2000000/fpga");
  708. if (fpga_offset < 0) {
  709. printf("i2c@2000000/fpga node not found in device tree\n");
  710. return fpga_offset;
  711. }
  712. phandle = fdt_alloc_phandle(fdt);
  713. mii_devs = mdio_get_list_head();
  714. list_for_each(entry, mii_devs) {
  715. mii_dev = list_entry(entry, struct mii_dev, link);
  716. debug("mii_dev name : %s\n", mii_dev->name);
  717. offset = fdt_get_ioslot_offset(fdt, mii_dev, fpga_offset);
  718. if (offset < 0)
  719. continue;
  720. // Look for phy devices attached to MDIO bus muxing front end
  721. // and create their entries with compatible being the device id
  722. for (i = 0; i < PHY_MAX_ADDR; i++) {
  723. phy_dev = mii_dev->phymap[i];
  724. if (!phy_dev)
  725. continue;
  726. // TODO: use sscanf instead of loop
  727. dpmac_id = WRIOP1_DPMAC1;
  728. while (dpmac_id < NUM_WRIOP_PORTS) {
  729. phy_iface = wriop_get_enet_if(dpmac_id);
  730. snprintf(ethname, ETH_NAME_LEN, "DPMAC%d@%s",
  731. dpmac_id,
  732. phy_string_for_interface(phy_iface));
  733. if (strcmp(ethname, phy_dev->dev->name) == 0)
  734. break;
  735. dpmac_id++;
  736. }
  737. if (dpmac_id == NUM_WRIOP_PORTS)
  738. continue;
  739. if ((dpmac_id == 17 || dpmac_id == 18) &&
  740. is_rgmii(dpmac_id))
  741. continue;
  742. ret = fdt_create_phy_node(fdt, offset, i,
  743. &subnodeoffset,
  744. phy_dev, phandle);
  745. if (ret)
  746. break;
  747. ret = fdt_fixup_dpmac_phy_handle(fdt,
  748. dpmac_id, phandle);
  749. if (ret) {
  750. fdt_del_node(fdt, subnodeoffset);
  751. break;
  752. }
  753. /* calculate offset again as new node addition may have
  754. * changed offset;
  755. */
  756. offset = fdt_get_ioslot_offset(fdt, mii_dev,
  757. fpga_offset);
  758. phandle++;
  759. }
  760. if (ret)
  761. break;
  762. }
  763. return ret;
  764. }
  765. #endif // CONFIG_FSL_MC_ENET
  766. #endif
  767. #if defined(CONFIG_DM_ETH) && defined(CONFIG_MULTI_DTB_FIT)
  768. /* Structure to hold SERDES protocols supported in case of
  769. * CONFIG_DM_ETH enabled (network interfaces are described in the DTS).
  770. *
  771. * @serdes_block: the index of the SERDES block
  772. * @serdes_protocol: the decimal value of the protocol supported
  773. * @dts_needed: DTS notes describing the current configuration are needed
  774. *
  775. * When dts_needed is true, the board_fit_config_name_match() function
  776. * will try to exactly match the current configuration of the block with a DTS
  777. * name provided.
  778. */
  779. static struct serdes_configuration {
  780. u8 serdes_block;
  781. u32 serdes_protocol;
  782. bool dts_needed;
  783. } supported_protocols[] = {
  784. /* Serdes block #1 */
  785. {1, 2, true},
  786. {1, 3, true},
  787. {1, 15, true},
  788. {1, 17, true},
  789. {1, 18, true},
  790. {1, 20, true},
  791. /* Serdes block #2 */
  792. {2, 2, false},
  793. {2, 3, false},
  794. {2, 5, false},
  795. {2, 10, false},
  796. {2, 11, true},
  797. {2, 12, true},
  798. };
  799. #define SUPPORTED_SERDES_PROTOCOLS ARRAY_SIZE(supported_protocols)
  800. static bool protocol_supported(u8 serdes_block, u32 protocol)
  801. {
  802. struct serdes_configuration serdes_conf;
  803. int i;
  804. for (i = 0; i < SUPPORTED_SERDES_PROTOCOLS; i++) {
  805. serdes_conf = supported_protocols[i];
  806. if (serdes_conf.serdes_block == serdes_block &&
  807. serdes_conf.serdes_protocol == protocol)
  808. return true;
  809. }
  810. return false;
  811. }
  812. static void get_str_protocol(u8 serdes_block, u32 protocol, char *str)
  813. {
  814. struct serdes_configuration serdes_conf;
  815. int i;
  816. for (i = 0; i < SUPPORTED_SERDES_PROTOCOLS; i++) {
  817. serdes_conf = supported_protocols[i];
  818. if (serdes_conf.serdes_block == serdes_block &&
  819. serdes_conf.serdes_protocol == protocol) {
  820. if (serdes_conf.dts_needed == true)
  821. sprintf(str, "%u", protocol);
  822. else
  823. sprintf(str, "x");
  824. return;
  825. }
  826. }
  827. }
  828. int board_fit_config_name_match(const char *name)
  829. {
  830. struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
  831. u32 rcw_status = in_le32(&gur->rcwsr[28]);
  832. char srds_s1_str[2], srds_s2_str[2];
  833. u32 srds_s1, srds_s2;
  834. char expected_dts[100];
  835. srds_s1 = rcw_status & FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK;
  836. srds_s1 >>= FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
  837. srds_s2 = rcw_status & FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK;
  838. srds_s2 >>= FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT;
  839. /* Check for supported protocols. The default DTS will be used
  840. * in this case
  841. */
  842. if (!protocol_supported(1, srds_s1) ||
  843. !protocol_supported(2, srds_s2))
  844. return -1;
  845. get_str_protocol(1, srds_s1, srds_s1_str);
  846. get_str_protocol(2, srds_s2, srds_s2_str);
  847. sprintf(expected_dts, "fsl-lx2160a-qds-%s-%s",
  848. srds_s1_str, srds_s2_str);
  849. if (!strcmp(name, expected_dts))
  850. return 0;
  851. return -1;
  852. }
  853. #endif