meesc.c 6.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2007-2008
  4. * Stelian Pop <stelian@popies.net>
  5. * Lead Tech Design <www.leadtechdesign.com>
  6. *
  7. * (C) Copyright 2009-2015
  8. * Daniel Gorsulowski <daniel.gorsulowski@esd.eu>
  9. * esd electronic system design gmbh <www.esd.eu>
  10. */
  11. #include <common.h>
  12. #include <env.h>
  13. #include <init.h>
  14. #include <net.h>
  15. #include <serial.h>
  16. #include <vsprintf.h>
  17. #include <asm/global_data.h>
  18. #include <asm/io.h>
  19. #include <asm/gpio.h>
  20. #include <asm/mach-types.h>
  21. #include <asm/setup.h>
  22. #include <asm/arch/at91sam9_smc.h>
  23. #include <asm/arch/at91_common.h>
  24. #include <asm/arch/at91_pmc.h>
  25. #include <asm/arch/at91_rstc.h>
  26. #include <asm/arch/at91_matrix.h>
  27. #include <asm/arch/at91_pio.h>
  28. #include <asm/arch/clk.h>
  29. #include <netdev.h>
  30. DECLARE_GLOBAL_DATA_PTR;
  31. /*
  32. * Miscelaneous platform dependent initialisations
  33. */
  34. #ifdef CONFIG_REVISION_TAG
  35. static int hw_rev = -1; /* hardware revision */
  36. int get_hw_rev(void)
  37. {
  38. if (hw_rev >= 0)
  39. return hw_rev;
  40. hw_rev = at91_get_pio_value(AT91_PIO_PORTB, 19);
  41. hw_rev |= at91_get_pio_value(AT91_PIO_PORTB, 20) << 1;
  42. hw_rev |= at91_get_pio_value(AT91_PIO_PORTB, 21) << 2;
  43. hw_rev |= at91_get_pio_value(AT91_PIO_PORTB, 22) << 3;
  44. if (hw_rev == 15)
  45. hw_rev = 0;
  46. return hw_rev;
  47. }
  48. #endif /* CONFIG_REVISION_TAG */
  49. #ifdef CONFIG_CMD_NAND
  50. static void meesc_nand_hw_init(void)
  51. {
  52. unsigned long csa;
  53. at91_smc_t *smc = (at91_smc_t *) ATMEL_BASE_SMC0;
  54. at91_matrix_t *matrix = (at91_matrix_t *) ATMEL_BASE_MATRIX;
  55. /* Enable CS3 */
  56. csa = readl(&matrix->csa[0]) | AT91_MATRIX_CSA_EBI_CS3A;
  57. writel(csa, &matrix->csa[0]);
  58. /* Configure SMC CS3 for NAND/SmartMedia */
  59. writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(1) |
  60. AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(2),
  61. &smc->cs[3].setup);
  62. writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
  63. AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
  64. &smc->cs[3].pulse);
  65. writel(AT91_SMC_CYCLE_NWE(6) | AT91_SMC_CYCLE_NRD(6),
  66. &smc->cs[3].cycle);
  67. writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
  68. AT91_SMC_MODE_EXNW_DISABLE |
  69. AT91_SMC_MODE_DBW_8 |
  70. AT91_SMC_MODE_TDF_CYCLE(12),
  71. &smc->cs[3].mode);
  72. /* Configure RDY/BSY */
  73. gpio_direction_input(CONFIG_SYS_NAND_READY_PIN);
  74. /* Enable NandFlash */
  75. gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
  76. }
  77. #endif /* CONFIG_CMD_NAND */
  78. #ifdef CONFIG_MACB
  79. static void meesc_macb_hw_init(void)
  80. {
  81. at91_periph_clk_enable(ATMEL_ID_EMAC);
  82. at91_macb_hw_init();
  83. }
  84. #endif
  85. /*
  86. * Static memory controller initialization to enable Beckhoff ET1100 EtherCAT
  87. * controller debugging
  88. * The ET1100 is located at physical address 0x70000000
  89. * Its process memory is located at physical address 0x70001000
  90. */
  91. static void meesc_ethercat_hw_init(void)
  92. {
  93. at91_smc_t *smc1 = (at91_smc_t *) ATMEL_BASE_SMC1;
  94. /* Configure SMC EBI1_CS0 for EtherCAT */
  95. writel(AT91_SMC_SETUP_NWE(0) | AT91_SMC_SETUP_NCS_WR(0) |
  96. AT91_SMC_SETUP_NRD(0) | AT91_SMC_SETUP_NCS_RD(0),
  97. &smc1->cs[0].setup);
  98. writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(9) |
  99. AT91_SMC_PULSE_NRD(5) | AT91_SMC_PULSE_NCS_RD(9),
  100. &smc1->cs[0].pulse);
  101. writel(AT91_SMC_CYCLE_NWE(10) | AT91_SMC_CYCLE_NRD(6),
  102. &smc1->cs[0].cycle);
  103. /*
  104. * Configure behavior at external wait signal, byte-select mode, 16 bit
  105. * data bus width, none data float wait states and TDF optimization
  106. */
  107. writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_EXNW_READY |
  108. AT91_SMC_MODE_DBW_16 | AT91_SMC_MODE_TDF_CYCLE(0) |
  109. AT91_SMC_MODE_TDF, &smc1->cs[0].mode);
  110. /* Configure RDY/BSY */
  111. at91_set_b_periph(AT91_PIO_PORTE, 20, 0); /* EBI1_NWAIT */
  112. }
  113. int dram_init(void)
  114. {
  115. /* dram_init must store complete ramsize in gd->ram_size */
  116. gd->ram_size = get_ram_size((void *)PHYS_SDRAM,
  117. PHYS_SDRAM_SIZE);
  118. return 0;
  119. }
  120. int dram_init_banksize(void)
  121. {
  122. gd->bd->bi_dram[0].start = PHYS_SDRAM;
  123. gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
  124. return 0;
  125. }
  126. int board_eth_init(struct bd_info *bis)
  127. {
  128. int rc = 0;
  129. #ifdef CONFIG_MACB
  130. rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x00);
  131. #endif
  132. return rc;
  133. }
  134. #ifdef CONFIG_DISPLAY_BOARDINFO
  135. int checkboard(void)
  136. {
  137. char str[32];
  138. u_char hw_type; /* hardware type */
  139. /* read the "Type" register of the ET1100 controller */
  140. hw_type = readb(CONFIG_ET1100_BASE);
  141. switch (hw_type) {
  142. case 0x11:
  143. case 0x3F:
  144. /* ET1100 present, arch number of MEESC-Board */
  145. gd->bd->bi_arch_number = MACH_TYPE_MEESC;
  146. puts("Board: CAN-EtherCAT Gateway");
  147. break;
  148. case 0xFF:
  149. /* no ET1100 present, arch number of EtherCAN/2-Board */
  150. gd->bd->bi_arch_number = MACH_TYPE_ETHERCAN2;
  151. puts("Board: EtherCAN/2 Gateway");
  152. /* switch on LED1D */
  153. at91_set_pio_output(AT91_PIO_PORTB, 12, 1);
  154. break;
  155. default:
  156. /* assume, no ET1100 present, arch number of EtherCAN/2-Board */
  157. gd->bd->bi_arch_number = MACH_TYPE_ETHERCAN2;
  158. printf("ERROR! Read invalid hw_type: %02X\n", hw_type);
  159. puts("Board: EtherCAN/2 Gateway");
  160. break;
  161. }
  162. if (env_get_f("serial#", str, sizeof(str)) > 0) {
  163. puts(", serial# ");
  164. puts(str);
  165. }
  166. #ifdef CONFIG_REVISION_TAG
  167. printf("\nHardware-revision: 1.%d\n", get_hw_rev());
  168. #endif
  169. printf("Mach-type: %lu\n", gd->bd->bi_arch_number);
  170. return 0;
  171. }
  172. #endif /* CONFIG_DISPLAY_BOARDINFO */
  173. #ifdef CONFIG_SERIAL_TAG
  174. void get_board_serial(struct tag_serialnr *serialnr)
  175. {
  176. char *str;
  177. char *serial = env_get("serial#");
  178. if (serial) {
  179. str = strchr(serial, '_');
  180. if (str && (strlen(str) >= 4)) {
  181. serialnr->high = (*(str + 1) << 8) | *(str + 2);
  182. serialnr->low = hextoul(str + 3, NULL);
  183. }
  184. } else {
  185. serialnr->high = 0;
  186. serialnr->low = 0;
  187. }
  188. }
  189. #endif
  190. #ifdef CONFIG_REVISION_TAG
  191. u32 get_board_rev(void)
  192. {
  193. return hw_rev | 0x100;
  194. }
  195. #endif
  196. #ifdef CONFIG_MISC_INIT_R
  197. int misc_init_r(void)
  198. {
  199. char *str;
  200. char buf[32];
  201. at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
  202. /*
  203. * Normally the processor clock has a divisor of 2.
  204. * In some cases this this needs to be set to 4.
  205. * Check the user has set environment mdiv to 4 to change the divisor.
  206. */
  207. str = env_get("mdiv");
  208. if (str && (strcmp(str, "4") == 0)) {
  209. writel((readl(&pmc->mckr) & ~AT91_PMC_MDIV) |
  210. AT91SAM9_PMC_MDIV_4, &pmc->mckr);
  211. at91_clock_init(CONFIG_SYS_AT91_MAIN_CLOCK);
  212. serial_setbrg();
  213. /* Notify the user that the clock is not default */
  214. printf("Setting master clock to %s MHz\n",
  215. strmhz(buf, get_mck_clk_rate()));
  216. }
  217. return 0;
  218. }
  219. #endif /* CONFIG_MISC_INIT_R */
  220. int board_early_init_f(void)
  221. {
  222. at91_periph_clk_enable(ATMEL_ID_UHP);
  223. return 0;
  224. }
  225. int board_init(void)
  226. {
  227. /* initialize ET1100 Controller */
  228. meesc_ethercat_hw_init();
  229. /* adress of boot parameters */
  230. gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
  231. #ifdef CONFIG_CMD_NAND
  232. meesc_nand_hw_init();
  233. #endif
  234. #ifdef CONFIG_MACB
  235. meesc_macb_hw_init();
  236. #endif
  237. #ifdef CONFIG_AT91_CAN
  238. at91_can_hw_init();
  239. #endif
  240. #ifdef CONFIG_USB_OHCI_NEW
  241. at91_uhp_hw_init();
  242. #endif
  243. return 0;
  244. }