mp.c 11 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2008-2011 Freescale Semiconductor, Inc.
  4. */
  5. #include <common.h>
  6. #include <cpu_func.h>
  7. #include <env.h>
  8. #include <log.h>
  9. #include <asm/global_data.h>
  10. #include <asm/processor.h>
  11. #include <env.h>
  12. #include <ioports.h>
  13. #include <lmb.h>
  14. #include <asm/io.h>
  15. #include <asm/mmu.h>
  16. #include <asm/fsl_law.h>
  17. #include <fsl_ddr_sdram.h>
  18. #include <linux/delay.h>
  19. #include "mp.h"
  20. DECLARE_GLOBAL_DATA_PTR;
  21. u32 fsl_ddr_get_intl3r(void);
  22. extern u32 __spin_table[];
  23. u32 get_my_id()
  24. {
  25. return mfspr(SPRN_PIR);
  26. }
  27. /*
  28. * Determine if U-Boot should keep secondary cores in reset, or let them out
  29. * of reset and hold them in a spinloop
  30. */
  31. int hold_cores_in_reset(int verbose)
  32. {
  33. /* Default to no, overridden by 'y', 'yes', 'Y', 'Yes', or '1' */
  34. if (env_get_yesno("mp_holdoff") == 1) {
  35. if (verbose) {
  36. puts("Secondary cores are being held in reset.\n");
  37. puts("See 'mp_holdoff' environment variable\n");
  38. }
  39. return 1;
  40. }
  41. return 0;
  42. }
  43. int cpu_reset(u32 nr)
  44. {
  45. volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR);
  46. out_be32(&pic->pir, 1 << nr);
  47. /* the dummy read works around an errata on early 85xx MP PICs */
  48. (void)in_be32(&pic->pir);
  49. out_be32(&pic->pir, 0x0);
  50. return 0;
  51. }
  52. int cpu_status(u32 nr)
  53. {
  54. u32 *table, id = get_my_id();
  55. if (hold_cores_in_reset(1))
  56. return 0;
  57. if (nr == id) {
  58. table = (u32 *)&__spin_table;
  59. printf("table base @ 0x%p\n", table);
  60. } else if (is_core_disabled(nr)) {
  61. puts("Disabled\n");
  62. } else {
  63. table = (u32 *)&__spin_table + nr * NUM_BOOT_ENTRY;
  64. printf("Running on cpu %d\n", id);
  65. printf("\n");
  66. printf("table @ 0x%p\n", table);
  67. printf(" addr - 0x%08x\n", table[BOOT_ENTRY_ADDR_LOWER]);
  68. printf(" r3 - 0x%08x\n", table[BOOT_ENTRY_R3_LOWER]);
  69. printf(" pir - 0x%08x\n", table[BOOT_ENTRY_PIR]);
  70. }
  71. return 0;
  72. }
  73. #ifdef CONFIG_FSL_CORENET
  74. int cpu_disable(u32 nr)
  75. {
  76. volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  77. setbits_be32(&gur->coredisrl, 1 << nr);
  78. return 0;
  79. }
  80. int is_core_disabled(int nr) {
  81. ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  82. u32 coredisrl = in_be32(&gur->coredisrl);
  83. return (coredisrl & (1 << nr));
  84. }
  85. #else
  86. int cpu_disable(u32 nr)
  87. {
  88. volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  89. switch (nr) {
  90. case 0:
  91. setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_CPU0);
  92. break;
  93. case 1:
  94. setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_CPU1);
  95. break;
  96. default:
  97. printf("Invalid cpu number for disable %d\n", nr);
  98. return 1;
  99. }
  100. return 0;
  101. }
  102. int is_core_disabled(int nr) {
  103. ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  104. u32 devdisr = in_be32(&gur->devdisr);
  105. switch (nr) {
  106. case 0:
  107. return (devdisr & MPC85xx_DEVDISR_CPU0);
  108. case 1:
  109. return (devdisr & MPC85xx_DEVDISR_CPU1);
  110. default:
  111. printf("Invalid cpu number for disable %d\n", nr);
  112. }
  113. return 0;
  114. }
  115. #endif
  116. static u8 boot_entry_map[4] = {
  117. 0,
  118. BOOT_ENTRY_PIR,
  119. BOOT_ENTRY_R3_LOWER,
  120. };
  121. int cpu_release(u32 nr, int argc, char *const argv[])
  122. {
  123. u32 i, val, *table = (u32 *)&__spin_table + nr * NUM_BOOT_ENTRY;
  124. u64 boot_addr;
  125. if (hold_cores_in_reset(1))
  126. return 0;
  127. if (nr == get_my_id()) {
  128. printf("Invalid to release the boot core.\n\n");
  129. return 1;
  130. }
  131. if (argc != 4) {
  132. printf("Invalid number of arguments to release.\n\n");
  133. return 1;
  134. }
  135. boot_addr = simple_strtoull(argv[0], NULL, 16);
  136. /* handle pir, r3 */
  137. for (i = 1; i < 3; i++) {
  138. if (argv[i][0] != '-') {
  139. u8 entry = boot_entry_map[i];
  140. val = hextoul(argv[i], NULL);
  141. table[entry] = val;
  142. }
  143. }
  144. table[BOOT_ENTRY_ADDR_UPPER] = (u32)(boot_addr >> 32);
  145. /* ensure all table updates complete before final address write */
  146. eieio();
  147. table[BOOT_ENTRY_ADDR_LOWER] = (u32)(boot_addr & 0xffffffff);
  148. return 0;
  149. }
  150. u32 determine_mp_bootpg(unsigned int *pagesize)
  151. {
  152. u32 bootpg;
  153. #ifdef CONFIG_SYS_FSL_ERRATUM_A004468
  154. u32 svr = get_svr();
  155. u32 granule_size, check;
  156. struct law_entry e;
  157. #endif
  158. /* use last 4K of mapped memory */
  159. bootpg = ((gd->ram_size > CONFIG_MAX_MEM_MAPPED) ?
  160. CONFIG_MAX_MEM_MAPPED : gd->ram_size) +
  161. CONFIG_SYS_SDRAM_BASE - 4096;
  162. if (pagesize)
  163. *pagesize = 4096;
  164. #ifdef CONFIG_SYS_FSL_ERRATUM_A004468
  165. /*
  166. * Erratum A004468 has two parts. The 3-way interleaving applies to T4240,
  167. * to be fixed in rev 2.0. The 2-way interleaving applies to many SoCs. But
  168. * the way boot page chosen in u-boot avoids hitting this erratum. So only
  169. * thw workaround for 3-way interleaving is needed.
  170. *
  171. * To make sure boot page translation works with 3-Way DDR interleaving
  172. * enforce a check for the following constrains
  173. * 8K granule size requires BRSIZE=8K and
  174. * bootpg >> log2(BRSIZE) %3 == 1
  175. * 4K and 1K granule size requires BRSIZE=4K and
  176. * bootpg >> log2(BRSIZE) %3 == 0
  177. */
  178. if (SVR_SOC_VER(svr) == SVR_T4240 && SVR_MAJ(svr) < 2) {
  179. e = find_law(bootpg);
  180. switch (e.trgt_id) {
  181. case LAW_TRGT_IF_DDR_INTLV_123:
  182. granule_size = fsl_ddr_get_intl3r() & 0x1f;
  183. if (granule_size == FSL_DDR_3WAY_8KB_INTERLEAVING) {
  184. if (pagesize)
  185. *pagesize = 8192;
  186. bootpg &= 0xffffe000; /* align to 8KB */
  187. check = bootpg >> 13;
  188. while ((check % 3) != 1)
  189. check--;
  190. bootpg = check << 13;
  191. debug("Boot page (8K) at 0x%08x\n", bootpg);
  192. break;
  193. } else {
  194. bootpg &= 0xfffff000; /* align to 4KB */
  195. check = bootpg >> 12;
  196. while ((check % 3) != 0)
  197. check--;
  198. bootpg = check << 12;
  199. debug("Boot page (4K) at 0x%08x\n", bootpg);
  200. }
  201. break;
  202. default:
  203. break;
  204. }
  205. }
  206. #endif /* CONFIG_SYS_FSL_ERRATUM_A004468 */
  207. return bootpg;
  208. }
  209. phys_addr_t get_spin_phys_addr(void)
  210. {
  211. return virt_to_phys(&__spin_table);
  212. }
  213. #ifdef CONFIG_FSL_CORENET
  214. static void plat_mp_up(unsigned long bootpg, unsigned int pagesize)
  215. {
  216. u32 cpu_up_mask, whoami, brsize = LAW_SIZE_4K;
  217. u32 *table = (u32 *)&__spin_table;
  218. volatile ccsr_gur_t *gur;
  219. volatile ccsr_local_t *ccm;
  220. volatile ccsr_rcpm_t *rcpm;
  221. volatile ccsr_pic_t *pic;
  222. int timeout = 10;
  223. u32 mask = cpu_mask();
  224. struct law_entry e;
  225. gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  226. ccm = (void *)(CONFIG_SYS_FSL_CORENET_CCM_ADDR);
  227. rcpm = (void *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR);
  228. pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR);
  229. whoami = in_be32(&pic->whoami);
  230. cpu_up_mask = 1 << whoami;
  231. out_be32(&ccm->bstrl, bootpg);
  232. e = find_law(bootpg);
  233. /* pagesize is only 4K or 8K */
  234. if (pagesize == 8192)
  235. brsize = LAW_SIZE_8K;
  236. out_be32(&ccm->bstrar, LAW_EN | e.trgt_id << 20 | brsize);
  237. debug("BRSIZE is 0x%x\n", brsize);
  238. /* readback to sync write */
  239. in_be32(&ccm->bstrar);
  240. /* disable time base at the platform */
  241. out_be32(&rcpm->ctbenrl, cpu_up_mask);
  242. out_be32(&gur->brrl, mask);
  243. /* wait for everyone */
  244. while (timeout) {
  245. unsigned int i, cpu, nr_cpus = cpu_numcores();
  246. for_each_cpu(i, cpu, nr_cpus, mask) {
  247. if (table[cpu * NUM_BOOT_ENTRY + BOOT_ENTRY_ADDR_LOWER])
  248. cpu_up_mask |= (1 << cpu);
  249. }
  250. if ((cpu_up_mask & mask) == mask)
  251. break;
  252. udelay(100);
  253. timeout--;
  254. }
  255. if (timeout == 0)
  256. printf("CPU up timeout. CPU up mask is %x should be %x\n",
  257. cpu_up_mask, mask);
  258. /* enable time base at the platform */
  259. out_be32(&rcpm->ctbenrl, 0);
  260. /* readback to sync write */
  261. in_be32(&rcpm->ctbenrl);
  262. mtspr(SPRN_TBWU, 0);
  263. mtspr(SPRN_TBWL, 0);
  264. out_be32(&rcpm->ctbenrl, mask);
  265. #ifdef CONFIG_MPC8xxx_DISABLE_BPTR
  266. /*
  267. * Disabling Boot Page Translation allows the memory region 0xfffff000
  268. * to 0xffffffff to be used normally. Leaving Boot Page Translation
  269. * enabled remaps 0xfffff000 to SDRAM which makes that memory region
  270. * unusable for normal operation but it does allow OSes to easily
  271. * reset a processor core to put it back into U-Boot's spinloop.
  272. */
  273. clrbits_be32(&ccm->bstrar, LAW_EN);
  274. #endif
  275. }
  276. #else
  277. static void plat_mp_up(unsigned long bootpg, unsigned int pagesize)
  278. {
  279. u32 up, cpu_up_mask, whoami;
  280. u32 *table = (u32 *)&__spin_table;
  281. volatile u32 bpcr;
  282. volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
  283. volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  284. volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR);
  285. u32 devdisr;
  286. int timeout = 10;
  287. whoami = in_be32(&pic->whoami);
  288. out_be32(&ecm->bptr, 0x80000000 | (bootpg >> 12));
  289. /* disable time base at the platform */
  290. devdisr = in_be32(&gur->devdisr);
  291. if (whoami)
  292. devdisr |= MPC85xx_DEVDISR_TB0;
  293. else
  294. devdisr |= MPC85xx_DEVDISR_TB1;
  295. out_be32(&gur->devdisr, devdisr);
  296. /* release the hounds */
  297. up = ((1 << cpu_numcores()) - 1);
  298. bpcr = in_be32(&ecm->eebpcr);
  299. bpcr |= (up << 24);
  300. out_be32(&ecm->eebpcr, bpcr);
  301. asm("sync; isync; msync");
  302. cpu_up_mask = 1 << whoami;
  303. /* wait for everyone */
  304. while (timeout) {
  305. int i;
  306. for (i = 0; i < cpu_numcores(); i++) {
  307. if (table[i * NUM_BOOT_ENTRY + BOOT_ENTRY_ADDR_LOWER])
  308. cpu_up_mask |= (1 << i);
  309. };
  310. if ((cpu_up_mask & up) == up)
  311. break;
  312. udelay(100);
  313. timeout--;
  314. }
  315. if (timeout == 0)
  316. printf("CPU up timeout. CPU up mask is %x should be %x\n",
  317. cpu_up_mask, up);
  318. /* enable time base at the platform */
  319. if (whoami)
  320. devdisr |= MPC85xx_DEVDISR_TB1;
  321. else
  322. devdisr |= MPC85xx_DEVDISR_TB0;
  323. out_be32(&gur->devdisr, devdisr);
  324. /* readback to sync write */
  325. in_be32(&gur->devdisr);
  326. mtspr(SPRN_TBWU, 0);
  327. mtspr(SPRN_TBWL, 0);
  328. devdisr &= ~(MPC85xx_DEVDISR_TB0 | MPC85xx_DEVDISR_TB1);
  329. out_be32(&gur->devdisr, devdisr);
  330. #ifdef CONFIG_MPC8xxx_DISABLE_BPTR
  331. /*
  332. * Disabling Boot Page Translation allows the memory region 0xfffff000
  333. * to 0xffffffff to be used normally. Leaving Boot Page Translation
  334. * enabled remaps 0xfffff000 to SDRAM which makes that memory region
  335. * unusable for normal operation but it does allow OSes to easily
  336. * reset a processor core to put it back into U-Boot's spinloop.
  337. */
  338. clrbits_be32(&ecm->bptr, 0x80000000);
  339. #endif
  340. }
  341. #endif
  342. void cpu_mp_lmb_reserve(struct lmb *lmb)
  343. {
  344. u32 bootpg = determine_mp_bootpg(NULL);
  345. lmb_reserve(lmb, bootpg, 4096);
  346. }
  347. void setup_mp(void)
  348. {
  349. extern u32 __secondary_start_page;
  350. extern u32 __bootpg_addr, __spin_table_addr, __second_half_boot_page;
  351. int i;
  352. ulong fixup = (u32)&__secondary_start_page;
  353. u32 bootpg, bootpg_map, pagesize;
  354. bootpg = determine_mp_bootpg(&pagesize);
  355. /*
  356. * pagesize is only 4K or 8K
  357. * we only use the last 4K of boot page
  358. * bootpg_map saves the address for the boot page
  359. * 8K is used for the workaround of 3-way DDR interleaving
  360. */
  361. bootpg_map = bootpg;
  362. if (pagesize == 8192)
  363. bootpg += 4096; /* use 2nd half */
  364. /* Some OSes expect secondary cores to be held in reset */
  365. if (hold_cores_in_reset(0))
  366. return;
  367. /*
  368. * Store the bootpg's cache-able half address for use by secondary
  369. * CPU cores to continue to boot
  370. */
  371. __bootpg_addr = (u32)virt_to_phys(&__second_half_boot_page);
  372. /* Store spin table's physical address for use by secondary cores */
  373. __spin_table_addr = (u32)get_spin_phys_addr();
  374. /* flush bootpg it before copying invalidate any staled cacheline */
  375. flush_cache(bootpg, 4096);
  376. /* look for the tlb covering the reset page, there better be one */
  377. i = find_tlb_idx((void *)CONFIG_BPTR_VIRT_ADDR, 1);
  378. /* we found a match */
  379. if (i != -1) {
  380. /* map reset page to bootpg so we can copy code there */
  381. disable_tlb(i);
  382. set_tlb(1, CONFIG_BPTR_VIRT_ADDR, bootpg, /* tlb, epn, rpn */
  383. MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */
  384. 0, i, BOOKE_PAGESZ_4K, 1); /* ts, esel, tsize, iprot */
  385. memcpy((void *)CONFIG_BPTR_VIRT_ADDR, (void *)fixup, 4096);
  386. plat_mp_up(bootpg_map, pagesize);
  387. } else {
  388. puts("WARNING: No reset page TLB. "
  389. "Skipping secondary core setup\n");
  390. }
  391. }