misc.c 5.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2012-2017 Altera Corporation <www.altera.com>
  4. */
  5. #include <common.h>
  6. #include <command.h>
  7. #include <cpu_func.h>
  8. #include <hang.h>
  9. #include <asm/cache.h>
  10. #include <init.h>
  11. #include <asm/global_data.h>
  12. #include <asm/io.h>
  13. #include <errno.h>
  14. #include <fdtdec.h>
  15. #include <linux/libfdt.h>
  16. #include <altera.h>
  17. #include <miiphy.h>
  18. #include <netdev.h>
  19. #include <watchdog.h>
  20. #include <asm/arch/misc.h>
  21. #include <asm/arch/reset_manager.h>
  22. #include <asm/arch/scan_manager.h>
  23. #include <asm/arch/system_manager.h>
  24. #include <asm/arch/nic301.h>
  25. #include <asm/arch/scu.h>
  26. #include <asm/pl310.h>
  27. DECLARE_GLOBAL_DATA_PTR;
  28. phys_addr_t socfpga_clkmgr_base __section(".data");
  29. phys_addr_t socfpga_rstmgr_base __section(".data");
  30. phys_addr_t socfpga_sysmgr_base __section(".data");
  31. #ifdef CONFIG_SYS_L2_PL310
  32. static const struct pl310_regs *const pl310 =
  33. (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
  34. #endif
  35. struct bsel bsel_str[] = {
  36. { "rsvd", "Reserved", },
  37. { "fpga", "FPGA (HPS2FPGA Bridge)", },
  38. { "nand", "NAND Flash (1.8V)", },
  39. { "nand", "NAND Flash (3.0V)", },
  40. { "sd", "SD/MMC External Transceiver (1.8V)", },
  41. { "sd", "SD/MMC Internal Transceiver (3.0V)", },
  42. { "qspi", "QSPI Flash (1.8V)", },
  43. { "qspi", "QSPI Flash (3.0V)", },
  44. };
  45. int dram_init(void)
  46. {
  47. if (fdtdec_setup_mem_size_base() != 0)
  48. return -EINVAL;
  49. return 0;
  50. }
  51. void enable_caches(void)
  52. {
  53. #if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
  54. icache_enable();
  55. #endif
  56. #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
  57. dcache_enable();
  58. #endif
  59. }
  60. #ifdef CONFIG_SYS_L2_PL310
  61. void v7_outer_cache_enable(void)
  62. {
  63. struct udevice *dev;
  64. if (uclass_get_device(UCLASS_CACHE, 0, &dev))
  65. pr_err("cache controller driver NOT found!\n");
  66. }
  67. void v7_outer_cache_disable(void)
  68. {
  69. /* Disable the L2 cache */
  70. clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
  71. }
  72. void socfpga_pl310_clear(void)
  73. {
  74. u32 mask = 0xff, ena = 0;
  75. icache_enable();
  76. /* Disable the L2 cache */
  77. clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
  78. writel(0x0, &pl310->pl310_tag_latency_ctrl);
  79. writel(0x10, &pl310->pl310_data_latency_ctrl);
  80. /* enable BRESP, instruction and data prefetch, full line of zeroes */
  81. setbits_le32(&pl310->pl310_aux_ctrl,
  82. L310_AUX_CTRL_DATA_PREFETCH_MASK |
  83. L310_AUX_CTRL_INST_PREFETCH_MASK |
  84. L310_SHARED_ATT_OVERRIDE_ENABLE);
  85. /* Enable the L2 cache */
  86. ena = readl(&pl310->pl310_ctrl);
  87. ena |= L2X0_CTRL_EN;
  88. /*
  89. * Invalidate the PL310 L2 cache. Keep the invalidation code
  90. * entirely in L1 I-cache to avoid any bus traffic through
  91. * the L2.
  92. */
  93. asm volatile(
  94. ".align 5 \n"
  95. " b 3f \n"
  96. "1: str %1, [%4] \n"
  97. " dsb \n"
  98. " isb \n"
  99. " str %0, [%2] \n"
  100. " dsb \n"
  101. " isb \n"
  102. "2: ldr %0, [%2] \n"
  103. " cmp %0, #0 \n"
  104. " bne 2b \n"
  105. " str %0, [%3] \n"
  106. " dsb \n"
  107. " isb \n"
  108. " b 4f \n"
  109. "3: b 1b \n"
  110. "4: nop \n"
  111. : "+r"(mask), "+r"(ena)
  112. : "r"(&pl310->pl310_inv_way),
  113. "r"(&pl310->pl310_cache_sync), "r"(&pl310->pl310_ctrl)
  114. : "memory", "cc");
  115. /* Disable the L2 cache */
  116. clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
  117. }
  118. #endif
  119. #if defined(CONFIG_SYS_CONSOLE_IS_IN_ENV) && \
  120. defined(CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE)
  121. int overwrite_console(void)
  122. {
  123. return 0;
  124. }
  125. #endif
  126. #ifdef CONFIG_FPGA
  127. /* add device descriptor to FPGA device table */
  128. void socfpga_fpga_add(void *fpga_desc)
  129. {
  130. fpga_init();
  131. fpga_add(fpga_altera, fpga_desc);
  132. }
  133. #endif
  134. int arch_cpu_init(void)
  135. {
  136. socfpga_get_managers_addr();
  137. #ifdef CONFIG_HW_WATCHDOG
  138. /*
  139. * In case the watchdog is enabled, make sure to (re-)configure it
  140. * so that the defined timeout is valid. Otherwise the SPL (Perloader)
  141. * timeout value is still active which might too short for Linux
  142. * booting.
  143. */
  144. hw_watchdog_init();
  145. #else
  146. /*
  147. * If the HW watchdog is NOT enabled, make sure it is not running,
  148. * for example because it was enabled in the preloader. This might
  149. * trigger a watchdog-triggered reboot of Linux kernel later.
  150. * Toggle watchdog reset, so watchdog in not running state.
  151. */
  152. socfpga_per_reset(SOCFPGA_RESET(L4WD0), 1);
  153. socfpga_per_reset(SOCFPGA_RESET(L4WD0), 0);
  154. #endif
  155. return 0;
  156. }
  157. #ifndef CONFIG_SPL_BUILD
  158. static int do_bridge(struct cmd_tbl *cmdtp, int flag, int argc,
  159. char *const argv[])
  160. {
  161. unsigned int mask = ~0;
  162. if (argc < 2 || argc > 3)
  163. return CMD_RET_USAGE;
  164. argv++;
  165. if (argc == 3)
  166. mask = hextoul(argv[1], NULL);
  167. switch (*argv[0]) {
  168. case 'e': /* Enable */
  169. do_bridge_reset(1, mask);
  170. break;
  171. case 'd': /* Disable */
  172. do_bridge_reset(0, mask);
  173. break;
  174. default:
  175. return CMD_RET_USAGE;
  176. }
  177. return 0;
  178. }
  179. U_BOOT_CMD(bridge, 3, 1, do_bridge,
  180. "SoCFPGA HPS FPGA bridge control",
  181. "enable [mask] - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n"
  182. "bridge disable [mask] - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n"
  183. ""
  184. );
  185. #endif
  186. static int socfpga_get_base_addr(const char *compat, phys_addr_t *base)
  187. {
  188. const void *blob = gd->fdt_blob;
  189. struct fdt_resource r;
  190. int node;
  191. int ret;
  192. node = fdt_node_offset_by_compatible(blob, -1, compat);
  193. if (node < 0)
  194. return node;
  195. if (!fdtdec_get_is_enabled(blob, node))
  196. return -ENODEV;
  197. ret = fdt_get_resource(blob, node, "reg", 0, &r);
  198. if (ret)
  199. return ret;
  200. *base = (phys_addr_t)r.start;
  201. return 0;
  202. }
  203. void socfpga_get_managers_addr(void)
  204. {
  205. int ret;
  206. ret = socfpga_get_base_addr("altr,rst-mgr", &socfpga_rstmgr_base);
  207. if (ret)
  208. hang();
  209. ret = socfpga_get_base_addr("altr,sys-mgr", &socfpga_sysmgr_base);
  210. if (ret)
  211. hang();
  212. #ifdef CONFIG_TARGET_SOCFPGA_AGILEX
  213. ret = socfpga_get_base_addr("intel,agilex-clkmgr",
  214. &socfpga_clkmgr_base);
  215. #else
  216. ret = socfpga_get_base_addr("altr,clk-mgr", &socfpga_clkmgr_base);
  217. #endif
  218. if (ret)
  219. hang();
  220. }
  221. phys_addr_t socfpga_get_rstmgr_addr(void)
  222. {
  223. return socfpga_rstmgr_base;
  224. }
  225. phys_addr_t socfpga_get_sysmgr_addr(void)
  226. {
  227. return socfpga_sysmgr_base;
  228. }
  229. phys_addr_t socfpga_get_clkmgr_addr(void)
  230. {
  231. return socfpga_clkmgr_base;
  232. }