mp.c 1.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2014
  4. * Gabriel Huau <contact@huau-gabriel.fr>
  5. *
  6. * (C) Copyright 2009 Freescale Semiconductor, Inc.
  7. */
  8. #include <common.h>
  9. #include <cpu_func.h>
  10. #include <asm/io.h>
  11. #include <linux/errno.h>
  12. #include <asm/arch/sys_proto.h>
  13. #include <asm/arch/imx-regs.h>
  14. #define MAX_CPUS 4
  15. static struct src *src = (struct src *)SRC_BASE_ADDR;
  16. static uint32_t cpu_reset_mask[MAX_CPUS] = {
  17. 0, /* We don't really want to modify the cpu0 */
  18. SRC_SCR_CORE_1_RESET_MASK,
  19. SRC_SCR_CORE_2_RESET_MASK,
  20. SRC_SCR_CORE_3_RESET_MASK
  21. };
  22. static uint32_t cpu_ctrl_mask[MAX_CPUS] = {
  23. 0, /* We don't really want to modify the cpu0 */
  24. SRC_SCR_CORE_1_ENABLE_MASK,
  25. SRC_SCR_CORE_2_ENABLE_MASK,
  26. SRC_SCR_CORE_3_ENABLE_MASK
  27. };
  28. int cpu_reset(u32 nr)
  29. {
  30. /* Software reset of the CPU N */
  31. src->scr |= cpu_reset_mask[nr];
  32. return 0;
  33. }
  34. int cpu_status(u32 nr)
  35. {
  36. printf("core %d => %d\n", nr, !!(src->scr & cpu_ctrl_mask[nr]));
  37. return 0;
  38. }
  39. int cpu_release(u32 nr, int argc, char *const argv[])
  40. {
  41. uint32_t boot_addr;
  42. boot_addr = hextoul(argv[0], NULL);
  43. switch (nr) {
  44. case 1:
  45. src->gpr3 = boot_addr;
  46. break;
  47. case 2:
  48. src->gpr5 = boot_addr;
  49. break;
  50. case 3:
  51. src->gpr7 = boot_addr;
  52. break;
  53. default:
  54. return 1;
  55. }
  56. /* CPU N is ready to start */
  57. src->scr |= cpu_ctrl_mask[nr];
  58. return 0;
  59. }
  60. int is_core_valid(unsigned int core)
  61. {
  62. uint32_t nr_cores = get_nr_cpus();
  63. if (core > nr_cores)
  64. return 0;
  65. return 1;
  66. }
  67. int cpu_disable(u32 nr)
  68. {
  69. /* Disable the CPU N */
  70. src->scr &= ~cpu_ctrl_mask[nr];
  71. return 0;
  72. }