pci-uclass.c 43 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (c) 2014 Google, Inc
  4. * Written by Simon Glass <sjg@chromium.org>
  5. */
  6. #define LOG_CATEGORY UCLASS_PCI
  7. #include <common.h>
  8. #include <dm.h>
  9. #include <errno.h>
  10. #include <init.h>
  11. #include <log.h>
  12. #include <malloc.h>
  13. #include <pci.h>
  14. #include <asm/global_data.h>
  15. #include <asm/io.h>
  16. #include <dm/device-internal.h>
  17. #include <dm/lists.h>
  18. #include <dm/uclass-internal.h>
  19. #if defined(CONFIG_X86) && defined(CONFIG_HAVE_FSP)
  20. #include <asm/fsp/fsp_support.h>
  21. #endif
  22. #include <linux/delay.h>
  23. #include "pci_internal.h"
  24. DECLARE_GLOBAL_DATA_PTR;
  25. int pci_get_bus(int busnum, struct udevice **busp)
  26. {
  27. int ret;
  28. ret = uclass_get_device_by_seq(UCLASS_PCI, busnum, busp);
  29. /* Since buses may not be numbered yet try a little harder with bus 0 */
  30. if (ret == -ENODEV) {
  31. ret = uclass_first_device_err(UCLASS_PCI, busp);
  32. if (ret)
  33. return ret;
  34. ret = uclass_get_device_by_seq(UCLASS_PCI, busnum, busp);
  35. }
  36. return ret;
  37. }
  38. struct udevice *pci_get_controller(struct udevice *dev)
  39. {
  40. while (device_is_on_pci_bus(dev))
  41. dev = dev->parent;
  42. return dev;
  43. }
  44. pci_dev_t dm_pci_get_bdf(const struct udevice *dev)
  45. {
  46. struct pci_child_plat *pplat = dev_get_parent_plat(dev);
  47. struct udevice *bus = dev->parent;
  48. /*
  49. * This error indicates that @dev is a device on an unprobed PCI bus.
  50. * The bus likely has bus=seq == -1, so the PCI_ADD_BUS() macro below
  51. * will produce a bad BDF>
  52. *
  53. * A common cause of this problem is that this function is called in the
  54. * of_to_plat() method of @dev. Accessing the PCI bus in that
  55. * method is not allowed, since it has not yet been probed. To fix this,
  56. * move that access to the probe() method of @dev instead.
  57. */
  58. if (!device_active(bus))
  59. log_err("PCI: Device '%s' on unprobed bus '%s'\n", dev->name,
  60. bus->name);
  61. return PCI_ADD_BUS(dev_seq(bus), pplat->devfn);
  62. }
  63. /**
  64. * pci_get_bus_max() - returns the bus number of the last active bus
  65. *
  66. * @return last bus number, or -1 if no active buses
  67. */
  68. static int pci_get_bus_max(void)
  69. {
  70. struct udevice *bus;
  71. struct uclass *uc;
  72. int ret = -1;
  73. ret = uclass_get(UCLASS_PCI, &uc);
  74. uclass_foreach_dev(bus, uc) {
  75. if (dev_seq(bus) > ret)
  76. ret = dev_seq(bus);
  77. }
  78. debug("%s: ret=%d\n", __func__, ret);
  79. return ret;
  80. }
  81. int pci_last_busno(void)
  82. {
  83. return pci_get_bus_max();
  84. }
  85. int pci_get_ff(enum pci_size_t size)
  86. {
  87. switch (size) {
  88. case PCI_SIZE_8:
  89. return 0xff;
  90. case PCI_SIZE_16:
  91. return 0xffff;
  92. default:
  93. return 0xffffffff;
  94. }
  95. }
  96. static void pci_dev_find_ofnode(struct udevice *bus, phys_addr_t bdf,
  97. ofnode *rnode)
  98. {
  99. struct fdt_pci_addr addr;
  100. ofnode node;
  101. int ret;
  102. dev_for_each_subnode(node, bus) {
  103. ret = ofnode_read_pci_addr(node, FDT_PCI_SPACE_CONFIG, "reg",
  104. &addr);
  105. if (ret)
  106. continue;
  107. if (PCI_MASK_BUS(addr.phys_hi) != PCI_MASK_BUS(bdf))
  108. continue;
  109. *rnode = node;
  110. break;
  111. }
  112. };
  113. int pci_bus_find_devfn(const struct udevice *bus, pci_dev_t find_devfn,
  114. struct udevice **devp)
  115. {
  116. struct udevice *dev;
  117. for (device_find_first_child(bus, &dev);
  118. dev;
  119. device_find_next_child(&dev)) {
  120. struct pci_child_plat *pplat;
  121. pplat = dev_get_parent_plat(dev);
  122. if (pplat && pplat->devfn == find_devfn) {
  123. *devp = dev;
  124. return 0;
  125. }
  126. }
  127. return -ENODEV;
  128. }
  129. int dm_pci_bus_find_bdf(pci_dev_t bdf, struct udevice **devp)
  130. {
  131. struct udevice *bus;
  132. int ret;
  133. ret = pci_get_bus(PCI_BUS(bdf), &bus);
  134. if (ret)
  135. return ret;
  136. return pci_bus_find_devfn(bus, PCI_MASK_BUS(bdf), devp);
  137. }
  138. static int pci_device_matches_ids(struct udevice *dev,
  139. struct pci_device_id *ids)
  140. {
  141. struct pci_child_plat *pplat;
  142. int i;
  143. pplat = dev_get_parent_plat(dev);
  144. if (!pplat)
  145. return -EINVAL;
  146. for (i = 0; ids[i].vendor != 0; i++) {
  147. if (pplat->vendor == ids[i].vendor &&
  148. pplat->device == ids[i].device)
  149. return i;
  150. }
  151. return -EINVAL;
  152. }
  153. int pci_bus_find_devices(struct udevice *bus, struct pci_device_id *ids,
  154. int *indexp, struct udevice **devp)
  155. {
  156. struct udevice *dev;
  157. /* Scan all devices on this bus */
  158. for (device_find_first_child(bus, &dev);
  159. dev;
  160. device_find_next_child(&dev)) {
  161. if (pci_device_matches_ids(dev, ids) >= 0) {
  162. if ((*indexp)-- <= 0) {
  163. *devp = dev;
  164. return 0;
  165. }
  166. }
  167. }
  168. return -ENODEV;
  169. }
  170. int pci_find_device_id(struct pci_device_id *ids, int index,
  171. struct udevice **devp)
  172. {
  173. struct udevice *bus;
  174. /* Scan all known buses */
  175. for (uclass_first_device(UCLASS_PCI, &bus);
  176. bus;
  177. uclass_next_device(&bus)) {
  178. if (!pci_bus_find_devices(bus, ids, &index, devp))
  179. return 0;
  180. }
  181. *devp = NULL;
  182. return -ENODEV;
  183. }
  184. static int dm_pci_bus_find_device(struct udevice *bus, unsigned int vendor,
  185. unsigned int device, int *indexp,
  186. struct udevice **devp)
  187. {
  188. struct pci_child_plat *pplat;
  189. struct udevice *dev;
  190. for (device_find_first_child(bus, &dev);
  191. dev;
  192. device_find_next_child(&dev)) {
  193. pplat = dev_get_parent_plat(dev);
  194. if (pplat->vendor == vendor && pplat->device == device) {
  195. if (!(*indexp)--) {
  196. *devp = dev;
  197. return 0;
  198. }
  199. }
  200. }
  201. return -ENODEV;
  202. }
  203. int dm_pci_find_device(unsigned int vendor, unsigned int device, int index,
  204. struct udevice **devp)
  205. {
  206. struct udevice *bus;
  207. /* Scan all known buses */
  208. for (uclass_first_device(UCLASS_PCI, &bus);
  209. bus;
  210. uclass_next_device(&bus)) {
  211. if (!dm_pci_bus_find_device(bus, vendor, device, &index, devp))
  212. return device_probe(*devp);
  213. }
  214. *devp = NULL;
  215. return -ENODEV;
  216. }
  217. int dm_pci_find_class(uint find_class, int index, struct udevice **devp)
  218. {
  219. struct udevice *dev;
  220. /* Scan all known buses */
  221. for (pci_find_first_device(&dev);
  222. dev;
  223. pci_find_next_device(&dev)) {
  224. struct pci_child_plat *pplat = dev_get_parent_plat(dev);
  225. if (pplat->class == find_class && !index--) {
  226. *devp = dev;
  227. return device_probe(*devp);
  228. }
  229. }
  230. *devp = NULL;
  231. return -ENODEV;
  232. }
  233. int pci_bus_write_config(struct udevice *bus, pci_dev_t bdf, int offset,
  234. unsigned long value, enum pci_size_t size)
  235. {
  236. struct dm_pci_ops *ops;
  237. ops = pci_get_ops(bus);
  238. if (!ops->write_config)
  239. return -ENOSYS;
  240. return ops->write_config(bus, bdf, offset, value, size);
  241. }
  242. int pci_bus_clrset_config32(struct udevice *bus, pci_dev_t bdf, int offset,
  243. u32 clr, u32 set)
  244. {
  245. ulong val;
  246. int ret;
  247. ret = pci_bus_read_config(bus, bdf, offset, &val, PCI_SIZE_32);
  248. if (ret)
  249. return ret;
  250. val &= ~clr;
  251. val |= set;
  252. return pci_bus_write_config(bus, bdf, offset, val, PCI_SIZE_32);
  253. }
  254. int pci_write_config(pci_dev_t bdf, int offset, unsigned long value,
  255. enum pci_size_t size)
  256. {
  257. struct udevice *bus;
  258. int ret;
  259. ret = pci_get_bus(PCI_BUS(bdf), &bus);
  260. if (ret)
  261. return ret;
  262. return pci_bus_write_config(bus, bdf, offset, value, size);
  263. }
  264. int dm_pci_write_config(struct udevice *dev, int offset, unsigned long value,
  265. enum pci_size_t size)
  266. {
  267. struct udevice *bus;
  268. for (bus = dev; device_is_on_pci_bus(bus);)
  269. bus = bus->parent;
  270. return pci_bus_write_config(bus, dm_pci_get_bdf(dev), offset, value,
  271. size);
  272. }
  273. int pci_write_config32(pci_dev_t bdf, int offset, u32 value)
  274. {
  275. return pci_write_config(bdf, offset, value, PCI_SIZE_32);
  276. }
  277. int pci_write_config16(pci_dev_t bdf, int offset, u16 value)
  278. {
  279. return pci_write_config(bdf, offset, value, PCI_SIZE_16);
  280. }
  281. int pci_write_config8(pci_dev_t bdf, int offset, u8 value)
  282. {
  283. return pci_write_config(bdf, offset, value, PCI_SIZE_8);
  284. }
  285. int dm_pci_write_config8(struct udevice *dev, int offset, u8 value)
  286. {
  287. return dm_pci_write_config(dev, offset, value, PCI_SIZE_8);
  288. }
  289. int dm_pci_write_config16(struct udevice *dev, int offset, u16 value)
  290. {
  291. return dm_pci_write_config(dev, offset, value, PCI_SIZE_16);
  292. }
  293. int dm_pci_write_config32(struct udevice *dev, int offset, u32 value)
  294. {
  295. return dm_pci_write_config(dev, offset, value, PCI_SIZE_32);
  296. }
  297. int pci_bus_read_config(const struct udevice *bus, pci_dev_t bdf, int offset,
  298. unsigned long *valuep, enum pci_size_t size)
  299. {
  300. struct dm_pci_ops *ops;
  301. ops = pci_get_ops(bus);
  302. if (!ops->read_config)
  303. return -ENOSYS;
  304. return ops->read_config(bus, bdf, offset, valuep, size);
  305. }
  306. int pci_read_config(pci_dev_t bdf, int offset, unsigned long *valuep,
  307. enum pci_size_t size)
  308. {
  309. struct udevice *bus;
  310. int ret;
  311. ret = pci_get_bus(PCI_BUS(bdf), &bus);
  312. if (ret)
  313. return ret;
  314. return pci_bus_read_config(bus, bdf, offset, valuep, size);
  315. }
  316. int dm_pci_read_config(const struct udevice *dev, int offset,
  317. unsigned long *valuep, enum pci_size_t size)
  318. {
  319. const struct udevice *bus;
  320. for (bus = dev; device_is_on_pci_bus(bus);)
  321. bus = bus->parent;
  322. return pci_bus_read_config(bus, dm_pci_get_bdf(dev), offset, valuep,
  323. size);
  324. }
  325. int pci_read_config32(pci_dev_t bdf, int offset, u32 *valuep)
  326. {
  327. unsigned long value;
  328. int ret;
  329. ret = pci_read_config(bdf, offset, &value, PCI_SIZE_32);
  330. if (ret)
  331. return ret;
  332. *valuep = value;
  333. return 0;
  334. }
  335. int pci_read_config16(pci_dev_t bdf, int offset, u16 *valuep)
  336. {
  337. unsigned long value;
  338. int ret;
  339. ret = pci_read_config(bdf, offset, &value, PCI_SIZE_16);
  340. if (ret)
  341. return ret;
  342. *valuep = value;
  343. return 0;
  344. }
  345. int pci_read_config8(pci_dev_t bdf, int offset, u8 *valuep)
  346. {
  347. unsigned long value;
  348. int ret;
  349. ret = pci_read_config(bdf, offset, &value, PCI_SIZE_8);
  350. if (ret)
  351. return ret;
  352. *valuep = value;
  353. return 0;
  354. }
  355. int dm_pci_read_config8(const struct udevice *dev, int offset, u8 *valuep)
  356. {
  357. unsigned long value;
  358. int ret;
  359. ret = dm_pci_read_config(dev, offset, &value, PCI_SIZE_8);
  360. if (ret)
  361. return ret;
  362. *valuep = value;
  363. return 0;
  364. }
  365. int dm_pci_read_config16(const struct udevice *dev, int offset, u16 *valuep)
  366. {
  367. unsigned long value;
  368. int ret;
  369. ret = dm_pci_read_config(dev, offset, &value, PCI_SIZE_16);
  370. if (ret)
  371. return ret;
  372. *valuep = value;
  373. return 0;
  374. }
  375. int dm_pci_read_config32(const struct udevice *dev, int offset, u32 *valuep)
  376. {
  377. unsigned long value;
  378. int ret;
  379. ret = dm_pci_read_config(dev, offset, &value, PCI_SIZE_32);
  380. if (ret)
  381. return ret;
  382. *valuep = value;
  383. return 0;
  384. }
  385. int dm_pci_clrset_config8(struct udevice *dev, int offset, u32 clr, u32 set)
  386. {
  387. u8 val;
  388. int ret;
  389. ret = dm_pci_read_config8(dev, offset, &val);
  390. if (ret)
  391. return ret;
  392. val &= ~clr;
  393. val |= set;
  394. return dm_pci_write_config8(dev, offset, val);
  395. }
  396. int dm_pci_clrset_config16(struct udevice *dev, int offset, u32 clr, u32 set)
  397. {
  398. u16 val;
  399. int ret;
  400. ret = dm_pci_read_config16(dev, offset, &val);
  401. if (ret)
  402. return ret;
  403. val &= ~clr;
  404. val |= set;
  405. return dm_pci_write_config16(dev, offset, val);
  406. }
  407. int dm_pci_clrset_config32(struct udevice *dev, int offset, u32 clr, u32 set)
  408. {
  409. u32 val;
  410. int ret;
  411. ret = dm_pci_read_config32(dev, offset, &val);
  412. if (ret)
  413. return ret;
  414. val &= ~clr;
  415. val |= set;
  416. return dm_pci_write_config32(dev, offset, val);
  417. }
  418. static void set_vga_bridge_bits(struct udevice *dev)
  419. {
  420. struct udevice *parent = dev->parent;
  421. u16 bc;
  422. while (dev_seq(parent) != 0) {
  423. dm_pci_read_config16(parent, PCI_BRIDGE_CONTROL, &bc);
  424. bc |= PCI_BRIDGE_CTL_VGA;
  425. dm_pci_write_config16(parent, PCI_BRIDGE_CONTROL, bc);
  426. parent = parent->parent;
  427. }
  428. }
  429. int pci_auto_config_devices(struct udevice *bus)
  430. {
  431. struct pci_controller *hose = dev_get_uclass_priv(bus);
  432. struct pci_child_plat *pplat;
  433. unsigned int sub_bus;
  434. struct udevice *dev;
  435. int ret;
  436. sub_bus = dev_seq(bus);
  437. debug("%s: start\n", __func__);
  438. pciauto_config_init(hose);
  439. for (ret = device_find_first_child(bus, &dev);
  440. !ret && dev;
  441. ret = device_find_next_child(&dev)) {
  442. unsigned int max_bus;
  443. int ret;
  444. debug("%s: device %s\n", __func__, dev->name);
  445. if (dev_has_ofnode(dev) &&
  446. dev_read_bool(dev, "pci,no-autoconfig"))
  447. continue;
  448. ret = dm_pciauto_config_device(dev);
  449. if (ret < 0)
  450. return log_msg_ret("auto", ret);
  451. max_bus = ret;
  452. sub_bus = max(sub_bus, max_bus);
  453. if (dev_get_parent(dev) == bus)
  454. continue;
  455. pplat = dev_get_parent_plat(dev);
  456. if (pplat->class == (PCI_CLASS_DISPLAY_VGA << 8))
  457. set_vga_bridge_bits(dev);
  458. }
  459. debug("%s: done\n", __func__);
  460. return log_msg_ret("sub", sub_bus);
  461. }
  462. int pci_generic_mmap_write_config(
  463. const struct udevice *bus,
  464. int (*addr_f)(const struct udevice *bus, pci_dev_t bdf, uint offset,
  465. void **addrp),
  466. pci_dev_t bdf,
  467. uint offset,
  468. ulong value,
  469. enum pci_size_t size)
  470. {
  471. void *address;
  472. if (addr_f(bus, bdf, offset, &address) < 0)
  473. return 0;
  474. switch (size) {
  475. case PCI_SIZE_8:
  476. writeb(value, address);
  477. return 0;
  478. case PCI_SIZE_16:
  479. writew(value, address);
  480. return 0;
  481. case PCI_SIZE_32:
  482. writel(value, address);
  483. return 0;
  484. default:
  485. return -EINVAL;
  486. }
  487. }
  488. int pci_generic_mmap_read_config(
  489. const struct udevice *bus,
  490. int (*addr_f)(const struct udevice *bus, pci_dev_t bdf, uint offset,
  491. void **addrp),
  492. pci_dev_t bdf,
  493. uint offset,
  494. ulong *valuep,
  495. enum pci_size_t size)
  496. {
  497. void *address;
  498. if (addr_f(bus, bdf, offset, &address) < 0) {
  499. *valuep = pci_get_ff(size);
  500. return 0;
  501. }
  502. switch (size) {
  503. case PCI_SIZE_8:
  504. *valuep = readb(address);
  505. return 0;
  506. case PCI_SIZE_16:
  507. *valuep = readw(address);
  508. return 0;
  509. case PCI_SIZE_32:
  510. *valuep = readl(address);
  511. return 0;
  512. default:
  513. return -EINVAL;
  514. }
  515. }
  516. int dm_pci_hose_probe_bus(struct udevice *bus)
  517. {
  518. int sub_bus;
  519. int ret;
  520. int ea_pos;
  521. u8 reg;
  522. debug("%s\n", __func__);
  523. ea_pos = dm_pci_find_capability(bus, PCI_CAP_ID_EA);
  524. if (ea_pos) {
  525. dm_pci_read_config8(bus, ea_pos + sizeof(u32) + sizeof(u8),
  526. &reg);
  527. sub_bus = reg;
  528. } else {
  529. sub_bus = pci_get_bus_max() + 1;
  530. }
  531. debug("%s: bus = %d/%s\n", __func__, sub_bus, bus->name);
  532. dm_pciauto_prescan_setup_bridge(bus, sub_bus);
  533. ret = device_probe(bus);
  534. if (ret) {
  535. debug("%s: Cannot probe bus %s: %d\n", __func__, bus->name,
  536. ret);
  537. return log_msg_ret("probe", ret);
  538. }
  539. if (!ea_pos)
  540. sub_bus = pci_get_bus_max();
  541. dm_pciauto_postscan_setup_bridge(bus, sub_bus);
  542. return sub_bus;
  543. }
  544. /**
  545. * pci_match_one_device - Tell if a PCI device structure has a matching
  546. * PCI device id structure
  547. * @id: single PCI device id structure to match
  548. * @find: the PCI device id structure to match against
  549. *
  550. * Returns true if the finding pci_device_id structure matched or false if
  551. * there is no match.
  552. */
  553. static bool pci_match_one_id(const struct pci_device_id *id,
  554. const struct pci_device_id *find)
  555. {
  556. if ((id->vendor == PCI_ANY_ID || id->vendor == find->vendor) &&
  557. (id->device == PCI_ANY_ID || id->device == find->device) &&
  558. (id->subvendor == PCI_ANY_ID || id->subvendor == find->subvendor) &&
  559. (id->subdevice == PCI_ANY_ID || id->subdevice == find->subdevice) &&
  560. !((id->class ^ find->class) & id->class_mask))
  561. return true;
  562. return false;
  563. }
  564. /**
  565. * pci_find_and_bind_driver() - Find and bind the right PCI driver
  566. *
  567. * This only looks at certain fields in the descriptor.
  568. *
  569. * @parent: Parent bus
  570. * @find_id: Specification of the driver to find
  571. * @bdf: Bus/device/function addreess - see PCI_BDF()
  572. * @devp: Returns a pointer to the device created
  573. * @return 0 if OK, -EPERM if the device is not needed before relocation and
  574. * therefore was not created, other -ve value on error
  575. */
  576. static int pci_find_and_bind_driver(struct udevice *parent,
  577. struct pci_device_id *find_id,
  578. pci_dev_t bdf, struct udevice **devp)
  579. {
  580. struct pci_driver_entry *start, *entry;
  581. ofnode node = ofnode_null();
  582. const char *drv;
  583. int n_ents;
  584. int ret;
  585. char name[30], *str;
  586. bool bridge;
  587. *devp = NULL;
  588. debug("%s: Searching for driver: vendor=%x, device=%x\n", __func__,
  589. find_id->vendor, find_id->device);
  590. /* Determine optional OF node */
  591. if (ofnode_valid(dev_ofnode(parent)))
  592. pci_dev_find_ofnode(parent, bdf, &node);
  593. if (ofnode_valid(node) && !ofnode_is_available(node)) {
  594. debug("%s: Ignoring disabled device\n", __func__);
  595. return log_msg_ret("dis", -EPERM);
  596. }
  597. start = ll_entry_start(struct pci_driver_entry, pci_driver_entry);
  598. n_ents = ll_entry_count(struct pci_driver_entry, pci_driver_entry);
  599. for (entry = start; entry != start + n_ents; entry++) {
  600. const struct pci_device_id *id;
  601. struct udevice *dev;
  602. const struct driver *drv;
  603. for (id = entry->match;
  604. id->vendor || id->subvendor || id->class_mask;
  605. id++) {
  606. if (!pci_match_one_id(id, find_id))
  607. continue;
  608. drv = entry->driver;
  609. /*
  610. * In the pre-relocation phase, we only bind devices
  611. * whose driver has the DM_FLAG_PRE_RELOC set, to save
  612. * precious memory space as on some platforms as that
  613. * space is pretty limited (ie: using Cache As RAM).
  614. */
  615. if (!(gd->flags & GD_FLG_RELOC) &&
  616. !(drv->flags & DM_FLAG_PRE_RELOC))
  617. return log_msg_ret("pre", -EPERM);
  618. /*
  619. * We could pass the descriptor to the driver as
  620. * plat (instead of NULL) and allow its bind()
  621. * method to return -ENOENT if it doesn't support this
  622. * device. That way we could continue the search to
  623. * find another driver. For now this doesn't seem
  624. * necesssary, so just bind the first match.
  625. */
  626. ret = device_bind(parent, drv, drv->name, NULL, node,
  627. &dev);
  628. if (ret)
  629. goto error;
  630. debug("%s: Match found: %s\n", __func__, drv->name);
  631. dev->driver_data = id->driver_data;
  632. *devp = dev;
  633. return 0;
  634. }
  635. }
  636. bridge = (find_id->class >> 8) == PCI_CLASS_BRIDGE_PCI;
  637. /*
  638. * In the pre-relocation phase, we only bind bridge devices to save
  639. * precious memory space as on some platforms as that space is pretty
  640. * limited (ie: using Cache As RAM).
  641. */
  642. if (!(gd->flags & GD_FLG_RELOC) && !bridge)
  643. return log_msg_ret("notbr", -EPERM);
  644. /* Bind a generic driver so that the device can be used */
  645. sprintf(name, "pci_%x:%x.%x", dev_seq(parent), PCI_DEV(bdf),
  646. PCI_FUNC(bdf));
  647. str = strdup(name);
  648. if (!str)
  649. return -ENOMEM;
  650. drv = bridge ? "pci_bridge_drv" : "pci_generic_drv";
  651. ret = device_bind_driver_to_node(parent, drv, str, node, devp);
  652. if (ret) {
  653. debug("%s: Failed to bind generic driver: %d\n", __func__, ret);
  654. free(str);
  655. return ret;
  656. }
  657. debug("%s: No match found: bound generic driver instead\n", __func__);
  658. return 0;
  659. error:
  660. debug("%s: No match found: error %d\n", __func__, ret);
  661. return ret;
  662. }
  663. __weak extern void board_pci_fixup_dev(struct udevice *bus, struct udevice *dev)
  664. {
  665. }
  666. int pci_bind_bus_devices(struct udevice *bus)
  667. {
  668. ulong vendor, device;
  669. ulong header_type;
  670. pci_dev_t bdf, end;
  671. bool found_multi;
  672. int ari_off;
  673. int ret;
  674. found_multi = false;
  675. end = PCI_BDF(dev_seq(bus), PCI_MAX_PCI_DEVICES - 1,
  676. PCI_MAX_PCI_FUNCTIONS - 1);
  677. for (bdf = PCI_BDF(dev_seq(bus), 0, 0); bdf <= end;
  678. bdf += PCI_BDF(0, 0, 1)) {
  679. struct pci_child_plat *pplat;
  680. struct udevice *dev;
  681. ulong class;
  682. if (!PCI_FUNC(bdf))
  683. found_multi = false;
  684. if (PCI_FUNC(bdf) && !found_multi)
  685. continue;
  686. /* Check only the first access, we don't expect problems */
  687. ret = pci_bus_read_config(bus, bdf, PCI_VENDOR_ID, &vendor,
  688. PCI_SIZE_16);
  689. if (ret)
  690. goto error;
  691. if (vendor == 0xffff || vendor == 0x0000)
  692. continue;
  693. pci_bus_read_config(bus, bdf, PCI_HEADER_TYPE,
  694. &header_type, PCI_SIZE_8);
  695. if (!PCI_FUNC(bdf))
  696. found_multi = header_type & 0x80;
  697. debug("%s: bus %d/%s: found device %x, function %d", __func__,
  698. dev_seq(bus), bus->name, PCI_DEV(bdf), PCI_FUNC(bdf));
  699. pci_bus_read_config(bus, bdf, PCI_DEVICE_ID, &device,
  700. PCI_SIZE_16);
  701. pci_bus_read_config(bus, bdf, PCI_CLASS_REVISION, &class,
  702. PCI_SIZE_32);
  703. class >>= 8;
  704. /* Find this device in the device tree */
  705. ret = pci_bus_find_devfn(bus, PCI_MASK_BUS(bdf), &dev);
  706. debug(": find ret=%d\n", ret);
  707. /* If nothing in the device tree, bind a device */
  708. if (ret == -ENODEV) {
  709. struct pci_device_id find_id;
  710. ulong val;
  711. memset(&find_id, '\0', sizeof(find_id));
  712. find_id.vendor = vendor;
  713. find_id.device = device;
  714. find_id.class = class;
  715. if ((header_type & 0x7f) == PCI_HEADER_TYPE_NORMAL) {
  716. pci_bus_read_config(bus, bdf,
  717. PCI_SUBSYSTEM_VENDOR_ID,
  718. &val, PCI_SIZE_32);
  719. find_id.subvendor = val & 0xffff;
  720. find_id.subdevice = val >> 16;
  721. }
  722. ret = pci_find_and_bind_driver(bus, &find_id, bdf,
  723. &dev);
  724. }
  725. if (ret == -EPERM)
  726. continue;
  727. else if (ret)
  728. return ret;
  729. /* Update the platform data */
  730. pplat = dev_get_parent_plat(dev);
  731. pplat->devfn = PCI_MASK_BUS(bdf);
  732. pplat->vendor = vendor;
  733. pplat->device = device;
  734. pplat->class = class;
  735. if (IS_ENABLED(CONFIG_PCI_ARID)) {
  736. ari_off = dm_pci_find_ext_capability(dev,
  737. PCI_EXT_CAP_ID_ARI);
  738. if (ari_off) {
  739. u16 ari_cap;
  740. /*
  741. * Read Next Function number in ARI Cap
  742. * Register
  743. */
  744. dm_pci_read_config16(dev, ari_off + 4,
  745. &ari_cap);
  746. /*
  747. * Update next scan on this function number,
  748. * subtract 1 in BDF to satisfy loop increment.
  749. */
  750. if (ari_cap & 0xff00) {
  751. bdf = PCI_BDF(PCI_BUS(bdf),
  752. PCI_DEV(ari_cap),
  753. PCI_FUNC(ari_cap));
  754. bdf = bdf - 0x100;
  755. }
  756. }
  757. }
  758. board_pci_fixup_dev(bus, dev);
  759. }
  760. return 0;
  761. error:
  762. printf("Cannot read bus configuration: %d\n", ret);
  763. return ret;
  764. }
  765. static void decode_regions(struct pci_controller *hose, ofnode parent_node,
  766. ofnode node)
  767. {
  768. int pci_addr_cells, addr_cells, size_cells;
  769. int cells_per_record;
  770. struct bd_info *bd;
  771. const u32 *prop;
  772. int max_regions;
  773. int len;
  774. int i;
  775. prop = ofnode_get_property(node, "ranges", &len);
  776. if (!prop) {
  777. debug("%s: Cannot decode regions\n", __func__);
  778. return;
  779. }
  780. pci_addr_cells = ofnode_read_simple_addr_cells(node);
  781. addr_cells = ofnode_read_simple_addr_cells(parent_node);
  782. size_cells = ofnode_read_simple_size_cells(node);
  783. /* PCI addresses are always 3-cells */
  784. len /= sizeof(u32);
  785. cells_per_record = pci_addr_cells + addr_cells + size_cells;
  786. hose->region_count = 0;
  787. debug("%s: len=%d, cells_per_record=%d\n", __func__, len,
  788. cells_per_record);
  789. /* Dynamically allocate the regions array */
  790. max_regions = len / cells_per_record + CONFIG_NR_DRAM_BANKS;
  791. hose->regions = (struct pci_region *)
  792. calloc(1, max_regions * sizeof(struct pci_region));
  793. for (i = 0; i < max_regions; i++, len -= cells_per_record) {
  794. u64 pci_addr, addr, size;
  795. int space_code;
  796. u32 flags;
  797. int type;
  798. int pos;
  799. if (len < cells_per_record)
  800. break;
  801. flags = fdt32_to_cpu(prop[0]);
  802. space_code = (flags >> 24) & 3;
  803. pci_addr = fdtdec_get_number(prop + 1, 2);
  804. prop += pci_addr_cells;
  805. addr = fdtdec_get_number(prop, addr_cells);
  806. prop += addr_cells;
  807. size = fdtdec_get_number(prop, size_cells);
  808. prop += size_cells;
  809. debug("%s: region %d, pci_addr=%llx, addr=%llx, size=%llx, space_code=%d\n",
  810. __func__, hose->region_count, pci_addr, addr, size, space_code);
  811. if (space_code & 2) {
  812. type = flags & (1U << 30) ? PCI_REGION_PREFETCH :
  813. PCI_REGION_MEM;
  814. } else if (space_code & 1) {
  815. type = PCI_REGION_IO;
  816. } else {
  817. continue;
  818. }
  819. if (!IS_ENABLED(CONFIG_SYS_PCI_64BIT) &&
  820. type == PCI_REGION_MEM && upper_32_bits(pci_addr)) {
  821. debug(" - beyond the 32-bit boundary, ignoring\n");
  822. continue;
  823. }
  824. pos = -1;
  825. if (!IS_ENABLED(CONFIG_PCI_REGION_MULTI_ENTRY)) {
  826. for (i = 0; i < hose->region_count; i++) {
  827. if (hose->regions[i].flags == type)
  828. pos = i;
  829. }
  830. }
  831. if (pos == -1)
  832. pos = hose->region_count++;
  833. debug(" - type=%d, pos=%d\n", type, pos);
  834. pci_set_region(hose->regions + pos, pci_addr, addr, size, type);
  835. }
  836. /* Add a region for our local memory */
  837. bd = gd->bd;
  838. if (!bd)
  839. return;
  840. for (i = 0; i < CONFIG_NR_DRAM_BANKS; ++i) {
  841. if (bd->bi_dram[i].size) {
  842. pci_set_region(hose->regions + hose->region_count++,
  843. bd->bi_dram[i].start,
  844. bd->bi_dram[i].start,
  845. bd->bi_dram[i].size,
  846. PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
  847. }
  848. }
  849. return;
  850. }
  851. static int pci_uclass_pre_probe(struct udevice *bus)
  852. {
  853. struct pci_controller *hose;
  854. struct uclass *uc;
  855. int ret;
  856. debug("%s, bus=%d/%s, parent=%s\n", __func__, dev_seq(bus), bus->name,
  857. bus->parent->name);
  858. hose = dev_get_uclass_priv(bus);
  859. /*
  860. * Set the sequence number, if device_bind() doesn't. We want control
  861. * of this so that numbers are allocated as devices are probed. That
  862. * ensures that sub-bus numbered is correct (sub-buses must get numbers
  863. * higher than their parents)
  864. */
  865. if (dev_seq(bus) == -1) {
  866. ret = uclass_get(UCLASS_PCI, &uc);
  867. if (ret)
  868. return ret;
  869. bus->seq_ = uclass_find_next_free_seq(uc);
  870. }
  871. /* For bridges, use the top-level PCI controller */
  872. if (!device_is_on_pci_bus(bus)) {
  873. hose->ctlr = bus;
  874. decode_regions(hose, dev_ofnode(bus->parent), dev_ofnode(bus));
  875. } else {
  876. struct pci_controller *parent_hose;
  877. parent_hose = dev_get_uclass_priv(bus->parent);
  878. hose->ctlr = parent_hose->bus;
  879. }
  880. hose->bus = bus;
  881. hose->first_busno = dev_seq(bus);
  882. hose->last_busno = dev_seq(bus);
  883. if (dev_has_ofnode(bus)) {
  884. hose->skip_auto_config_until_reloc =
  885. dev_read_bool(bus,
  886. "u-boot,skip-auto-config-until-reloc");
  887. }
  888. return 0;
  889. }
  890. static int pci_uclass_post_probe(struct udevice *bus)
  891. {
  892. struct pci_controller *hose = dev_get_uclass_priv(bus);
  893. int ret;
  894. debug("%s: probing bus %d\n", __func__, dev_seq(bus));
  895. ret = pci_bind_bus_devices(bus);
  896. if (ret)
  897. return log_msg_ret("bind", ret);
  898. if (CONFIG_IS_ENABLED(PCI_PNP) && ll_boot_init() &&
  899. (!hose->skip_auto_config_until_reloc ||
  900. (gd->flags & GD_FLG_RELOC))) {
  901. ret = pci_auto_config_devices(bus);
  902. if (ret < 0)
  903. return log_msg_ret("cfg", ret);
  904. }
  905. #if defined(CONFIG_X86) && defined(CONFIG_HAVE_FSP)
  906. /*
  907. * Per Intel FSP specification, we should call FSP notify API to
  908. * inform FSP that PCI enumeration has been done so that FSP will
  909. * do any necessary initialization as required by the chipset's
  910. * BIOS Writer's Guide (BWG).
  911. *
  912. * Unfortunately we have to put this call here as with driver model,
  913. * the enumeration is all done on a lazy basis as needed, so until
  914. * something is touched on PCI it won't happen.
  915. *
  916. * Note we only call this 1) after U-Boot is relocated, and 2)
  917. * root bus has finished probing.
  918. */
  919. if ((gd->flags & GD_FLG_RELOC) && dev_seq(bus) == 0 && ll_boot_init()) {
  920. ret = fsp_init_phase_pci();
  921. if (ret)
  922. return log_msg_ret("fsp", ret);
  923. }
  924. #endif
  925. return 0;
  926. }
  927. static int pci_uclass_child_post_bind(struct udevice *dev)
  928. {
  929. struct pci_child_plat *pplat;
  930. if (!dev_has_ofnode(dev))
  931. return 0;
  932. pplat = dev_get_parent_plat(dev);
  933. /* Extract vendor id and device id if available */
  934. ofnode_read_pci_vendev(dev_ofnode(dev), &pplat->vendor, &pplat->device);
  935. /* Extract the devfn from fdt_pci_addr */
  936. pplat->devfn = pci_get_devfn(dev);
  937. return 0;
  938. }
  939. static int pci_bridge_read_config(const struct udevice *bus, pci_dev_t bdf,
  940. uint offset, ulong *valuep,
  941. enum pci_size_t size)
  942. {
  943. struct pci_controller *hose = dev_get_uclass_priv(bus);
  944. return pci_bus_read_config(hose->ctlr, bdf, offset, valuep, size);
  945. }
  946. static int pci_bridge_write_config(struct udevice *bus, pci_dev_t bdf,
  947. uint offset, ulong value,
  948. enum pci_size_t size)
  949. {
  950. struct pci_controller *hose = dev_get_uclass_priv(bus);
  951. return pci_bus_write_config(hose->ctlr, bdf, offset, value, size);
  952. }
  953. static int skip_to_next_device(struct udevice *bus, struct udevice **devp)
  954. {
  955. struct udevice *dev;
  956. int ret = 0;
  957. /*
  958. * Scan through all the PCI controllers. On x86 there will only be one
  959. * but that is not necessarily true on other hardware.
  960. */
  961. do {
  962. device_find_first_child(bus, &dev);
  963. if (dev) {
  964. *devp = dev;
  965. return 0;
  966. }
  967. ret = uclass_next_device(&bus);
  968. if (ret)
  969. return ret;
  970. } while (bus);
  971. return 0;
  972. }
  973. int pci_find_next_device(struct udevice **devp)
  974. {
  975. struct udevice *child = *devp;
  976. struct udevice *bus = child->parent;
  977. int ret;
  978. /* First try all the siblings */
  979. *devp = NULL;
  980. while (child) {
  981. device_find_next_child(&child);
  982. if (child) {
  983. *devp = child;
  984. return 0;
  985. }
  986. }
  987. /* We ran out of siblings. Try the next bus */
  988. ret = uclass_next_device(&bus);
  989. if (ret)
  990. return ret;
  991. return bus ? skip_to_next_device(bus, devp) : 0;
  992. }
  993. int pci_find_first_device(struct udevice **devp)
  994. {
  995. struct udevice *bus;
  996. int ret;
  997. *devp = NULL;
  998. ret = uclass_first_device(UCLASS_PCI, &bus);
  999. if (ret)
  1000. return ret;
  1001. return skip_to_next_device(bus, devp);
  1002. }
  1003. ulong pci_conv_32_to_size(ulong value, uint offset, enum pci_size_t size)
  1004. {
  1005. switch (size) {
  1006. case PCI_SIZE_8:
  1007. return (value >> ((offset & 3) * 8)) & 0xff;
  1008. case PCI_SIZE_16:
  1009. return (value >> ((offset & 2) * 8)) & 0xffff;
  1010. default:
  1011. return value;
  1012. }
  1013. }
  1014. ulong pci_conv_size_to_32(ulong old, ulong value, uint offset,
  1015. enum pci_size_t size)
  1016. {
  1017. uint off_mask;
  1018. uint val_mask, shift;
  1019. ulong ldata, mask;
  1020. switch (size) {
  1021. case PCI_SIZE_8:
  1022. off_mask = 3;
  1023. val_mask = 0xff;
  1024. break;
  1025. case PCI_SIZE_16:
  1026. off_mask = 2;
  1027. val_mask = 0xffff;
  1028. break;
  1029. default:
  1030. return value;
  1031. }
  1032. shift = (offset & off_mask) * 8;
  1033. ldata = (value & val_mask) << shift;
  1034. mask = val_mask << shift;
  1035. value = (old & ~mask) | ldata;
  1036. return value;
  1037. }
  1038. int pci_get_dma_regions(struct udevice *dev, struct pci_region *memp, int index)
  1039. {
  1040. int pci_addr_cells, addr_cells, size_cells;
  1041. int cells_per_record;
  1042. const u32 *prop;
  1043. int len;
  1044. int i = 0;
  1045. prop = ofnode_get_property(dev_ofnode(dev), "dma-ranges", &len);
  1046. if (!prop) {
  1047. log_err("PCI: Device '%s': Cannot decode dma-ranges\n",
  1048. dev->name);
  1049. return -EINVAL;
  1050. }
  1051. pci_addr_cells = ofnode_read_simple_addr_cells(dev_ofnode(dev));
  1052. addr_cells = ofnode_read_simple_addr_cells(dev_ofnode(dev->parent));
  1053. size_cells = ofnode_read_simple_size_cells(dev_ofnode(dev));
  1054. /* PCI addresses are always 3-cells */
  1055. len /= sizeof(u32);
  1056. cells_per_record = pci_addr_cells + addr_cells + size_cells;
  1057. debug("%s: len=%d, cells_per_record=%d\n", __func__, len,
  1058. cells_per_record);
  1059. while (len) {
  1060. memp->bus_start = fdtdec_get_number(prop + 1, 2);
  1061. prop += pci_addr_cells;
  1062. memp->phys_start = fdtdec_get_number(prop, addr_cells);
  1063. prop += addr_cells;
  1064. memp->size = fdtdec_get_number(prop, size_cells);
  1065. prop += size_cells;
  1066. if (i == index)
  1067. return 0;
  1068. i++;
  1069. len -= cells_per_record;
  1070. }
  1071. return -EINVAL;
  1072. }
  1073. int pci_get_regions(struct udevice *dev, struct pci_region **iop,
  1074. struct pci_region **memp, struct pci_region **prefp)
  1075. {
  1076. struct udevice *bus = pci_get_controller(dev);
  1077. struct pci_controller *hose = dev_get_uclass_priv(bus);
  1078. int i;
  1079. *iop = NULL;
  1080. *memp = NULL;
  1081. *prefp = NULL;
  1082. for (i = 0; i < hose->region_count; i++) {
  1083. switch (hose->regions[i].flags) {
  1084. case PCI_REGION_IO:
  1085. if (!*iop || (*iop)->size < hose->regions[i].size)
  1086. *iop = hose->regions + i;
  1087. break;
  1088. case PCI_REGION_MEM:
  1089. if (!*memp || (*memp)->size < hose->regions[i].size)
  1090. *memp = hose->regions + i;
  1091. break;
  1092. case (PCI_REGION_MEM | PCI_REGION_PREFETCH):
  1093. if (!*prefp || (*prefp)->size < hose->regions[i].size)
  1094. *prefp = hose->regions + i;
  1095. break;
  1096. }
  1097. }
  1098. return (*iop != NULL) + (*memp != NULL) + (*prefp != NULL);
  1099. }
  1100. u32 dm_pci_read_bar32(const struct udevice *dev, int barnum)
  1101. {
  1102. u32 addr;
  1103. int bar;
  1104. bar = PCI_BASE_ADDRESS_0 + barnum * 4;
  1105. dm_pci_read_config32(dev, bar, &addr);
  1106. /*
  1107. * If we get an invalid address, return this so that comparisons with
  1108. * FDT_ADDR_T_NONE work correctly
  1109. */
  1110. if (addr == 0xffffffff)
  1111. return addr;
  1112. else if (addr & PCI_BASE_ADDRESS_SPACE_IO)
  1113. return addr & PCI_BASE_ADDRESS_IO_MASK;
  1114. else
  1115. return addr & PCI_BASE_ADDRESS_MEM_MASK;
  1116. }
  1117. void dm_pci_write_bar32(struct udevice *dev, int barnum, u32 addr)
  1118. {
  1119. int bar;
  1120. bar = PCI_BASE_ADDRESS_0 + barnum * 4;
  1121. dm_pci_write_config32(dev, bar, addr);
  1122. }
  1123. static int _dm_pci_bus_to_phys(struct udevice *ctlr,
  1124. pci_addr_t bus_addr, unsigned long flags,
  1125. unsigned long skip_mask, phys_addr_t *pa)
  1126. {
  1127. struct pci_controller *hose = dev_get_uclass_priv(ctlr);
  1128. struct pci_region *res;
  1129. int i;
  1130. if (hose->region_count == 0) {
  1131. *pa = bus_addr;
  1132. return 0;
  1133. }
  1134. for (i = 0; i < hose->region_count; i++) {
  1135. res = &hose->regions[i];
  1136. if (((res->flags ^ flags) & PCI_REGION_TYPE) != 0)
  1137. continue;
  1138. if (res->flags & skip_mask)
  1139. continue;
  1140. if (bus_addr >= res->bus_start &&
  1141. (bus_addr - res->bus_start) < res->size) {
  1142. *pa = (bus_addr - res->bus_start + res->phys_start);
  1143. return 0;
  1144. }
  1145. }
  1146. return 1;
  1147. }
  1148. phys_addr_t dm_pci_bus_to_phys(struct udevice *dev, pci_addr_t bus_addr,
  1149. unsigned long flags)
  1150. {
  1151. phys_addr_t phys_addr = 0;
  1152. struct udevice *ctlr;
  1153. int ret;
  1154. /* The root controller has the region information */
  1155. ctlr = pci_get_controller(dev);
  1156. /*
  1157. * if PCI_REGION_MEM is set we do a two pass search with preference
  1158. * on matches that don't have PCI_REGION_SYS_MEMORY set
  1159. */
  1160. if ((flags & PCI_REGION_TYPE) == PCI_REGION_MEM) {
  1161. ret = _dm_pci_bus_to_phys(ctlr, bus_addr,
  1162. flags, PCI_REGION_SYS_MEMORY,
  1163. &phys_addr);
  1164. if (!ret)
  1165. return phys_addr;
  1166. }
  1167. ret = _dm_pci_bus_to_phys(ctlr, bus_addr, flags, 0, &phys_addr);
  1168. if (ret)
  1169. puts("pci_hose_bus_to_phys: invalid physical address\n");
  1170. return phys_addr;
  1171. }
  1172. int _dm_pci_phys_to_bus(struct udevice *dev, phys_addr_t phys_addr,
  1173. unsigned long flags, unsigned long skip_mask,
  1174. pci_addr_t *ba)
  1175. {
  1176. struct pci_region *res;
  1177. struct udevice *ctlr;
  1178. pci_addr_t bus_addr;
  1179. int i;
  1180. struct pci_controller *hose;
  1181. /* The root controller has the region information */
  1182. ctlr = pci_get_controller(dev);
  1183. hose = dev_get_uclass_priv(ctlr);
  1184. if (hose->region_count == 0) {
  1185. *ba = phys_addr;
  1186. return 0;
  1187. }
  1188. for (i = 0; i < hose->region_count; i++) {
  1189. res = &hose->regions[i];
  1190. if (((res->flags ^ flags) & PCI_REGION_TYPE) != 0)
  1191. continue;
  1192. if (res->flags & skip_mask)
  1193. continue;
  1194. bus_addr = phys_addr - res->phys_start + res->bus_start;
  1195. if (bus_addr >= res->bus_start &&
  1196. (bus_addr - res->bus_start) < res->size) {
  1197. *ba = bus_addr;
  1198. return 0;
  1199. }
  1200. }
  1201. return 1;
  1202. }
  1203. pci_addr_t dm_pci_phys_to_bus(struct udevice *dev, phys_addr_t phys_addr,
  1204. unsigned long flags)
  1205. {
  1206. pci_addr_t bus_addr = 0;
  1207. int ret;
  1208. /*
  1209. * if PCI_REGION_MEM is set we do a two pass search with preference
  1210. * on matches that don't have PCI_REGION_SYS_MEMORY set
  1211. */
  1212. if ((flags & PCI_REGION_TYPE) == PCI_REGION_MEM) {
  1213. ret = _dm_pci_phys_to_bus(dev, phys_addr, flags,
  1214. PCI_REGION_SYS_MEMORY, &bus_addr);
  1215. if (!ret)
  1216. return bus_addr;
  1217. }
  1218. ret = _dm_pci_phys_to_bus(dev, phys_addr, flags, 0, &bus_addr);
  1219. if (ret)
  1220. puts("pci_hose_phys_to_bus: invalid physical address\n");
  1221. return bus_addr;
  1222. }
  1223. static phys_addr_t dm_pci_map_ea_virt(struct udevice *dev, int ea_off,
  1224. struct pci_child_plat *pdata)
  1225. {
  1226. phys_addr_t addr = 0;
  1227. /*
  1228. * In the case of a Virtual Function device using BAR
  1229. * base and size, add offset for VFn BAR(1, 2, 3...n)
  1230. */
  1231. if (pdata->is_virtfn) {
  1232. size_t sz;
  1233. u32 ea_entry;
  1234. /* MaxOffset, 1st DW */
  1235. dm_pci_read_config32(dev, ea_off + 8, &ea_entry);
  1236. sz = ea_entry & PCI_EA_FIELD_MASK;
  1237. /* Fill up lower 2 bits */
  1238. sz |= (~PCI_EA_FIELD_MASK);
  1239. if (ea_entry & PCI_EA_IS_64) {
  1240. /* MaxOffset 2nd DW */
  1241. dm_pci_read_config32(dev, ea_off + 16, &ea_entry);
  1242. sz |= ((u64)ea_entry) << 32;
  1243. }
  1244. addr = (pdata->virtid - 1) * (sz + 1);
  1245. }
  1246. return addr;
  1247. }
  1248. static void *dm_pci_map_ea_bar(struct udevice *dev, int bar, int flags,
  1249. int ea_off, struct pci_child_plat *pdata)
  1250. {
  1251. int ea_cnt, i, entry_size;
  1252. int bar_id = (bar - PCI_BASE_ADDRESS_0) >> 2;
  1253. u32 ea_entry;
  1254. phys_addr_t addr;
  1255. if (IS_ENABLED(CONFIG_PCI_SRIOV)) {
  1256. /*
  1257. * In the case of a Virtual Function device, device is
  1258. * Physical function, so pdata will point to required VF
  1259. * specific data.
  1260. */
  1261. if (pdata->is_virtfn)
  1262. bar_id += PCI_EA_BEI_VF_BAR0;
  1263. }
  1264. /* EA capability structure header */
  1265. dm_pci_read_config32(dev, ea_off, &ea_entry);
  1266. ea_cnt = (ea_entry >> 16) & PCI_EA_NUM_ENT_MASK;
  1267. ea_off += PCI_EA_FIRST_ENT;
  1268. for (i = 0; i < ea_cnt; i++, ea_off += entry_size) {
  1269. /* Entry header */
  1270. dm_pci_read_config32(dev, ea_off, &ea_entry);
  1271. entry_size = ((ea_entry & PCI_EA_ES) + 1) << 2;
  1272. if (((ea_entry & PCI_EA_BEI) >> 4) != bar_id)
  1273. continue;
  1274. /* Base address, 1st DW */
  1275. dm_pci_read_config32(dev, ea_off + 4, &ea_entry);
  1276. addr = ea_entry & PCI_EA_FIELD_MASK;
  1277. if (ea_entry & PCI_EA_IS_64) {
  1278. /* Base address, 2nd DW, skip over 4B MaxOffset */
  1279. dm_pci_read_config32(dev, ea_off + 12, &ea_entry);
  1280. addr |= ((u64)ea_entry) << 32;
  1281. }
  1282. if (IS_ENABLED(CONFIG_PCI_SRIOV))
  1283. addr += dm_pci_map_ea_virt(dev, ea_off, pdata);
  1284. /* size ignored for now */
  1285. return map_physmem(addr, 0, flags);
  1286. }
  1287. return 0;
  1288. }
  1289. void *dm_pci_map_bar(struct udevice *dev, int bar, int flags)
  1290. {
  1291. struct pci_child_plat *pdata = dev_get_parent_plat(dev);
  1292. struct udevice *udev = dev;
  1293. pci_addr_t pci_bus_addr;
  1294. u32 bar_response;
  1295. int ea_off;
  1296. if (IS_ENABLED(CONFIG_PCI_SRIOV)) {
  1297. /*
  1298. * In case of Virtual Function devices, use PF udevice
  1299. * as EA capability is defined in Physical Function
  1300. */
  1301. if (pdata->is_virtfn)
  1302. udev = pdata->pfdev;
  1303. }
  1304. /*
  1305. * if the function supports Enhanced Allocation use that instead of
  1306. * BARs
  1307. * Incase of virtual functions, pdata will help read VF BEI
  1308. * and EA entry size.
  1309. */
  1310. ea_off = dm_pci_find_capability(udev, PCI_CAP_ID_EA);
  1311. if (ea_off)
  1312. return dm_pci_map_ea_bar(udev, bar, flags, ea_off, pdata);
  1313. /* read BAR address */
  1314. dm_pci_read_config32(udev, bar, &bar_response);
  1315. pci_bus_addr = (pci_addr_t)(bar_response & ~0xf);
  1316. /*
  1317. * Pass "0" as the length argument to pci_bus_to_virt. The arg
  1318. * isn't actually used on any platform because U-Boot assumes a static
  1319. * linear mapping. In the future, this could read the BAR size
  1320. * and pass that as the size if needed.
  1321. */
  1322. return dm_pci_bus_to_virt(udev, pci_bus_addr, flags, 0, MAP_NOCACHE);
  1323. }
  1324. static int _dm_pci_find_next_capability(struct udevice *dev, u8 pos, int cap)
  1325. {
  1326. int ttl = PCI_FIND_CAP_TTL;
  1327. u8 id;
  1328. u16 ent;
  1329. dm_pci_read_config8(dev, pos, &pos);
  1330. while (ttl--) {
  1331. if (pos < PCI_STD_HEADER_SIZEOF)
  1332. break;
  1333. pos &= ~3;
  1334. dm_pci_read_config16(dev, pos, &ent);
  1335. id = ent & 0xff;
  1336. if (id == 0xff)
  1337. break;
  1338. if (id == cap)
  1339. return pos;
  1340. pos = (ent >> 8);
  1341. }
  1342. return 0;
  1343. }
  1344. int dm_pci_find_next_capability(struct udevice *dev, u8 start, int cap)
  1345. {
  1346. return _dm_pci_find_next_capability(dev, start + PCI_CAP_LIST_NEXT,
  1347. cap);
  1348. }
  1349. int dm_pci_find_capability(struct udevice *dev, int cap)
  1350. {
  1351. u16 status;
  1352. u8 header_type;
  1353. u8 pos;
  1354. dm_pci_read_config16(dev, PCI_STATUS, &status);
  1355. if (!(status & PCI_STATUS_CAP_LIST))
  1356. return 0;
  1357. dm_pci_read_config8(dev, PCI_HEADER_TYPE, &header_type);
  1358. if ((header_type & 0x7f) == PCI_HEADER_TYPE_CARDBUS)
  1359. pos = PCI_CB_CAPABILITY_LIST;
  1360. else
  1361. pos = PCI_CAPABILITY_LIST;
  1362. return _dm_pci_find_next_capability(dev, pos, cap);
  1363. }
  1364. int dm_pci_find_next_ext_capability(struct udevice *dev, int start, int cap)
  1365. {
  1366. u32 header;
  1367. int ttl;
  1368. int pos = PCI_CFG_SPACE_SIZE;
  1369. /* minimum 8 bytes per capability */
  1370. ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
  1371. if (start)
  1372. pos = start;
  1373. dm_pci_read_config32(dev, pos, &header);
  1374. /*
  1375. * If we have no capabilities, this is indicated by cap ID,
  1376. * cap version and next pointer all being 0.
  1377. */
  1378. if (header == 0)
  1379. return 0;
  1380. while (ttl--) {
  1381. if (PCI_EXT_CAP_ID(header) == cap)
  1382. return pos;
  1383. pos = PCI_EXT_CAP_NEXT(header);
  1384. if (pos < PCI_CFG_SPACE_SIZE)
  1385. break;
  1386. dm_pci_read_config32(dev, pos, &header);
  1387. }
  1388. return 0;
  1389. }
  1390. int dm_pci_find_ext_capability(struct udevice *dev, int cap)
  1391. {
  1392. return dm_pci_find_next_ext_capability(dev, 0, cap);
  1393. }
  1394. int dm_pci_flr(struct udevice *dev)
  1395. {
  1396. int pcie_off;
  1397. u32 cap;
  1398. /* look for PCI Express Capability */
  1399. pcie_off = dm_pci_find_capability(dev, PCI_CAP_ID_EXP);
  1400. if (!pcie_off)
  1401. return -ENOENT;
  1402. /* check FLR capability */
  1403. dm_pci_read_config32(dev, pcie_off + PCI_EXP_DEVCAP, &cap);
  1404. if (!(cap & PCI_EXP_DEVCAP_FLR))
  1405. return -ENOENT;
  1406. dm_pci_clrset_config16(dev, pcie_off + PCI_EXP_DEVCTL, 0,
  1407. PCI_EXP_DEVCTL_BCR_FLR);
  1408. /* wait 100ms, per PCI spec */
  1409. mdelay(100);
  1410. return 0;
  1411. }
  1412. #if defined(CONFIG_PCI_SRIOV)
  1413. int pci_sriov_init(struct udevice *pdev, int vf_en)
  1414. {
  1415. u16 vendor, device;
  1416. struct udevice *bus;
  1417. struct udevice *dev;
  1418. pci_dev_t bdf;
  1419. u16 ctrl;
  1420. u16 num_vfs;
  1421. u16 total_vf;
  1422. u16 vf_offset;
  1423. u16 vf_stride;
  1424. int vf, ret;
  1425. int pos;
  1426. pos = dm_pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_SRIOV);
  1427. if (!pos) {
  1428. debug("Error: SRIOV capability not found\n");
  1429. return -ENOENT;
  1430. }
  1431. dm_pci_read_config16(pdev, pos + PCI_SRIOV_CTRL, &ctrl);
  1432. dm_pci_read_config16(pdev, pos + PCI_SRIOV_TOTAL_VF, &total_vf);
  1433. if (vf_en > total_vf)
  1434. vf_en = total_vf;
  1435. dm_pci_write_config16(pdev, pos + PCI_SRIOV_NUM_VF, vf_en);
  1436. ctrl |= PCI_SRIOV_CTRL_VFE | PCI_SRIOV_CTRL_MSE;
  1437. dm_pci_write_config16(pdev, pos + PCI_SRIOV_CTRL, ctrl);
  1438. dm_pci_read_config16(pdev, pos + PCI_SRIOV_NUM_VF, &num_vfs);
  1439. if (num_vfs > vf_en)
  1440. num_vfs = vf_en;
  1441. dm_pci_read_config16(pdev, pos + PCI_SRIOV_VF_OFFSET, &vf_offset);
  1442. dm_pci_read_config16(pdev, pos + PCI_SRIOV_VF_STRIDE, &vf_stride);
  1443. dm_pci_read_config16(pdev, PCI_VENDOR_ID, &vendor);
  1444. dm_pci_read_config16(pdev, pos + PCI_SRIOV_VF_DID, &device);
  1445. bdf = dm_pci_get_bdf(pdev);
  1446. pci_get_bus(PCI_BUS(bdf), &bus);
  1447. if (!bus)
  1448. return -ENODEV;
  1449. bdf += PCI_BDF(0, 0, vf_offset);
  1450. for (vf = 0; vf < num_vfs; vf++) {
  1451. struct pci_child_plat *pplat;
  1452. ulong class;
  1453. pci_bus_read_config(bus, bdf, PCI_CLASS_DEVICE,
  1454. &class, PCI_SIZE_16);
  1455. debug("%s: bus %d/%s: found VF %x:%x\n", __func__,
  1456. dev_seq(bus), bus->name, PCI_DEV(bdf), PCI_FUNC(bdf));
  1457. /* Find this device in the device tree */
  1458. ret = pci_bus_find_devfn(bus, PCI_MASK_BUS(bdf), &dev);
  1459. if (ret == -ENODEV) {
  1460. struct pci_device_id find_id;
  1461. memset(&find_id, '\0', sizeof(find_id));
  1462. find_id.vendor = vendor;
  1463. find_id.device = device;
  1464. find_id.class = class;
  1465. ret = pci_find_and_bind_driver(bus, &find_id,
  1466. bdf, &dev);
  1467. if (ret)
  1468. return ret;
  1469. }
  1470. /* Update the platform data */
  1471. pplat = dev_get_parent_plat(dev);
  1472. pplat->devfn = PCI_MASK_BUS(bdf);
  1473. pplat->vendor = vendor;
  1474. pplat->device = device;
  1475. pplat->class = class;
  1476. pplat->is_virtfn = true;
  1477. pplat->pfdev = pdev;
  1478. pplat->virtid = vf * vf_stride + vf_offset;
  1479. debug("%s: bus %d/%s: found VF %x:%x %x:%x class %lx id %x\n",
  1480. __func__, dev_seq(dev), dev->name, PCI_DEV(bdf),
  1481. PCI_FUNC(bdf), vendor, device, class, pplat->virtid);
  1482. bdf += PCI_BDF(0, 0, vf_stride);
  1483. }
  1484. return 0;
  1485. }
  1486. int pci_sriov_get_totalvfs(struct udevice *pdev)
  1487. {
  1488. u16 total_vf;
  1489. int pos;
  1490. pos = dm_pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_SRIOV);
  1491. if (!pos) {
  1492. debug("Error: SRIOV capability not found\n");
  1493. return -ENOENT;
  1494. }
  1495. dm_pci_read_config16(pdev, pos + PCI_SRIOV_TOTAL_VF, &total_vf);
  1496. return total_vf;
  1497. }
  1498. #endif /* SRIOV */
  1499. UCLASS_DRIVER(pci) = {
  1500. .id = UCLASS_PCI,
  1501. .name = "pci",
  1502. .flags = DM_UC_FLAG_SEQ_ALIAS | DM_UC_FLAG_NO_AUTO_SEQ,
  1503. .post_bind = dm_scan_fdt_dev,
  1504. .pre_probe = pci_uclass_pre_probe,
  1505. .post_probe = pci_uclass_post_probe,
  1506. .child_post_bind = pci_uclass_child_post_bind,
  1507. .per_device_auto = sizeof(struct pci_controller),
  1508. .per_child_plat_auto = sizeof(struct pci_child_plat),
  1509. };
  1510. static const struct dm_pci_ops pci_bridge_ops = {
  1511. .read_config = pci_bridge_read_config,
  1512. .write_config = pci_bridge_write_config,
  1513. };
  1514. static const struct udevice_id pci_bridge_ids[] = {
  1515. { .compatible = "pci-bridge" },
  1516. { }
  1517. };
  1518. U_BOOT_DRIVER(pci_bridge_drv) = {
  1519. .name = "pci_bridge_drv",
  1520. .id = UCLASS_PCI,
  1521. .of_match = pci_bridge_ids,
  1522. .ops = &pci_bridge_ops,
  1523. };
  1524. UCLASS_DRIVER(pci_generic) = {
  1525. .id = UCLASS_PCI_GENERIC,
  1526. .name = "pci_generic",
  1527. };
  1528. static const struct udevice_id pci_generic_ids[] = {
  1529. { .compatible = "pci-generic" },
  1530. { }
  1531. };
  1532. U_BOOT_DRIVER(pci_generic_drv) = {
  1533. .name = "pci_generic_drv",
  1534. .id = UCLASS_PCI_GENERIC,
  1535. .of_match = pci_generic_ids,
  1536. };
  1537. int pci_init(void)
  1538. {
  1539. struct udevice *bus;
  1540. /*
  1541. * Enumerate all known controller devices. Enumeration has the side-
  1542. * effect of probing them, so PCIe devices will be enumerated too.
  1543. */
  1544. for (uclass_first_device_check(UCLASS_PCI, &bus);
  1545. bus;
  1546. uclass_next_device_check(&bus)) {
  1547. ;
  1548. }
  1549. return 0;
  1550. }