io.h 8.3 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright (C) 2013-2014, 2020 Synopsys, Inc. All rights reserved.
  4. */
  5. #ifndef __ASM_ARC_IO_H
  6. #define __ASM_ARC_IO_H
  7. #include <linux/types.h>
  8. #include <asm/byteorder.h>
  9. /*
  10. * Compiler barrier. It prevents compiler from reordering instructions before
  11. * and after it. It doesn't prevent HW (CPU) from any reordering though.
  12. */
  13. #define __comp_b() asm volatile("" : : : "memory")
  14. #ifdef __ARCHS__
  15. /*
  16. * ARCv2 based HS38 cores are in-order issue, but still weakly ordered
  17. * due to micro-arch buffering/queuing of load/store, cache hit vs. miss ...
  18. *
  19. * Explicit barrier provided by DMB instruction
  20. * - Operand supports fine grained load/store/load+store semantics
  21. * - Ensures that selected memory operation issued before it will complete
  22. * before any subsequent memory operation of same type
  23. * - DMB guarantees SMP as well as local barrier semantics
  24. * (asm-generic/barrier.h ensures sane smp_*mb if not defined here, i.e.
  25. * UP: barrier(), SMP: smp_*mb == *mb)
  26. * - DSYNC provides DMB+completion_of_cache_bpu_maintenance_ops hence not needed
  27. * in the general case. Plus it only provides full barrier.
  28. */
  29. #define mb() asm volatile("dmb 3\n" : : : "memory")
  30. #define rmb() asm volatile("dmb 1\n" : : : "memory")
  31. #define wmb() asm volatile("dmb 2\n" : : : "memory")
  32. #else
  33. /*
  34. * ARCompact based cores (ARC700) only have SYNC instruction which is super
  35. * heavy weight as it flushes the pipeline as well.
  36. * There are no real SMP implementations of such cores.
  37. */
  38. #define mb() asm volatile("sync\n" : : : "memory")
  39. #endif
  40. #ifdef __ARCHS__
  41. #define __iormb() rmb()
  42. #define __iowmb() wmb()
  43. #else
  44. #define __iormb() __comp_b()
  45. #define __iowmb() __comp_b()
  46. #endif
  47. static inline void sync(void)
  48. {
  49. /* Not yet implemented */
  50. }
  51. /*
  52. * We must use 'volatile' in C-version read/write IO accessors implementation
  53. * to avoid merging several reads (writes) into one read (write), or optimizing
  54. * them out by compiler.
  55. * We must use compiler barriers before and after operation (read or write) so
  56. * it won't be reordered by compiler.
  57. */
  58. #define __arch_getb(a) ({ u8 __v; __comp_b(); __v = *(volatile u8 *)(a); __comp_b(); __v; })
  59. #define __arch_getw(a) ({ u16 __v; __comp_b(); __v = *(volatile u16 *)(a); __comp_b(); __v; })
  60. #define __arch_getl(a) ({ u32 __v; __comp_b(); __v = *(volatile u32 *)(a); __comp_b(); __v; })
  61. #define __arch_getq(a) ({ u64 __v; __comp_b(); __v = *(volatile u64 *)(a); __comp_b(); __v; })
  62. #define __arch_putb(v, a) ({ __comp_b(); *(volatile u8 *)(a) = (v); __comp_b(); })
  63. #define __arch_putw(v, a) ({ __comp_b(); *(volatile u16 *)(a) = (v); __comp_b(); })
  64. #define __arch_putl(v, a) ({ __comp_b(); *(volatile u32 *)(a) = (v); __comp_b(); })
  65. #define __arch_putq(v, a) ({ __comp_b(); *(volatile u64 *)(a) = (v); __comp_b(); })
  66. /*
  67. * We add memory barriers for __raw_readX / __raw_writeX accessors same way as
  68. * it is done for readX and writeX accessors as lots of U-boot driver uses
  69. * __raw_readX / __raw_writeX instead of proper accessor with barrier.
  70. */
  71. #define __raw_writeb(v, c) ({ __iowmb(); __arch_putb(v, c); })
  72. #define __raw_writew(v, c) ({ __iowmb(); __arch_putw(v, c); })
  73. #define __raw_writel(v, c) ({ __iowmb(); __arch_putl(v, c); })
  74. #define __raw_writeq(v, c) ({ __iowmb(); __arch_putq(v, c); })
  75. #define __raw_readb(c) ({ u8 __v = __arch_getb(c); __iormb(); __v; })
  76. #define __raw_readw(c) ({ u16 __v = __arch_getw(c); __iormb(); __v; })
  77. #define __raw_readl(c) ({ u32 __v = __arch_getl(c); __iormb(); __v; })
  78. #define __raw_readq(c) ({ u64 __v = __arch_getq(c); __iormb(); __v; })
  79. static inline void __raw_writesb(unsigned long addr, const void *data,
  80. int bytelen)
  81. {
  82. u8 *buf = (uint8_t *)data;
  83. __iowmb();
  84. while (bytelen--)
  85. __arch_putb(*buf++, addr);
  86. }
  87. static inline void __raw_writesw(unsigned long addr, const void *data,
  88. int wordlen)
  89. {
  90. u16 *buf = (uint16_t *)data;
  91. __iowmb();
  92. while (wordlen--)
  93. __arch_putw(*buf++, addr);
  94. }
  95. static inline void __raw_writesl(unsigned long addr, const void *data,
  96. int longlen)
  97. {
  98. u32 *buf = (uint32_t *)data;
  99. __iowmb();
  100. while (longlen--)
  101. __arch_putl(*buf++, addr);
  102. }
  103. static inline void __raw_readsb(unsigned long addr, void *data, int bytelen)
  104. {
  105. u8 *buf = (uint8_t *)data;
  106. while (bytelen--)
  107. *buf++ = __arch_getb(addr);
  108. __iormb();
  109. }
  110. static inline void __raw_readsw(unsigned long addr, void *data, int wordlen)
  111. {
  112. u16 *buf = (uint16_t *)data;
  113. while (wordlen--)
  114. *buf++ = __arch_getw(addr);
  115. __iormb();
  116. }
  117. static inline void __raw_readsl(unsigned long addr, void *data, int longlen)
  118. {
  119. u32 *buf = (uint32_t *)data;
  120. while (longlen--)
  121. *buf++ = __arch_getl(addr);
  122. __iormb();
  123. }
  124. /*
  125. * Relaxed I/O memory access primitives. These follow the Device memory
  126. * ordering rules but do not guarantee any ordering relative to Normal memory
  127. * accesses.
  128. */
  129. #define readb_relaxed(c) ({ u8 __r = __arch_getb(c); __r; })
  130. #define readw_relaxed(c) ({ u16 __r = le16_to_cpu((__force __le16)__arch_getw(c)); __r; })
  131. #define readl_relaxed(c) ({ u32 __r = le32_to_cpu((__force __le32)__arch_getl(c)); __r; })
  132. #define readq_relaxed(c) ({ u64 __r = le64_to_cpu((__force __le64)__arch_getq(c)); __r; })
  133. #define writeb_relaxed(v, c) ((void)__arch_putb((v), (c)))
  134. #define writew_relaxed(v, c) ((void)__arch_putw((__force u16)cpu_to_le16(v), (c)))
  135. #define writel_relaxed(v, c) ((void)__arch_putl((__force u32)cpu_to_le32(v), (c)))
  136. #define writeq_relaxed(v, c) ((void)__arch_putq((__force u64)cpu_to_le64(v), (c)))
  137. /*
  138. * MMIO can also get buffered/optimized in micro-arch, so barriers needed
  139. * Based on ARM model for the typical use case
  140. *
  141. * <ST [DMA buffer]>
  142. * <writel MMIO "go" reg>
  143. * or:
  144. * <readl MMIO "status" reg>
  145. * <LD [DMA buffer]>
  146. *
  147. * http://lkml.kernel.org/r/20150622133656.GG1583@arm.com
  148. */
  149. #define readb(c) ({ u8 __v = readb_relaxed(c); __iormb(); __v; })
  150. #define readw(c) ({ u16 __v = readw_relaxed(c); __iormb(); __v; })
  151. #define readl(c) ({ u32 __v = readl_relaxed(c); __iormb(); __v; })
  152. #define readq(c) ({ u64 __v = readq_relaxed(c); __iormb(); __v; })
  153. #define writeb(v, c) ({ __iowmb(); writeb_relaxed(v, c); })
  154. #define writew(v, c) ({ __iowmb(); writew_relaxed(v, c); })
  155. #define writel(v, c) ({ __iowmb(); writel_relaxed(v, c); })
  156. #define writeq(v, c) ({ __iowmb(); writeq_relaxed(v, c); })
  157. #define out_arch(type, endian, a, v) __raw_write##type(cpu_to_##endian(v), a)
  158. #define in_arch(type, endian, a) endian##_to_cpu(__raw_read##type(a))
  159. #define out_le32(a, v) out_arch(l, le32, a, v)
  160. #define out_le16(a, v) out_arch(w, le16, a, v)
  161. #define in_le32(a) in_arch(l, le32, a)
  162. #define in_le16(a) in_arch(w, le16, a)
  163. #define out_be32(a, v) out_arch(l, be32, a, v)
  164. #define out_be16(a, v) out_arch(w, be16, a, v)
  165. #define in_be32(a) in_arch(l, be32, a)
  166. #define in_be16(a) in_arch(w, be16, a)
  167. #define out_8(a, v) __raw_writeb(v, a)
  168. #define in_8(a) __raw_readb(a)
  169. /*
  170. * Clear and set bits in one shot. These macros can be used to clear and
  171. * set multiple bits in a register using a single call. These macros can
  172. * also be used to set a multiple-bit bit pattern using a mask, by
  173. * specifying the mask in the 'clear' parameter and the new bit pattern
  174. * in the 'set' parameter.
  175. */
  176. #define clrbits(type, addr, clear) \
  177. out_##type((addr), in_##type(addr) & ~(clear))
  178. #define setbits(type, addr, set) \
  179. out_##type((addr), in_##type(addr) | (set))
  180. #define clrsetbits(type, addr, clear, set) \
  181. out_##type((addr), (in_##type(addr) & ~(clear)) | (set))
  182. #define clrbits_be32(addr, clear) clrbits(be32, addr, clear)
  183. #define setbits_be32(addr, set) setbits(be32, addr, set)
  184. #define clrsetbits_be32(addr, clear, set) clrsetbits(be32, addr, clear, set)
  185. #define clrbits_le32(addr, clear) clrbits(le32, addr, clear)
  186. #define setbits_le32(addr, set) setbits(le32, addr, set)
  187. #define clrsetbits_le32(addr, clear, set) clrsetbits(le32, addr, clear, set)
  188. #define clrbits_be16(addr, clear) clrbits(be16, addr, clear)
  189. #define setbits_be16(addr, set) setbits(be16, addr, set)
  190. #define clrsetbits_be16(addr, clear, set) clrsetbits(be16, addr, clear, set)
  191. #define clrbits_le16(addr, clear) clrbits(le16, addr, clear)
  192. #define setbits_le16(addr, set) setbits(le16, addr, set)
  193. #define clrsetbits_le16(addr, clear, set) clrsetbits(le16, addr, clear, set)
  194. #define clrbits_8(addr, clear) clrbits(8, addr, clear)
  195. #define setbits_8(addr, set) setbits(8, addr, set)
  196. #define clrsetbits_8(addr, clear, set) clrsetbits(8, addr, clear, set)
  197. #include <asm-generic/io.h>
  198. #endif /* __ASM_ARC_IO_H */