omap-cache.c 1.7 KB

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  1. /*
  2. *
  3. * Common functions for OMAP4/5 based boards
  4. *
  5. * (C) Copyright 2010
  6. * Texas Instruments, <www.ti.com>
  7. *
  8. * Author :
  9. * Aneesh V <aneesh@ti.com>
  10. * Steve Sakoman <steve@sakoman.com>
  11. *
  12. * SPDX-License-Identifier: GPL-2.0+
  13. */
  14. #include <common.h>
  15. #include <asm/cache.h>
  16. DECLARE_GLOBAL_DATA_PTR;
  17. /*
  18. * Without LPAE short descriptors are used
  19. * Set C - Cache Bit3
  20. * Set B - Buffer Bit2
  21. * The last 2 bits set to 0b10
  22. * Do Not set XN bit4
  23. * So value is 0xe
  24. *
  25. * With LPAE cache configuration happens via MAIR0 register
  26. * AttrIndx value is 0x3 for picking byte3 for MAIR0 which has 0xFF.
  27. * 0xFF maps to Cache writeback with Read and Write Allocate set
  28. * The bits[1:0] should have the value 0b01 for the first level
  29. * descriptor.
  30. * So the value is 0xd
  31. */
  32. #ifdef CONFIG_ARMV7_LPAE
  33. #define ARMV7_DCACHE_POLICY DCACHE_WRITEALLOC
  34. #else
  35. #define ARMV7_DCACHE_POLICY DCACHE_WRITEBACK & ~TTB_SECT_XN_MASK
  36. #endif
  37. #define ARMV7_DOMAIN_CLIENT 1
  38. #define ARMV7_DOMAIN_MASK (0x3 << 0)
  39. void enable_caches(void)
  40. {
  41. /* Enable I cache if not enabled */
  42. if (!icache_status())
  43. icache_enable();
  44. dcache_enable();
  45. }
  46. void dram_bank_mmu_setup(int bank)
  47. {
  48. bd_t *bd = gd->bd;
  49. int i;
  50. u32 start = bd->bi_dram[bank].start >> MMU_SECTION_SHIFT;
  51. u32 size = bd->bi_dram[bank].size >> MMU_SECTION_SHIFT;
  52. u32 end = start + size;
  53. debug("%s: bank: %d\n", __func__, bank);
  54. for (i = start; i < end; i++)
  55. set_section_dcache(i, ARMV7_DCACHE_POLICY);
  56. }
  57. void arm_init_domains(void)
  58. {
  59. u32 reg;
  60. reg = get_dacr();
  61. /*
  62. * Set DOMAIN to client access so that all permissions
  63. * set in pagetables are validated by the mmu.
  64. */
  65. reg &= ~ARMV7_DOMAIN_MASK;
  66. reg |= ARMV7_DOMAIN_CLIENT;
  67. set_dacr(reg);
  68. }