socfpga_n5x_socdk.h 1.5 KB

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  1. /* SPDX-License-Identifier: GPL-2.0
  2. *
  3. * Copyright (C) 2020-2021 Intel Corporation <www.intel.com>
  4. *
  5. */
  6. #ifndef __CONFIG_SOCFGPA_N5X_H__
  7. #define __CONFIG_SOCFGPA_N5X_H__
  8. #include <configs/socfpga_soc64_common.h>
  9. #undef CONFIG_EXTRA_ENV_SETTINGS
  10. #define CONFIG_EXTRA_ENV_SETTINGS \
  11. "loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
  12. "bootfile=" CONFIG_BOOTFILE "\0" \
  13. "fdt_addr=1100000\0" \
  14. "fdtimage=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \
  15. "mmcroot=/dev/mmcblk0p2\0" \
  16. "mmcboot=setenv bootargs " CONFIG_BOOTARGS \
  17. " root=${mmcroot} rw rootwait;" \
  18. "booti ${loadaddr} - ${fdt_addr}\0" \
  19. "mmcload=mmc rescan;" \
  20. "load mmc 0:1 ${loadaddr} ${bootfile};" \
  21. "load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \
  22. "mmcfitboot=setenv bootargs " CONFIG_BOOTARGS \
  23. " root=${mmcroot} rw rootwait;" \
  24. "bootm ${loadaddr}\0" \
  25. "mmcfitload=mmc rescan;" \
  26. "load mmc 0:1 ${loadaddr} ${bootfile}\0" \
  27. "ramboot=setenv bootargs " CONFIG_BOOTARGS";" \
  28. "booti ${loadaddr} - ${fdt_addr}\0" \
  29. "linux_qspi_enable=if sf probe; then " \
  30. "echo Enabling QSPI at Linux DTB...;" \
  31. "fdt addr ${fdt_addr}; fdt resize;" \
  32. "fdt set /soc/spi@ff8d2000 status okay;" \
  33. "if fdt set /soc/clocks/qspi-clk clock-frequency" \
  34. " ${qspi_clock}; then" \
  35. " else fdt set /soc/clkmgr/clocks/qspi_clk clock-frequency" \
  36. " ${qspi_clock}; fi; fi\0" \
  37. "scriptaddr=0x02100000\0" \
  38. "scriptfile=u-boot.scr\0" \
  39. "fatscript=if fatload mmc 0:1 ${scriptaddr} ${scriptfile};" \
  40. "then source ${scriptaddr}; fi\0"
  41. #endif /* __CONFIG_SOCFGPA_N5X_H__ */