clk-n5x.c 13 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (C) 2020-2021 Intel Corporation <www.intel.com>
  4. */
  5. #include <common.h>
  6. #include <asm/arch/clock_manager.h>
  7. #include <asm/global_data.h>
  8. #include <asm/io.h>
  9. #include <clk-uclass.h>
  10. #include <dm.h>
  11. #include <dm/lists.h>
  12. #include <dm/util.h>
  13. #include <dt-bindings/clock/n5x-clock.h>
  14. DECLARE_GLOBAL_DATA_PTR;
  15. struct socfpga_clk_plat {
  16. void __iomem *regs;
  17. };
  18. /*
  19. * function to write the bypass register which requires a poll of the
  20. * busy bit
  21. */
  22. static void clk_write_bypass_mainpll(struct socfpga_clk_plat *plat, u32 val)
  23. {
  24. CM_REG_WRITEL(plat, val, CLKMGR_MAINPLL_BYPASS);
  25. cm_wait_for_fsm();
  26. }
  27. static void clk_write_bypass_perpll(struct socfpga_clk_plat *plat, u32 val)
  28. {
  29. CM_REG_WRITEL(plat, val, CLKMGR_PERPLL_BYPASS);
  30. cm_wait_for_fsm();
  31. }
  32. /* function to write the ctrl register which requires a poll of the busy bit */
  33. static void clk_write_ctrl(struct socfpga_clk_plat *plat, u32 val)
  34. {
  35. CM_REG_WRITEL(plat, val, CLKMGR_CTRL);
  36. cm_wait_for_fsm();
  37. }
  38. /*
  39. * Setup clocks while making no assumptions about previous state of the clocks.
  40. */
  41. static void clk_basic_init(struct udevice *dev,
  42. const struct cm_config * const cfg)
  43. {
  44. struct socfpga_clk_plat *plat = dev_get_plat(dev);
  45. if (!cfg)
  46. return;
  47. #if IS_ENABLED(CONFIG_SPL_BUILD)
  48. /* Always force clock manager into boot mode before any configuration */
  49. clk_write_ctrl(plat,
  50. CM_REG_READL(plat, CLKMGR_CTRL) | CLKMGR_CTRL_BOOTMODE);
  51. #else
  52. /* Skip clock configuration in SSBL if it's not in boot mode */
  53. if (!(CM_REG_READL(plat, CLKMGR_CTRL) & CLKMGR_CTRL_BOOTMODE))
  54. return;
  55. #endif
  56. /* Put both PLLs in bypass */
  57. clk_write_bypass_mainpll(plat, CLKMGR_BYPASS_MAINPLL_ALL);
  58. clk_write_bypass_perpll(plat, CLKMGR_BYPASS_PERPLL_ALL);
  59. /* Put both PLLs in Reset */
  60. CM_REG_SETBITS(plat, CLKMGR_MAINPLL_PLLCTRL,
  61. CLKMGR_PLLCTRL_BYPASS_MASK);
  62. CM_REG_SETBITS(plat, CLKMGR_PERPLL_PLLCTRL,
  63. CLKMGR_PLLCTRL_BYPASS_MASK);
  64. /* setup main PLL */
  65. CM_REG_WRITEL(plat, cfg->main_pll_pllglob, CLKMGR_MAINPLL_PLLGLOB);
  66. CM_REG_WRITEL(plat, cfg->main_pll_plldiv, CLKMGR_MAINPLL_PLLDIV);
  67. CM_REG_WRITEL(plat, cfg->main_pll_plloutdiv, CLKMGR_MAINPLL_PLLOUTDIV);
  68. CM_REG_WRITEL(plat, cfg->main_pll_mpuclk, CLKMGR_MAINPLL_MPUCLK);
  69. CM_REG_WRITEL(plat, cfg->main_pll_nocclk, CLKMGR_MAINPLL_NOCCLK);
  70. CM_REG_WRITEL(plat, cfg->main_pll_nocdiv, CLKMGR_MAINPLL_NOCDIV);
  71. /* setup peripheral */
  72. CM_REG_WRITEL(plat, cfg->per_pll_pllglob, CLKMGR_PERPLL_PLLGLOB);
  73. CM_REG_WRITEL(plat, cfg->per_pll_plldiv, CLKMGR_PERPLL_PLLDIV);
  74. CM_REG_WRITEL(plat, cfg->per_pll_plloutdiv, CLKMGR_PERPLL_PLLOUTDIV);
  75. CM_REG_WRITEL(plat, cfg->per_pll_emacctl, CLKMGR_PERPLL_EMACCTL);
  76. CM_REG_WRITEL(plat, cfg->per_pll_gpiodiv, CLKMGR_PERPLL_GPIODIV);
  77. /* Take both PLL out of reset and power up */
  78. CM_REG_CLRBITS(plat, CLKMGR_MAINPLL_PLLCTRL,
  79. CLKMGR_PLLCTRL_BYPASS_MASK);
  80. CM_REG_CLRBITS(plat, CLKMGR_PERPLL_PLLCTRL,
  81. CLKMGR_PLLCTRL_BYPASS_MASK);
  82. cm_wait_for_lock(CLKMGR_STAT_ALLPLL_LOCKED_MASK);
  83. CM_REG_WRITEL(plat, cfg->alt_emacactr, CLKMGR_ALTR_EMACACTR);
  84. CM_REG_WRITEL(plat, cfg->alt_emacbctr, CLKMGR_ALTR_EMACBCTR);
  85. CM_REG_WRITEL(plat, cfg->alt_emacptpctr, CLKMGR_ALTR_EMACPTPCTR);
  86. CM_REG_WRITEL(plat, cfg->alt_gpiodbctr, CLKMGR_ALTR_GPIODBCTR);
  87. CM_REG_WRITEL(plat, cfg->alt_sdmmcctr, CLKMGR_ALTR_SDMMCCTR);
  88. CM_REG_WRITEL(plat, cfg->alt_s2fuser0ctr, CLKMGR_ALTR_S2FUSER0CTR);
  89. CM_REG_WRITEL(plat, cfg->alt_s2fuser1ctr, CLKMGR_ALTR_S2FUSER1CTR);
  90. CM_REG_WRITEL(plat, cfg->alt_psirefctr, CLKMGR_ALTR_PSIREFCTR);
  91. /* Configure ping pong counters in altera group */
  92. CM_REG_WRITEL(plat, CLKMGR_LOSTLOCK_SET_MASK, CLKMGR_MAINPLL_LOSTLOCK);
  93. CM_REG_WRITEL(plat, CLKMGR_LOSTLOCK_SET_MASK, CLKMGR_PERPLL_LOSTLOCK);
  94. CM_REG_WRITEL(plat, CM_REG_READL(plat, CLKMGR_MAINPLL_PLLGLOB) |
  95. CLKMGR_PLLGLOB_CLR_LOSTLOCK_BYPASS_MASK,
  96. CLKMGR_MAINPLL_PLLGLOB);
  97. CM_REG_WRITEL(plat, CM_REG_READL(plat, CLKMGR_PERPLL_PLLGLOB) |
  98. CLKMGR_PLLGLOB_CLR_LOSTLOCK_BYPASS_MASK,
  99. CLKMGR_PERPLL_PLLGLOB);
  100. /* Take all PLLs out of bypass */
  101. clk_write_bypass_mainpll(plat, 0);
  102. clk_write_bypass_perpll(plat, 0);
  103. /* Clear the loss of lock bits */
  104. CM_REG_CLRBITS(plat, CLKMGR_INTRCLR,
  105. CLKMGR_INTER_PERPLLLOST_MASK |
  106. CLKMGR_INTER_MAINPLLLOST_MASK);
  107. /* Take all ping pong counters out of reset */
  108. CM_REG_CLRBITS(plat, CLKMGR_ALTR_EXTCNTRST,
  109. CLKMGR_ALT_EXTCNTRST_ALLCNTRST_MASK);
  110. /* Out of boot mode */
  111. clk_write_ctrl(plat,
  112. CM_REG_READL(plat, CLKMGR_CTRL) & ~CLKMGR_CTRL_BOOTMODE);
  113. }
  114. static u32 clk_get_5_1_clk_src(struct socfpga_clk_plat *plat, u32 reg)
  115. {
  116. u32 clksrc = CM_REG_READL(plat, reg);
  117. return (clksrc & CLKMGR_CLKSRC_MASK) >> CLKMGR_CLKSRC_OFFSET;
  118. }
  119. static u64 clk_get_pll_output_hz(struct socfpga_clk_plat *plat,
  120. u32 pllglob_reg, u32 plldiv_reg)
  121. {
  122. u64 clock = 0;
  123. u32 clklsrc, divf, divr, divq, power = 1;
  124. /* Get input clock frequency */
  125. clklsrc = (CM_REG_READL(plat, pllglob_reg) &
  126. CLKMGR_PLLGLOB_VCO_PSRC_MASK) >>
  127. CLKMGR_PLLGLOB_VCO_PSRC_OFFSET;
  128. switch (clklsrc) {
  129. case CLKMGR_VCO_PSRC_EOSC1:
  130. clock = cm_get_osc_clk_hz();
  131. break;
  132. case CLKMGR_VCO_PSRC_INTOSC:
  133. clock = cm_get_intosc_clk_hz();
  134. break;
  135. case CLKMGR_VCO_PSRC_F2S:
  136. clock = cm_get_fpga_clk_hz();
  137. break;
  138. }
  139. /* Calculate pll out clock frequency */
  140. divf = (CM_REG_READL(plat, plldiv_reg) &
  141. CLKMGR_PLLDIV_FDIV_MASK) >>
  142. CLKMGR_PLLDIV_FDIV_OFFSET;
  143. divr = (CM_REG_READL(plat, plldiv_reg) &
  144. CLKMGR_PLLDIV_REFCLKDIV_MASK) >>
  145. CLKMGR_PLLDIV_REFCLKDIV_OFFSET;
  146. divq = (CM_REG_READL(plat, plldiv_reg) &
  147. CLKMGR_PLLDIV_OUTDIV_QDIV_MASK) >>
  148. CLKMGR_PLLDIV_OUTDIV_QDIV_OFFSET;
  149. while (divq) {
  150. power *= 2;
  151. divq--;
  152. }
  153. return (clock * 2 * (divf + 1)) / ((divr + 1) * power);
  154. }
  155. static u64 clk_get_clksrc_hz(struct socfpga_clk_plat *plat, u32 clksrc_reg,
  156. u32 main_div, u32 per_div)
  157. {
  158. u64 clock = 0;
  159. u32 clklsrc = clk_get_5_1_clk_src(plat, clksrc_reg);
  160. switch (clklsrc) {
  161. case CLKMGR_CLKSRC_MAIN:
  162. clock = clk_get_pll_output_hz(plat,
  163. CLKMGR_MAINPLL_PLLGLOB,
  164. CLKMGR_MAINPLL_PLLDIV);
  165. clock /= 1 + main_div;
  166. break;
  167. case CLKMGR_CLKSRC_PER:
  168. clock = clk_get_pll_output_hz(plat,
  169. CLKMGR_PERPLL_PLLGLOB,
  170. CLKMGR_PERPLL_PLLDIV);
  171. clock /= 1 + per_div;
  172. break;
  173. case CLKMGR_CLKSRC_OSC1:
  174. clock = cm_get_osc_clk_hz();
  175. break;
  176. case CLKMGR_CLKSRC_INTOSC:
  177. clock = cm_get_intosc_clk_hz();
  178. break;
  179. case CLKMGR_CLKSRC_FPGA:
  180. clock = cm_get_fpga_clk_hz();
  181. break;
  182. default:
  183. return 0;
  184. }
  185. return clock;
  186. }
  187. static u64 clk_get_mpu_clk_hz(struct socfpga_clk_plat *plat)
  188. {
  189. u32 mainpll_c0cnt = (CM_REG_READL(plat, CLKMGR_MAINPLL_PLLOUTDIV) &
  190. CLKMGR_PLLOUTDIV_C0CNT_MASK) >>
  191. CLKMGR_PLLOUTDIV_C0CNT_OFFSET;
  192. u32 perpll_c0cnt = (CM_REG_READL(plat, CLKMGR_PERPLL_PLLOUTDIV) &
  193. CLKMGR_PLLOUTDIV_C0CNT_MASK) >>
  194. CLKMGR_PLLOUTDIV_C0CNT_OFFSET;
  195. u64 clock = clk_get_clksrc_hz(plat, CLKMGR_MAINPLL_MPUCLK,
  196. mainpll_c0cnt, perpll_c0cnt);
  197. clock /= 1 + (CM_REG_READL(plat, CLKMGR_MAINPLL_MPUCLK) &
  198. CLKMGR_CLKCNT_MSK);
  199. return clock;
  200. }
  201. static u32 clk_get_l3_main_clk_hz(struct socfpga_clk_plat *plat)
  202. {
  203. u32 mainpll_c1cnt = (CM_REG_READL(plat, CLKMGR_MAINPLL_PLLOUTDIV) &
  204. CLKMGR_PLLOUTDIV_C1CNT_MASK) >>
  205. CLKMGR_PLLOUTDIV_C1CNT_OFFSET;
  206. u32 perpll_c1cnt = (CM_REG_READL(plat, CLKMGR_PERPLL_PLLOUTDIV) &
  207. CLKMGR_PLLOUTDIV_C1CNT_MASK) >>
  208. CLKMGR_PLLOUTDIV_C1CNT_OFFSET;
  209. return clk_get_clksrc_hz(plat, CLKMGR_MAINPLL_NOCCLK,
  210. mainpll_c1cnt, perpll_c1cnt);
  211. }
  212. static u32 clk_get_l4_main_clk_hz(struct socfpga_clk_plat *plat)
  213. {
  214. u64 clock = clk_get_l3_main_clk_hz(plat);
  215. clock /= BIT((CM_REG_READL(plat, CLKMGR_MAINPLL_NOCDIV) >>
  216. CLKMGR_NOCDIV_L4MAIN_OFFSET) &
  217. CLKMGR_NOCDIV_DIVIDER_MASK);
  218. return clock;
  219. }
  220. static u32 clk_get_sdmmc_clk_hz(struct socfpga_clk_plat *plat)
  221. {
  222. u32 mainpll_c3cnt = (CM_REG_READL(plat, CLKMGR_MAINPLL_PLLOUTDIV) &
  223. CLKMGR_PLLOUTDIV_C3CNT_MASK) >>
  224. CLKMGR_PLLOUTDIV_C3CNT_OFFSET;
  225. u32 perpll_c3cnt = (CM_REG_READL(plat, CLKMGR_PERPLL_PLLOUTDIV) &
  226. CLKMGR_PLLOUTDIV_C3CNT_MASK) >>
  227. CLKMGR_PLLOUTDIV_C3CNT_OFFSET;
  228. u64 clock = clk_get_clksrc_hz(plat, CLKMGR_ALTR_SDMMCCTR,
  229. mainpll_c3cnt, perpll_c3cnt);
  230. clock /= 1 + (CM_REG_READL(plat, CLKMGR_ALTR_SDMMCCTR) &
  231. CLKMGR_CLKCNT_MSK);
  232. return clock / 4;
  233. }
  234. static u32 clk_get_l4_sp_clk_hz(struct socfpga_clk_plat *plat)
  235. {
  236. u64 clock = clk_get_l3_main_clk_hz(plat);
  237. clock /= BIT((CM_REG_READL(plat, CLKMGR_MAINPLL_NOCDIV) >>
  238. CLKMGR_NOCDIV_L4SPCLK_OFFSET) &
  239. CLKMGR_NOCDIV_DIVIDER_MASK);
  240. return clock;
  241. }
  242. static u32 clk_get_l4_mp_clk_hz(struct socfpga_clk_plat *plat)
  243. {
  244. u64 clock = clk_get_l3_main_clk_hz(plat);
  245. clock /= BIT((CM_REG_READL(plat, CLKMGR_MAINPLL_NOCDIV) >>
  246. CLKMGR_NOCDIV_L4MPCLK_OFFSET) &
  247. CLKMGR_NOCDIV_DIVIDER_MASK);
  248. return clock;
  249. }
  250. static u32 clk_get_l4_sys_free_clk_hz(struct socfpga_clk_plat *plat)
  251. {
  252. if (CM_REG_READL(plat, CLKMGR_STAT) & CLKMGR_STAT_BOOTMODE)
  253. return clk_get_l3_main_clk_hz(plat) / 2;
  254. return clk_get_l3_main_clk_hz(plat) / 4;
  255. }
  256. static u32 clk_get_emac_clk_hz(struct socfpga_clk_plat *plat, u32 emac_id)
  257. {
  258. bool emacsel_a;
  259. u32 ctl;
  260. u32 ctr_reg;
  261. u32 clock;
  262. u32 div;
  263. u32 reg;
  264. /* Get EMAC clock source */
  265. ctl = CM_REG_READL(plat, CLKMGR_PERPLL_EMACCTL);
  266. if (emac_id == N5X_EMAC0_CLK)
  267. ctl = (ctl >> CLKMGR_PERPLLGRP_EMACCTL_EMAC0SELB_OFFSET) &
  268. CLKMGR_PERPLLGRP_EMACCTL_EMAC0SELB_MASK;
  269. else if (emac_id == N5X_EMAC1_CLK)
  270. ctl = (ctl >> CLKMGR_PERPLLGRP_EMACCTL_EMAC1SELB_OFFSET) &
  271. CLKMGR_PERPLLGRP_EMACCTL_EMAC1SELB_MASK;
  272. else if (emac_id == N5X_EMAC2_CLK)
  273. ctl = (ctl >> CLKMGR_PERPLLGRP_EMACCTL_EMAC2SELB_OFFSET) &
  274. CLKMGR_PERPLLGRP_EMACCTL_EMAC2SELB_MASK;
  275. else
  276. return 0;
  277. if (ctl) {
  278. /* EMAC B source */
  279. emacsel_a = false;
  280. ctr_reg = CLKMGR_ALTR_EMACBCTR;
  281. } else {
  282. /* EMAC A source */
  283. emacsel_a = true;
  284. ctr_reg = CLKMGR_ALTR_EMACACTR;
  285. }
  286. reg = CM_REG_READL(plat, ctr_reg);
  287. clock = (reg & CLKMGR_ALT_EMACCTR_SRC_MASK)
  288. >> CLKMGR_ALT_EMACCTR_SRC_OFFSET;
  289. div = (reg & CLKMGR_ALT_EMACCTR_CNT_MASK)
  290. >> CLKMGR_ALT_EMACCTR_CNT_OFFSET;
  291. switch (clock) {
  292. case CLKMGR_CLKSRC_MAIN:
  293. clock = clk_get_pll_output_hz(plat,
  294. CLKMGR_MAINPLL_PLLGLOB,
  295. CLKMGR_MAINPLL_PLLDIV);
  296. if (emacsel_a) {
  297. clock /= 1 + ((CM_REG_READL(plat,
  298. CLKMGR_MAINPLL_PLLOUTDIV) &
  299. CLKMGR_PLLOUTDIV_C2CNT_MASK) >>
  300. CLKMGR_PLLOUTDIV_C2CNT_OFFSET);
  301. } else {
  302. clock /= 1 + ((CM_REG_READL(plat,
  303. CLKMGR_MAINPLL_PLLOUTDIV) &
  304. CLKMGR_PLLOUTDIV_C3CNT_MASK) >>
  305. CLKMGR_PLLOUTDIV_C3CNT_OFFSET);
  306. }
  307. break;
  308. case CLKMGR_CLKSRC_PER:
  309. clock = clk_get_pll_output_hz(plat,
  310. CLKMGR_PERPLL_PLLGLOB,
  311. CLKMGR_PERPLL_PLLDIV);
  312. if (emacsel_a) {
  313. clock /= 1 + ((CM_REG_READL(plat,
  314. CLKMGR_PERPLL_PLLOUTDIV) &
  315. CLKMGR_PLLOUTDIV_C2CNT_MASK) >>
  316. CLKMGR_PLLOUTDIV_C2CNT_OFFSET);
  317. } else {
  318. clock /= 1 + ((CM_REG_READL(plat,
  319. CLKMGR_PERPLL_PLLOUTDIV) &
  320. CLKMGR_PLLOUTDIV_C3CNT_MASK >>
  321. CLKMGR_PLLOUTDIV_C3CNT_OFFSET));
  322. }
  323. break;
  324. case CLKMGR_CLKSRC_OSC1:
  325. clock = cm_get_osc_clk_hz();
  326. break;
  327. case CLKMGR_CLKSRC_INTOSC:
  328. clock = cm_get_intosc_clk_hz();
  329. break;
  330. case CLKMGR_CLKSRC_FPGA:
  331. clock = cm_get_fpga_clk_hz();
  332. break;
  333. }
  334. clock /= 1 + div;
  335. return clock;
  336. }
  337. static ulong socfpga_clk_get_rate(struct clk *clk)
  338. {
  339. struct socfpga_clk_plat *plat = dev_get_plat(clk->dev);
  340. switch (clk->id) {
  341. case N5X_MPU_CLK:
  342. return clk_get_mpu_clk_hz(plat);
  343. case N5X_L4_MAIN_CLK:
  344. return clk_get_l4_main_clk_hz(plat);
  345. case N5X_L4_SYS_FREE_CLK:
  346. return clk_get_l4_sys_free_clk_hz(plat);
  347. case N5X_L4_MP_CLK:
  348. return clk_get_l4_mp_clk_hz(plat);
  349. case N5X_L4_SP_CLK:
  350. return clk_get_l4_sp_clk_hz(plat);
  351. case N5X_SDMMC_CLK:
  352. return clk_get_sdmmc_clk_hz(plat);
  353. case N5X_EMAC0_CLK:
  354. case N5X_EMAC1_CLK:
  355. case N5X_EMAC2_CLK:
  356. return clk_get_emac_clk_hz(plat, clk->id);
  357. case N5X_USB_CLK:
  358. case N5X_NAND_X_CLK:
  359. return clk_get_l4_mp_clk_hz(plat);
  360. case N5X_NAND_CLK:
  361. return clk_get_l4_mp_clk_hz(plat) / 4;
  362. default:
  363. return -ENXIO;
  364. }
  365. }
  366. static int socfpga_clk_enable(struct clk *clk)
  367. {
  368. return 0;
  369. }
  370. static int socfpga_clk_probe(struct udevice *dev)
  371. {
  372. const struct cm_config *cm_default_cfg = cm_get_default_config();
  373. clk_basic_init(dev, cm_default_cfg);
  374. return 0;
  375. }
  376. static int socfpga_clk_of_to_plat(struct udevice *dev)
  377. {
  378. struct socfpga_clk_plat *plat = dev_get_plat(dev);
  379. fdt_addr_t addr;
  380. addr = devfdt_get_addr(dev);
  381. if (addr == FDT_ADDR_T_NONE)
  382. return -EINVAL;
  383. plat->regs = (void __iomem *)addr;
  384. return 0;
  385. }
  386. static struct clk_ops socfpga_clk_ops = {
  387. .enable = socfpga_clk_enable,
  388. .get_rate = socfpga_clk_get_rate,
  389. };
  390. static const struct udevice_id socfpga_clk_match[] = {
  391. { .compatible = "intel,n5x-clkmgr" },
  392. {}
  393. };
  394. U_BOOT_DRIVER(socfpga_n5x_clk) = {
  395. .name = "clk-n5x",
  396. .id = UCLASS_CLK,
  397. .of_match = socfpga_clk_match,
  398. .ops = &socfpga_clk_ops,
  399. .probe = socfpga_clk_probe,
  400. .of_to_plat = socfpga_clk_of_to_plat,
  401. .plat_auto = sizeof(struct socfpga_clk_plat),
  402. };