clk-mem-n5x.h 2.6 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * Copyright (C) 2020-2021 Intel Corporation <www.intel.com>
  4. */
  5. #ifndef _CLK_MEM_N5X_
  6. #define _CLK_MEM_N5X_
  7. #ifndef __ASSEMBLY__
  8. #include <linux/bitops.h>
  9. #endif
  10. /* Clock Manager registers */
  11. #define MEMCLKMGR_STAT 4
  12. #define MEMCLKMGR_INTRGEN 8
  13. #define MEMCLKMGR_INTRMSK 0x0c
  14. #define MEMCLKMGR_INTRCLR 0x10
  15. #define MEMCLKMGR_INTRSTS 0x14
  16. #define MEMCLKMGR_INTRSTK 0x18
  17. #define MEMCLKMGR_INTRRAW 0x1c
  18. /* Memory Clock Manager PPL group registers */
  19. #define MEMCLKMGR_MEMPLL_EN 0x20
  20. #define MEMCLKMGR_MEMPLL_ENS 0x24
  21. #define MEMCLKMGR_MEMPLL_ENR 0x28
  22. #define MEMCLKMGR_MEMPLL_BYPASS 0x2c
  23. #define MEMCLKMGR_MEMPLL_BYPASSS 0x30
  24. #define MEMCLKMGR_MEMPLL_BYPASSR 0x34
  25. #define MEMCLKMGR_MEMPLL_MEMDIV 0x38
  26. #define MEMCLKMGR_MEMPLL_PLLGLOB 0x3c
  27. #define MEMCLKMGR_MEMPLL_PLLCTRL 0x40
  28. #define MEMCLKMGR_MEMPLL_PLLDIV 0x44
  29. #define MEMCLKMGR_MEMPLL_PLLOUTDIV 0x48
  30. #define MEMCLKMGR_MEMPLL_EXTCNTRST 0x4c
  31. #define MEMCLKMGR_CTRL_BOOTMODE BIT(0)
  32. #define MEMCLKMGR_STAT_MEMPLL_LOCKED BIT(8)
  33. #define MEMCLKMGR_STAT_ALLPLL_LOCKED_MASK \
  34. (MEMCLKMGR_STAT_MEMPLL_LOCKED)
  35. #define MEMCLKMGR_INTER_MEMPLLLOCKED_MASK BIT(0)
  36. #define MEMCLKMGR_INTER_MEMPLLLOST_MASK BIT(2)
  37. #define MEMCLKMGR_BYPASS_MEMPLL_ALL 0x1
  38. #define MEMCLKMGR_MEMDIV_MPFEDIV_OFFSET 0
  39. #define MEMCLKMGR_MEMDIV_APBDIV_OFFSET 4
  40. #define MEMCLKMGR_MEMDIV_DFICTRLDIV_OFFSET 8
  41. #define MEMCLKMGR_MEMDIV_DFIDIV_OFFSET 12
  42. #define MEMCLKMGR_MEMDIV_DFICTRLDIV_MASK BIT(0)
  43. #define MEMCLKMGR_MEMDIV_DIVIDER_MASK GENMASK(1, 0)
  44. #define MEMCLKMGR_PLLGLOB_PSRC_MASK GENMASK(17, 16)
  45. #define MEMCLKMGR_PLLGLOB_PSRC_OFFSET 16
  46. #define MEMCLKMGR_PLLGLOB_LOSTLOCK_BYPASS_EN_MASK BIT(28)
  47. #define MEMCLKMGR_PLLGLOB_CLR_LOSTLOCK_BYPASS_MASK BIT(29)
  48. #define MEMCLKMGR_PSRC_EOSC1 0
  49. #define MEMCLKMGR_PSRC_INTOSC 1
  50. #define MEMCLKMGR_PSRC_F2S 2
  51. #define MEMCLKMGR_PLLCTRL_BYPASS_MASK BIT(0)
  52. #define MEMCLKMGR_PLLCTRL_RST_N_MASK BIT(1)
  53. #define MEMCLKMGR_PLLDIV_DIVR_MASK GENMASK(5, 0)
  54. #define MEMCLKMGR_PLLDIV_DIVF_MASK GENMASK(16, 8)
  55. #define MEMCLKMGR_PLLDIV_DIVQ_MASK GENMASK(26, 24)
  56. #define MEMCLKMGR_PLLDIV_RANGE_MASK GENMASK(30, 28)
  57. #define MEMCLKMGR_PLLDIV_DIVR_OFFSET 0
  58. #define MEMCLKMGR_PLLDIV_DIVF_OFFSET 8
  59. #define MEMCLKMGR_PLLDIV_DIVQ_QDIV_OFFSET 24
  60. #define MEMCLKMGR_PLLDIV_RANGE_OFFSET 28
  61. #define MEMCLKMGR_PLLOUTDIV_C0CNT_MASK GENMASK(4, 0)
  62. #define MEMCLKMGR_PLLOUTDIV_C0CNT_OFFSET 0
  63. #define MEMCLKMGR_EXTCNTRST_C0CNTRST BIT(7)
  64. #define MEMCLKMGR_EXTCNTRST_ALLCNTRST \
  65. (MEMCLKMGR_EXTCNTRST_C0CNTRST)
  66. #endif /* _CLK_MEM_N5X_ */