clk-mem-n5x.c 3.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (C) 2020-2021 Intel Corporation <www.intel.com>
  4. */
  5. #include <common.h>
  6. #include <asm/arch/clock_manager.h>
  7. #include <asm/global_data.h>
  8. #include <asm/io.h>
  9. #include "clk-mem-n5x.h"
  10. #include <clk-uclass.h>
  11. #include <dm.h>
  12. #include <dm/lists.h>
  13. #include <dm/util.h>
  14. #include <dt-bindings/clock/n5x-clock.h>
  15. DECLARE_GLOBAL_DATA_PTR;
  16. struct socfpga_mem_clk_plat {
  17. void __iomem *regs;
  18. };
  19. void clk_mem_wait_for_lock(struct socfpga_mem_clk_plat *plat, u32 mask)
  20. {
  21. u32 inter_val;
  22. u32 retry = 0;
  23. do {
  24. inter_val = CM_REG_READL(plat, MEMCLKMGR_STAT) & mask;
  25. /* Wait for stable lock */
  26. if (inter_val == mask)
  27. retry++;
  28. else
  29. retry = 0;
  30. if (retry >= 10)
  31. return;
  32. } while (1);
  33. }
  34. /*
  35. * function to write the bypass register which requires a poll of the
  36. * busy bit
  37. */
  38. void clk_mem_write_bypass_mempll(struct socfpga_mem_clk_plat *plat, u32 val)
  39. {
  40. CM_REG_WRITEL(plat, val, MEMCLKMGR_MEMPLL_BYPASS);
  41. }
  42. /*
  43. * Setup clocks while making no assumptions about previous state of the clocks.
  44. */
  45. static void clk_mem_basic_init(struct udevice *dev,
  46. const struct cm_config * const cfg)
  47. {
  48. struct socfpga_mem_clk_plat *plat = dev_get_plat(dev);
  49. if (!cfg)
  50. return;
  51. /* Put PLLs in bypass */
  52. clk_mem_write_bypass_mempll(plat, MEMCLKMGR_BYPASS_MEMPLL_ALL);
  53. /* Put PLLs in Reset */
  54. CM_REG_SETBITS(plat, MEMCLKMGR_MEMPLL_PLLCTRL,
  55. MEMCLKMGR_PLLCTRL_BYPASS_MASK);
  56. /* setup mem PLL */
  57. CM_REG_WRITEL(plat, cfg->mem_memdiv, MEMCLKMGR_MEMPLL_MEMDIV);
  58. CM_REG_WRITEL(plat, cfg->mem_pllglob, MEMCLKMGR_MEMPLL_PLLGLOB);
  59. CM_REG_WRITEL(plat, cfg->mem_plldiv, MEMCLKMGR_MEMPLL_PLLDIV);
  60. CM_REG_WRITEL(plat, cfg->mem_plloutdiv, MEMCLKMGR_MEMPLL_PLLOUTDIV);
  61. /* Take PLL out of reset and power up */
  62. CM_REG_CLRBITS(plat, MEMCLKMGR_MEMPLL_PLLCTRL,
  63. MEMCLKMGR_PLLCTRL_BYPASS_MASK);
  64. }
  65. static int socfpga_mem_clk_enable(struct clk *clk)
  66. {
  67. const struct cm_config *cm_default_cfg = cm_get_default_config();
  68. struct socfpga_mem_clk_plat *plat = dev_get_plat(clk->dev);
  69. clk_mem_basic_init(clk->dev, cm_default_cfg);
  70. clk_mem_wait_for_lock(plat, MEMCLKMGR_STAT_ALLPLL_LOCKED_MASK);
  71. CM_REG_WRITEL(plat, CM_REG_READL(plat, MEMCLKMGR_MEMPLL_PLLGLOB) |
  72. MEMCLKMGR_PLLGLOB_CLR_LOSTLOCK_BYPASS_MASK,
  73. MEMCLKMGR_MEMPLL_PLLGLOB);
  74. /* Take all PLLs out of bypass */
  75. clk_mem_write_bypass_mempll(plat, 0);
  76. /* Clear the loss of lock bits (write 1 to clear) */
  77. CM_REG_CLRBITS(plat, MEMCLKMGR_INTRCLR,
  78. MEMCLKMGR_INTER_MEMPLLLOST_MASK);
  79. /* Take all ping pong counters out of reset */
  80. CM_REG_CLRBITS(plat, MEMCLKMGR_MEMPLL_EXTCNTRST,
  81. MEMCLKMGR_EXTCNTRST_ALLCNTRST);
  82. return 0;
  83. }
  84. static int socfpga_mem_clk_of_to_plat(struct udevice *dev)
  85. {
  86. struct socfpga_mem_clk_plat *plat = dev_get_plat(dev);
  87. fdt_addr_t addr;
  88. addr = devfdt_get_addr(dev);
  89. if (addr == FDT_ADDR_T_NONE)
  90. return -EINVAL;
  91. plat->regs = (void __iomem *)addr;
  92. return 0;
  93. }
  94. static struct clk_ops socfpga_mem_clk_ops = {
  95. .enable = socfpga_mem_clk_enable
  96. };
  97. static const struct udevice_id socfpga_mem_clk_match[] = {
  98. { .compatible = "intel,n5x-mem-clkmgr" },
  99. {}
  100. };
  101. U_BOOT_DRIVER(socfpga_n5x_mem_clk) = {
  102. .name = "mem-clk-n5x",
  103. .id = UCLASS_CLK,
  104. .of_match = socfpga_mem_clk_match,
  105. .ops = &socfpga_mem_clk_ops,
  106. .of_to_plat = socfpga_mem_clk_of_to_plat,
  107. .plat_auto = sizeof(struct socfpga_mem_clk_plat),
  108. };