system_manager_soc64.c 3.7 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119
  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (C) 2016-2021 Intel Corporation <www.intel.com>
  4. *
  5. */
  6. #include <asm/arch/handoff_soc64.h>
  7. #include <asm/arch/system_manager.h>
  8. #include <asm/global_data.h>
  9. #include <asm/io.h>
  10. #include <common.h>
  11. DECLARE_GLOBAL_DATA_PTR;
  12. /*
  13. * Configure all the pin muxes
  14. */
  15. void sysmgr_pinmux_init(void)
  16. {
  17. populate_sysmgr_pinmux();
  18. populate_sysmgr_fpgaintf_module();
  19. }
  20. /*
  21. * Populate the value for SYSMGR.FPGAINTF.MODULE based on pinmux setting.
  22. * The value is not wrote to SYSMGR.FPGAINTF.MODULE but
  23. * CONFIG_SYSMGR_ISWGRP_HANDOFF.
  24. */
  25. void populate_sysmgr_fpgaintf_module(void)
  26. {
  27. u32 handoff_val = 0;
  28. /* Enable the signal for those HPS peripherals that use FPGA. */
  29. if (readl(socfpga_get_sysmgr_addr() + SYSMGR_SOC64_NAND_USEFPGA) ==
  30. SYSMGR_FPGAINTF_USEFPGA)
  31. handoff_val |= SYSMGR_FPGAINTF_NAND;
  32. if (readl(socfpga_get_sysmgr_addr() + SYSMGR_SOC64_SDMMC_USEFPGA) ==
  33. SYSMGR_FPGAINTF_USEFPGA)
  34. handoff_val |= SYSMGR_FPGAINTF_SDMMC;
  35. if (readl(socfpga_get_sysmgr_addr() + SYSMGR_SOC64_SPIM0_USEFPGA) ==
  36. SYSMGR_FPGAINTF_USEFPGA)
  37. handoff_val |= SYSMGR_FPGAINTF_SPIM0;
  38. if (readl(socfpga_get_sysmgr_addr() + SYSMGR_SOC64_SPIM1_USEFPGA) ==
  39. SYSMGR_FPGAINTF_USEFPGA)
  40. handoff_val |= SYSMGR_FPGAINTF_SPIM1;
  41. writel(handoff_val,
  42. socfpga_get_sysmgr_addr() + SYSMGR_SOC64_FPGAINTF_EN2);
  43. handoff_val = 0;
  44. if (readl(socfpga_get_sysmgr_addr() + SYSMGR_SOC64_EMAC0_USEFPGA) ==
  45. SYSMGR_FPGAINTF_USEFPGA)
  46. handoff_val |= SYSMGR_FPGAINTF_EMAC0;
  47. if (readl(socfpga_get_sysmgr_addr() + SYSMGR_SOC64_EMAC1_USEFPGA) ==
  48. SYSMGR_FPGAINTF_USEFPGA)
  49. handoff_val |= SYSMGR_FPGAINTF_EMAC1;
  50. if (readl(socfpga_get_sysmgr_addr() + SYSMGR_SOC64_EMAC2_USEFPGA) ==
  51. SYSMGR_FPGAINTF_USEFPGA)
  52. handoff_val |= SYSMGR_FPGAINTF_EMAC2;
  53. writel(handoff_val,
  54. socfpga_get_sysmgr_addr() + SYSMGR_SOC64_FPGAINTF_EN3);
  55. }
  56. /*
  57. * Configure all the pin muxes
  58. */
  59. void populate_sysmgr_pinmux(void)
  60. {
  61. u32 len, i;
  62. u32 len_mux = socfpga_get_handoff_size((void *)SOC64_HANDOFF_MUX);
  63. u32 len_ioctl = socfpga_get_handoff_size((void *)SOC64_HANDOFF_IOCTL);
  64. u32 len_fpga = socfpga_get_handoff_size((void *)SOC64_HANDOFF_FPGA);
  65. u32 len_delay = socfpga_get_handoff_size((void *)SOC64_HANDOFF_DELAY);
  66. len = (len_mux > len_ioctl) ? len_mux : len_ioctl;
  67. len = (len > len_fpga) ? len : len_fpga;
  68. len = (len > len_delay) ? len : len_delay;
  69. u32 handoff_table[len];
  70. /* setup the pin sel */
  71. len = (len_mux < SOC64_HANDOFF_MUX_LEN) ? len_mux : SOC64_HANDOFF_MUX_LEN;
  72. socfpga_handoff_read((void *)SOC64_HANDOFF_MUX, handoff_table, len);
  73. for (i = 0; i < len; i = i + 2) {
  74. writel(handoff_table[i + 1],
  75. handoff_table[i] +
  76. (u8 *)socfpga_get_sysmgr_addr() +
  77. SYSMGR_SOC64_PINSEL0);
  78. }
  79. /* setup the pin ctrl */
  80. len = (len_ioctl < SOC64_HANDOFF_IOCTL_LEN) ? len_ioctl : SOC64_HANDOFF_IOCTL_LEN;
  81. socfpga_handoff_read((void *)SOC64_HANDOFF_IOCTL, handoff_table, len);
  82. for (i = 0; i < len; i = i + 2) {
  83. writel(handoff_table[i + 1],
  84. handoff_table[i] +
  85. (u8 *)socfpga_get_sysmgr_addr() +
  86. SYSMGR_SOC64_IOCTRL0);
  87. }
  88. /* setup the fpga use */
  89. len = (len_fpga < SOC64_HANDOFF_FPGA_LEN) ? len_fpga : SOC64_HANDOFF_FPGA_LEN;
  90. socfpga_handoff_read((void *)SOC64_HANDOFF_FPGA, handoff_table, len);
  91. for (i = 0; i < len; i = i + 2) {
  92. writel(handoff_table[i + 1],
  93. handoff_table[i] +
  94. (u8 *)socfpga_get_sysmgr_addr() +
  95. SYSMGR_SOC64_EMAC0_USEFPGA);
  96. }
  97. /* setup the IO delay */
  98. len = (len_delay < SOC64_HANDOFF_DELAY_LEN) ? len_delay : SOC64_HANDOFF_DELAY_LEN;
  99. socfpga_handoff_read((void *)SOC64_HANDOFF_DELAY, handoff_table, len);
  100. for (i = 0; i < len; i = i + 2) {
  101. writel(handoff_table[i + 1],
  102. handoff_table[i] +
  103. (u8 *)socfpga_get_sysmgr_addr() +
  104. SYSMGR_SOC64_IODELAY0);
  105. }
  106. }