clock_manager_n5x.c 1.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (C) 2020-2021 Intel Corporation <www.intel.com>
  4. *
  5. */
  6. #include <common.h>
  7. #include <asm/arch/clock_manager.h>
  8. #include <asm/arch/system_manager.h>
  9. #include <asm/global_data.h>
  10. #include <asm/io.h>
  11. #include <clk.h>
  12. #include <dm.h>
  13. #include <dt-bindings/clock/n5x-clock.h>
  14. #include <malloc.h>
  15. DECLARE_GLOBAL_DATA_PTR;
  16. static ulong cm_get_rate_dm(u32 id)
  17. {
  18. struct udevice *dev;
  19. struct clk clk;
  20. ulong rate;
  21. int ret;
  22. ret = uclass_get_device_by_driver(UCLASS_CLK,
  23. DM_DRIVER_GET(socfpga_n5x_clk),
  24. &dev);
  25. if (ret)
  26. return 0;
  27. clk.id = id;
  28. ret = clk_request(dev, &clk);
  29. if (ret < 0)
  30. return 0;
  31. rate = clk_get_rate(&clk);
  32. clk_free(&clk);
  33. if ((rate == (unsigned long)-ENXIO) ||
  34. (rate == (unsigned long)-EIO)) {
  35. debug("%s id %u: clk_get_rate err: %ld\n",
  36. __func__, id, rate);
  37. return 0;
  38. }
  39. return rate;
  40. }
  41. static u32 cm_get_rate_dm_khz(u32 id)
  42. {
  43. return cm_get_rate_dm(id) / 1000;
  44. }
  45. unsigned long cm_get_mpu_clk_hz(void)
  46. {
  47. return cm_get_rate_dm(N5X_MPU_CLK);
  48. }
  49. unsigned int cm_get_l4_sys_free_clk_hz(void)
  50. {
  51. return cm_get_rate_dm(N5X_L4_SYS_FREE_CLK);
  52. }
  53. void cm_print_clock_quick_summary(void)
  54. {
  55. printf("MPU %10d kHz\n",
  56. cm_get_rate_dm_khz(N5X_MPU_CLK));
  57. printf("L4 Main %8d kHz\n",
  58. cm_get_rate_dm_khz(N5X_L4_MAIN_CLK));
  59. printf("L4 sys free %8d kHz\n",
  60. cm_get_rate_dm_khz(N5X_L4_SYS_FREE_CLK));
  61. printf("L4 MP %8d kHz\n",
  62. cm_get_rate_dm_khz(N5X_L4_MP_CLK));
  63. printf("L4 SP %8d kHz\n",
  64. cm_get_rate_dm_khz(N5X_L4_SP_CLK));
  65. printf("SDMMC %8d kHz\n",
  66. cm_get_rate_dm_khz(N5X_SDMMC_CLK));
  67. }