socfpga_n5x_socdk-u-boot.dtsi 1.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * U-Boot additions
  4. *
  5. * Copyright (C) 2020-2021 Intel Corporation <www.intel.com>
  6. */
  7. #include "socfpga_n5x-u-boot.dtsi"
  8. /{
  9. aliases {
  10. spi0 = &qspi;
  11. i2c0 = &i2c1;
  12. };
  13. memory {
  14. /*
  15. * Memory type: DDR4 (non-interleaving mode)
  16. * 16GB
  17. * <0 0x00000000 0 0x80000000>,
  18. * <4 0x80000000 3 0x80000000>;
  19. *
  20. * 8GB
  21. * <0 0x00000000 0 0x80000000>,
  22. * <2 0x80000000 1 0x80000000>;
  23. *
  24. * 4GB
  25. * <0 0x00000000 0 0x80000000>,
  26. * <1 0x80000000 0 0x80000000>;
  27. *
  28. * Memory type: LPDDR4 (non-interleaving mode)
  29. * Total memory size 3GB, usable = 2.5GB, 0.5GB trade off for secure
  30. * region.
  31. */
  32. reg = <0 0x00000000 0 0x60000000>,
  33. <0x10 0x00100000 0 0x40000000>;
  34. };
  35. };
  36. &flash0 {
  37. compatible = "jedec,spi-nor";
  38. spi-tx-bus-width = <4>;
  39. spi-rx-bus-width = <4>;
  40. u-boot,dm-pre-reloc;
  41. };
  42. &i2c1 {
  43. status = "okay";
  44. };
  45. &mmc {
  46. drvsel = <3>;
  47. smplsel = <0>;
  48. u-boot,dm-pre-reloc;
  49. };
  50. &qspi {
  51. status = "okay";
  52. };
  53. &watchdog0 {
  54. u-boot,dm-pre-reloc;
  55. };