socfpga_n5x-u-boot.dtsi 2.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * U-Boot additions
  4. *
  5. * Copyright (C) 2020-2021 Intel Corporation <www.intel.com>
  6. */
  7. #include "socfpga_soc64_fit-u-boot.dtsi"
  8. #include <dt-bindings/clock/n5x-clock.h>
  9. /{
  10. memory {
  11. #address-cells = <2>;
  12. #size-cells = <2>;
  13. u-boot,dm-pre-reloc;
  14. };
  15. soc {
  16. u-boot,dm-pre-reloc;
  17. ccu: cache-controller@f7000000 {
  18. compatible = "arteris,ncore-ccu";
  19. reg = <0xf7000000 0x100900>;
  20. u-boot,dm-pre-reloc;
  21. };
  22. clocks {
  23. dram_eosc_clk: dram-eosc-clk {
  24. #clock-cells = <0>;
  25. compatible = "fixed-clock";
  26. };
  27. };
  28. memclkmgr: mem-clock-controller@f8040000 {
  29. compatible = "intel,n5x-mem-clkmgr";
  30. reg = <0xf8040000 0x1000>;
  31. #clock-cells = <0>;
  32. clocks = <&dram_eosc_clk>, <&f2s_free_clk>;
  33. };
  34. };
  35. };
  36. &clkmgr {
  37. compatible = "intel,n5x-clkmgr";
  38. u-boot,dm-pre-reloc;
  39. };
  40. &gmac0 {
  41. clocks = <&clkmgr N5X_EMAC0_CLK>;
  42. };
  43. &gmac1 {
  44. altr,sysmgr-syscon = <&sysmgr 0x48 0>;
  45. clocks = <&clkmgr N5X_EMAC1_CLK>;
  46. };
  47. &gmac2 {
  48. altr,sysmgr-syscon = <&sysmgr 0x4c 0>;
  49. clocks = <&clkmgr N5X_EMAC2_CLK>;
  50. };
  51. &i2c0 {
  52. clocks = <&clkmgr N5X_L4_SP_CLK>;
  53. reset-names = "i2c";
  54. };
  55. &i2c1 {
  56. clocks = <&clkmgr N5X_L4_SP_CLK>;
  57. reset-names = "i2c";
  58. };
  59. &i2c2 {
  60. clocks = <&clkmgr N5X_L4_SP_CLK>;
  61. reset-names = "i2c";
  62. };
  63. &i2c3 {
  64. clocks = <&clkmgr N5X_L4_SP_CLK>;
  65. reset-names = "i2c";
  66. };
  67. &i2c4 {
  68. clocks = <&clkmgr N5X_L4_SP_CLK>;
  69. reset-names = "i2c";
  70. };
  71. &memclkmgr {
  72. u-boot,dm-pre-reloc;
  73. };
  74. &mmc {
  75. clocks = <&clkmgr N5X_L4_MP_CLK>,
  76. <&clkmgr N5X_SDMMC_CLK>;
  77. resets = <&rst SDMMC_RESET>, <&rst SDMMC_OCP_RESET>;
  78. };
  79. &pdma {
  80. clocks = <&clkmgr N5X_L4_MAIN_CLK>;
  81. };
  82. &porta {
  83. bank-name = "porta";
  84. };
  85. &portb {
  86. bank-name = "portb";
  87. };
  88. &qspi {
  89. u-boot,dm-pre-reloc;
  90. };
  91. &rst {
  92. compatible = "altr,rst-mgr";
  93. altr,modrst-offset = <0x20>;
  94. u-boot,dm-pre-reloc;
  95. };
  96. &sdr {
  97. compatible = "intel,sdr-ctl-n5x";
  98. resets = <&rst DDRSCH_RESET>;
  99. clocks = <&memclkmgr>;
  100. clock-names = "mem_clk";
  101. u-boot,dm-pre-reloc;
  102. };
  103. &spi0 {
  104. clocks = <&clkmgr N5X_L4_MAIN_CLK>;
  105. };
  106. &spi1 {
  107. clocks = <&clkmgr N5X_L4_MAIN_CLK>;
  108. };
  109. &sysmgr {
  110. compatible = "altr,sys-mgr", "syscon";
  111. u-boot,dm-pre-reloc;
  112. };
  113. &timer0 {
  114. clocks = <&clkmgr N5X_L4_SP_CLK>;
  115. };
  116. &timer1 {
  117. clocks = <&clkmgr N5X_L4_SP_CLK>;
  118. };
  119. &timer2 {
  120. clocks = <&clkmgr N5X_L4_SP_CLK>;
  121. };
  122. &timer3 {
  123. clocks = <&clkmgr N5X_L4_SP_CLK>;
  124. };
  125. &uart0 {
  126. clocks = <&clkmgr N5X_L4_SP_CLK>;
  127. u-boot,dm-pre-reloc;
  128. };
  129. &uart1 {
  130. clocks = <&clkmgr N5X_L4_SP_CLK>;
  131. };
  132. &usb0 {
  133. clocks = <&clkmgr N5X_USB_CLK>;
  134. disable-over-current;
  135. u-boot,dm-pre-reloc;
  136. };
  137. &usb1 {
  138. clocks = <&clkmgr N5X_USB_CLK>;
  139. u-boot,dm-pre-reloc;
  140. };
  141. &watchdog0 {
  142. clocks = <&clkmgr N5X_L4_SYS_FREE_CLK>;
  143. u-boot,dm-pre-reloc;
  144. };
  145. &watchdog1 {
  146. clocks = <&clkmgr N5X_L4_SYS_FREE_CLK>;
  147. };
  148. &watchdog2 {
  149. clocks = <&clkmgr N5X_L4_SYS_FREE_CLK>;
  150. };
  151. &watchdog3 {
  152. clocks = <&clkmgr N5X_L4_SYS_FREE_CLK>;
  153. };