UCP1020.h 29 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright 2013-2019 Arcturus Networks, Inc.
  4. * https://www.arcturusnetworks.com/products/ucp1020/
  5. * based on include/configs/p1_p2_rdb_pc.h
  6. * original copyright follows:
  7. * Copyright 2009-2011 Freescale Semiconductor, Inc.
  8. */
  9. /*
  10. * QorIQ uCP1020-xx boards configuration file
  11. */
  12. #ifndef __CONFIG_H
  13. #define __CONFIG_H
  14. #include <linux/stringify.h>
  15. /*** Arcturus FirmWare Environment */
  16. #define MAX_SERIAL_SIZE 15
  17. #define MAX_HWADDR_SIZE 17
  18. #define MAX_FWENV_ADDR 4
  19. #define FWENV_MMC 1
  20. #define FWENV_SPI_FLASH 2
  21. #define FWENV_NOR_FLASH 3
  22. /*
  23. #define FWENV_TYPE FWENV_MMC
  24. #define FWENV_TYPE FWENV_SPI_FLASH
  25. */
  26. #define FWENV_TYPE FWENV_NOR_FLASH
  27. #if (FWENV_TYPE == FWENV_MMC)
  28. #define FWENV_ADDR1 -1
  29. #define FWENV_ADDR2 -1
  30. #define FWENV_ADDR3 -1
  31. #define FWENV_ADDR4 -1
  32. #define EMPY_CHAR 0
  33. #endif
  34. #if (FWENV_TYPE == FWENV_SPI_FLASH)
  35. #ifndef CONFIG_SF_DEFAULT_SPEED
  36. #define CONFIG_SF_DEFAULT_SPEED 1000000
  37. #endif
  38. #ifndef CONFIG_SF_DEFAULT_MODE
  39. #define CONFIG_SF_DEFAULT_MODE SPI_MODE0
  40. #endif
  41. #ifndef CONFIG_SF_DEFAULT_CS
  42. #define CONFIG_SF_DEFAULT_CS 0
  43. #endif
  44. #ifndef CONFIG_SF_DEFAULT_BUS
  45. #define CONFIG_SF_DEFAULT_BUS 0
  46. #endif
  47. #define FWENV_ADDR1 (0x200 - sizeof(smac))
  48. #define FWENV_ADDR2 (0x400 - sizeof(smac))
  49. #define FWENV_ADDR3 (CONFIG_ENV_SECT_SIZE + 0x200 - sizeof(smac))
  50. #define FWENV_ADDR4 (CONFIG_ENV_SECT_SIZE + 0x400 - sizeof(smac))
  51. #define EMPY_CHAR 0xff
  52. #endif
  53. #if (FWENV_TYPE == FWENV_NOR_FLASH)
  54. #define FWENV_ADDR1 0xEC080000
  55. #define FWENV_ADDR2 -1
  56. #define FWENV_ADDR3 -1
  57. #define FWENV_ADDR4 -1
  58. #define EMPY_CHAR 0xff
  59. #endif
  60. /***********************************/
  61. #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
  62. #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */
  63. #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
  64. #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
  65. #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
  66. #if defined(CONFIG_TARTGET_UCP1020T1)
  67. #define CONFIG_UCP1020_REV_1_3
  68. #define CONFIG_BOARDNAME "uCP1020-64EE512-0U1-XR-T1"
  69. #define CONFIG_TSEC1
  70. #define CONFIG_TSEC3
  71. #define CONFIG_HAS_ETH0
  72. #define CONFIG_HAS_ETH1
  73. #define CONFIG_ETHADDR 00:19:D3:FF:FF:FF
  74. #define CONFIG_ETH1ADDR 00:19:D3:FF:FF:FE
  75. #define CONFIG_ETH2ADDR 00:19:D3:FF:FF:FD
  76. #define CONFIG_IPADDR 10.80.41.229
  77. #define CONFIG_SERVERIP 10.80.41.227
  78. #define CONFIG_NETMASK 255.255.252.0
  79. #define CONFIG_ETHPRIME "eTSEC3"
  80. #define CONFIG_SYS_L2_SIZE (256 << 10)
  81. #endif
  82. #if defined(CONFIG_TARGET_UCP1020)
  83. #define CONFIG_UCP1020
  84. #define CONFIG_UCP1020_REV_1_3
  85. #define CONFIG_BOARDNAME_LOCAL "uCP1020-64EEE512-OU1-XR"
  86. #define CONFIG_TSEC1
  87. #define CONFIG_TSEC3
  88. #define CONFIG_HAS_ETH0
  89. #define CONFIG_HAS_ETH1
  90. #define CONFIG_HAS_ETH2
  91. #define CONFIG_ETHADDR 00:06:3B:FF:FF:FF
  92. #define CONFIG_ETH1ADDR 00:06:3B:FF:FF:FE
  93. #define CONFIG_ETH2ADDR 00:06:3B:FF:FF:FD
  94. #define CONFIG_IPADDR 192.168.1.81
  95. #define CONFIG_IPADDR1 192.168.1.82
  96. #define CONFIG_IPADDR2 192.168.1.83
  97. #define CONFIG_SERVERIP 192.168.1.80
  98. #define CONFIG_GATEWAYIP 102.168.1.1
  99. #define CONFIG_NETMASK 255.255.255.0
  100. #define CONFIG_ETHPRIME "eTSEC1"
  101. #define CONFIG_SYS_L2_SIZE (256 << 10)
  102. #endif
  103. #ifdef CONFIG_SDCARD
  104. #define CONFIG_RAMBOOT_SDCARD
  105. #define CONFIG_SYS_RAMBOOT
  106. #define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc
  107. #endif
  108. #ifdef CONFIG_SPIFLASH
  109. #define CONFIG_RAMBOOT_SPIFLASH
  110. #define CONFIG_SYS_RAMBOOT
  111. #define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc
  112. #endif
  113. #define CONFIG_SYS_TEXT_BASE_NOR 0xeff80000
  114. #ifndef CONFIG_RESET_VECTOR_ADDRESS
  115. #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
  116. #endif
  117. #ifndef CONFIG_SYS_MONITOR_BASE
  118. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
  119. #endif
  120. #define CONFIG_SYS_SATA_MAX_DEVICE 2
  121. #define CONFIG_LBA48
  122. #define CONFIG_SYS_CLK_FREQ 66666666
  123. #define CONFIG_DDR_CLK_FREQ 66666666
  124. #define CONFIG_HWCONFIG
  125. /*
  126. * These can be toggled for performance analysis, otherwise use default.
  127. */
  128. #define CONFIG_L2_CACHE
  129. #define CONFIG_BTB
  130. #define CONFIG_ENABLE_36BIT_PHYS
  131. #define CONFIG_SYS_CCSRBAR 0xffe00000
  132. #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
  133. /* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k
  134. SPL code*/
  135. #ifdef CONFIG_SPL_BUILD
  136. #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
  137. #endif
  138. /* DDR Setup */
  139. #define CONFIG_DDR_ECC_ENABLE
  140. #ifndef CONFIG_DDR_ECC_ENABLE
  141. #define CONFIG_SYS_DDR_RAW_TIMING
  142. #define CONFIG_DDR_SPD
  143. #endif
  144. #define CONFIG_SYS_SPD_BUS_NUM 1
  145. #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_512M
  146. #define CONFIG_CHIP_SELECTS_PER_CTRL 1
  147. #define CONFIG_SYS_SDRAM_SIZE (1u << (CONFIG_SYS_SDRAM_SIZE_LAW - 19))
  148. #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
  149. #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
  150. #define CONFIG_DIMM_SLOTS_PER_CTLR 1
  151. /* Default settings for DDR3 */
  152. #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f
  153. #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302
  154. #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
  155. #define CONFIG_SYS_DDR_CS1_BNDS 0x0040007f
  156. #define CONFIG_SYS_DDR_CS1_CONFIG 0x80014302
  157. #define CONFIG_SYS_DDR_CS1_CONFIG_2 0x00000000
  158. #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
  159. #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000
  160. #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000
  161. #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000
  162. #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600
  163. #define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8655A608
  164. #define CONFIG_SYS_DDR_SR_CNTR 0x00000000
  165. #define CONFIG_SYS_DDR_RCW_1 0x00000000
  166. #define CONFIG_SYS_DDR_RCW_2 0x00000000
  167. #ifdef CONFIG_DDR_ECC_ENABLE
  168. #define CONFIG_SYS_DDR_CONTROL 0xE70C0000 /* Type = DDR3 & ECC */
  169. #else
  170. #define CONFIG_SYS_DDR_CONTROL 0xC70C0000 /* Type = DDR3 */
  171. #endif
  172. #define CONFIG_SYS_DDR_CONTROL_2 0x04401050
  173. #define CONFIG_SYS_DDR_TIMING_4 0x00220001
  174. #define CONFIG_SYS_DDR_TIMING_5 0x03402400
  175. #define CONFIG_SYS_DDR_TIMING_3 0x00020000
  176. #define CONFIG_SYS_DDR_TIMING_0 0x00330004
  177. #define CONFIG_SYS_DDR_TIMING_1 0x6f6B4846
  178. #define CONFIG_SYS_DDR_TIMING_2 0x0FA8C8CF
  179. #define CONFIG_SYS_DDR_CLK_CTRL 0x03000000
  180. #define CONFIG_SYS_DDR_MODE_1 0x40461520
  181. #define CONFIG_SYS_DDR_MODE_2 0x8000c000
  182. #define CONFIG_SYS_DDR_INTERVAL 0x0C300000
  183. /*
  184. * Memory map
  185. *
  186. * 0x0000_0000 0x7fff_ffff DDR Up to 2GB cacheable
  187. * 0x8000_0000 0xdfff_ffff PCI Express Mem 1G non-cacheable(PCIe * 2)
  188. * 0xec00_0000 0xefff_ffff NOR flash Up to 64M non-cacheable CS0/1
  189. * 0xf8f8_0000 0xf8ff_ffff L2 SRAM Up to 256K cacheable
  190. * (early boot only)
  191. * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable
  192. * 0xffd0_0000 0xffd0_3fff L1 for stack 16K cacheable
  193. * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
  194. */
  195. /*
  196. * Local Bus Definitions
  197. */
  198. #define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */
  199. #define CONFIG_SYS_FLASH_BASE 0xec000000
  200. #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
  201. #define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
  202. | BR_PS_16 | BR_V)
  203. #define CONFIG_FLASH_OR_PRELIM 0xfc000ff7
  204. #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
  205. #define CONFIG_SYS_FLASH_QUIET_TEST
  206. #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
  207. #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
  208. #undef CONFIG_SYS_FLASH_CHECKSUM
  209. #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
  210. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
  211. #define CONFIG_SYS_FLASH_EMPTY_INFO
  212. #define CONFIG_SYS_INIT_RAM_LOCK
  213. #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */
  214. /* Initial L1 address */
  215. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR
  216. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
  217. #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
  218. /* Size of used area in RAM */
  219. #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
  220. #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
  221. GENERATED_GBL_DATA_SIZE)
  222. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  223. #define CONFIG_SYS_MONITOR_LEN (256 * 1024)/* Reserve 256 kB for Mon */
  224. #define CONFIG_SYS_MALLOC_LEN (1024 * 1024)/* Reserved for malloc */
  225. #define CONFIG_SYS_PMC_BASE 0xff980000
  226. #define CONFIG_SYS_PMC_BASE_PHYS CONFIG_SYS_PMC_BASE
  227. #define CONFIG_PMC_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_PMC_BASE_PHYS) | \
  228. BR_PS_8 | BR_V)
  229. #define CONFIG_PMC_OR_PRELIM (OR_AM_64KB | OR_GPCM_CSNT | OR_GPCM_XACS | \
  230. OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR | \
  231. OR_GPCM_EAD)
  232. #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
  233. #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
  234. #ifdef CONFIG_NAND_FSL_ELBC
  235. #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */
  236. #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
  237. #endif
  238. /* Serial Port - controlled on board with jumper J8
  239. * open - index 2
  240. * shorted - index 1
  241. */
  242. #undef CONFIG_SERIAL_SOFTWARE_FIFO
  243. #define CONFIG_SYS_NS16550_SERIAL
  244. #define CONFIG_SYS_NS16550_REG_SIZE 1
  245. #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
  246. #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
  247. #define CONFIG_NS16550_MIN_FUNCTIONS
  248. #endif
  249. #define CONFIG_SYS_BAUDRATE_TABLE \
  250. {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
  251. #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500)
  252. #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600)
  253. /* I2C */
  254. #define CONFIG_SYS_I2C_LEGACY
  255. #define CONFIG_SYS_I2C_FSL
  256. #define CONFIG_SYS_FSL_I2C_SPEED 400000
  257. #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
  258. #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
  259. #define CONFIG_SYS_FSL_I2C2_SPEED 400000
  260. #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
  261. #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
  262. #define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} }
  263. #define CONFIG_SYS_SPD_BUS_NUM 1 /* For rom_loc and flash bank */
  264. #define CONFIG_RTC_DS1337
  265. #define CONFIG_RTC_DS1337_NOOSC
  266. #define CONFIG_SYS_I2C_RTC_ADDR 0x68
  267. #define CONFIG_SYS_I2C_PCA9557_ADDR 0x18
  268. #define CONFIG_SYS_I2C_NCT72_ADDR 0x4C
  269. #define CONFIG_SYS_I2C_IDT6V49205B 0x69
  270. #if defined(CONFIG_PCI)
  271. /*
  272. * General PCI
  273. * Memory space is mapped 1-1, but I/O space must start from 0.
  274. */
  275. /* controller 2, direct to uli, tgtid 2, Base address 9000 */
  276. #define CONFIG_SYS_PCIE2_NAME "PCIe SLOT CON9"
  277. #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
  278. #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
  279. #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
  280. #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
  281. #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
  282. #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
  283. #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
  284. #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
  285. /* controller 1, Slot 2, tgtid 1, Base address a000 */
  286. #define CONFIG_SYS_PCIE1_NAME "PCIe SLOT CON10"
  287. #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
  288. #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
  289. #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
  290. #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
  291. #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000
  292. #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
  293. #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000
  294. #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
  295. #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
  296. #endif /* CONFIG_PCI */
  297. /*
  298. * Environment
  299. */
  300. #if !defined(CONFIG_ENV_FIT_UCBOOT) && defined(CONFIG_RAMBOOT_SDCARD)
  301. #define CONFIG_FSL_FIXED_MMC_LOCATION
  302. #endif
  303. #define CONFIG_LOADS_ECHO /* echo on for serial download */
  304. #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
  305. /*
  306. * USB
  307. */
  308. #define CONFIG_HAS_FSL_DR_USB
  309. #if defined(CONFIG_HAS_FSL_DR_USB)
  310. #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
  311. #ifdef CONFIG_USB_EHCI_HCD
  312. #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
  313. #define CONFIG_USB_EHCI_FSL
  314. #endif
  315. #endif
  316. #undef CONFIG_WATCHDOG /* watchdog disabled */
  317. #ifdef CONFIG_MMC
  318. #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
  319. #endif
  320. /* Misc Extra Settings */
  321. #undef CONFIG_WATCHDOG /* watchdog disabled */
  322. /*
  323. * Miscellaneous configurable options
  324. */
  325. #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
  326. #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms tick */
  327. /*
  328. * For booting Linux, the board info and command line data
  329. * have to be in the first 64 MB of memory, since this is
  330. * the maximum mapped by the Linux kernel during initialization.
  331. */
  332. #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux*/
  333. #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
  334. #if defined(CONFIG_CMD_KGDB)
  335. #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
  336. #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
  337. #endif
  338. /*
  339. * Environment Configuration
  340. */
  341. #if defined(CONFIG_TSEC_ENET)
  342. #if defined(CONFIG_UCP1020_REV_1_2) || defined(CONFIG_UCP1020_REV_1_3)
  343. #else
  344. #error "UCP1020 module revision is not defined !!!"
  345. #endif
  346. #define CONFIG_BOOTP_SERVERIP
  347. #define CONFIG_TSEC1_NAME "eTSEC1"
  348. #define CONFIG_TSEC2_NAME "eTSEC2"
  349. #define CONFIG_TSEC3_NAME "eTSEC3"
  350. #define TSEC1_PHY_ADDR 4
  351. #define TSEC2_PHY_ADDR 0
  352. #define TSEC2_PHY_ADDR_SGMII 0x00
  353. #define TSEC3_PHY_ADDR 6
  354. #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
  355. #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
  356. #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
  357. #define TSEC1_PHYIDX 0
  358. #define TSEC2_PHYIDX 0
  359. #define TSEC3_PHYIDX 0
  360. #endif
  361. #define CONFIG_HOSTNAME "UCP1020"
  362. #define CONFIG_ROOTPATH "/opt/nfsroot"
  363. #define CONFIG_BOOTFILE "uImage"
  364. #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
  365. /* default location for tftp and bootm */
  366. #define CONFIG_LOADADDR 1000000
  367. #if defined(CONFIG_DONGLE)
  368. #define CONFIG_EXTRA_ENV_SETTINGS \
  369. "bootcmd=run prog_spi_mbrbootcramfs\0" \
  370. "bootfile=uImage\0" \
  371. "consoledev=ttyS0\0" \
  372. "cramfsfile=image.cramfs\0" \
  373. "dtbaddr=0x00c00000\0" \
  374. "dtbfile=image.dtb\0" \
  375. "ethaddr=" __stringify(CONFIG_ETHADDR) "\0" \
  376. "eth1addr=" __stringify(CONFIG_ETH1ADDR) "\0" \
  377. "eth2addr=" __stringify(CONFIG_ETH2ADDR) "\0" \
  378. "fileaddr=0x01000000\0" \
  379. "filesize=0x00080000\0" \
  380. "flashmbr=sf probe 0; " \
  381. "tftp $loadaddr $mbr; " \
  382. "sf erase $mbr_offset +$filesize; " \
  383. "sf write $loadaddr $mbr_offset $filesize\0" \
  384. "flashrecovery=tftp $recoveryaddr $cramfsfile; " \
  385. "protect off $nor_recoveryaddr +$filesize; " \
  386. "erase $nor_recoveryaddr +$filesize; " \
  387. "cp.b $recoveryaddr $nor_recoveryaddr $filesize; " \
  388. "protect on $nor_recoveryaddr +$filesize\0 " \
  389. "flashuboot=tftp $ubootaddr $ubootfile; " \
  390. "protect off $nor_ubootaddr +$filesize; " \
  391. "erase $nor_ubootaddr +$filesize; " \
  392. "cp.b $ubootaddr $nor_ubootaddr $filesize; " \
  393. "protect on $nor_ubootaddr +$filesize\0 " \
  394. "flashworking=tftp $workingaddr $cramfsfile; " \
  395. "protect off $nor_workingaddr +$filesize; " \
  396. "erase $nor_workingaddr +$filesize; " \
  397. "cp.b $workingaddr $nor_workingaddr $filesize; " \
  398. "protect on $nor_workingaddr +$filesize\0 " \
  399. "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0 " \
  400. "kerneladdr=0x01100000\0" \
  401. "kernelfile=uImage\0" \
  402. "loadaddr=0x01000000\0" \
  403. "mbr=uCP1020d.mbr\0" \
  404. "mbr_offset=0x00000000\0" \
  405. "mmbr=uCP1020Quiet.mbr\0" \
  406. "mmcpart=0:2\0" \
  407. "mmc__mbrd=fatload mmc $mmcpart $loadaddr $mbr; " \
  408. "mmc erase 1 1; " \
  409. "mmc write $loadaddr 1 1\0" \
  410. "mmc__uboot=fatload mmc $mmcpart $loadaddr $ubootfile; " \
  411. "mmc erase 0x40 0x400; " \
  412. "mmc write $loadaddr 0x40 0x400\0" \
  413. "netdev=eth0\0" \
  414. "nor_recoveryaddr=0xEC0A0000\0" \
  415. "nor_ubootaddr=0xEFF80000\0" \
  416. "nor_workingaddr=0xECFA0000\0" \
  417. "norbootrecovery=setenv bootargs $recoverybootargs" \
  418. " console=$consoledev,$baudrate $othbootargs; " \
  419. "run norloadrecovery; " \
  420. "bootm $kerneladdr - $dtbaddr\0" \
  421. "norbootworking=setenv bootargs $workingbootargs" \
  422. " console=$consoledev,$baudrate $othbootargs; " \
  423. "run norloadworking; " \
  424. "bootm $kerneladdr - $dtbaddr\0" \
  425. "norloadrecovery=mw.l $kerneladdr 0x0 0x00a00000; " \
  426. "setenv cramfsaddr $nor_recoveryaddr; " \
  427. "cramfsload $dtbaddr $dtbfile; " \
  428. "cramfsload $kerneladdr $kernelfile\0" \
  429. "norloadworking=mw.l $kerneladdr 0x0 0x00a00000; " \
  430. "setenv cramfsaddr $nor_workingaddr; " \
  431. "cramfsload $dtbaddr $dtbfile; " \
  432. "cramfsload $kerneladdr $kernelfile\0" \
  433. "prog_spi_mbr=run spi__mbr\0" \
  434. "prog_spi_mbrboot=run spi__mbr; run spi__boot1; run spi__boot2\0" \
  435. "prog_spi_mbrbootcramfs=run spi__mbr; run spi__boot1; run spi__boot2; " \
  436. "run spi__cramfs\0" \
  437. "ramboot=setenv bootargs root=/dev/ram ramdisk_size=$ramdisk_size ro" \
  438. " console=$consoledev,$baudrate $othbootargs; " \
  439. "tftp $rootfsaddr $rootfsfile; " \
  440. "tftp $loadaddr $kernelfile; " \
  441. "tftp $dtbaddr $dtbfile; " \
  442. "bootm $loadaddr $rootfsaddr $dtbaddr\0" \
  443. "ramdisk_size=120000\0" \
  444. "ramdiskfile=rootfs.ext2.gz.uboot\0" \
  445. "recoveryaddr=0x02F00000\0" \
  446. "recoverybootargs=root=/dev/mtdblock0 rootfstype=cramfs ro\0" \
  447. "releasefpga=mw.l 0xffe0f000 0x00400000; mw.l 0xffe0f004 0x00000000; " \
  448. "mw.l 0xffe0f008 0x00400000\0" \
  449. "rootfsaddr=0x02F00000\0" \
  450. "rootfsfile=rootfs.ext2.gz.uboot\0" \
  451. "rootpath=/opt/nfsroot\0" \
  452. "spi__boot1=fatload mmc $mmcpart $loadaddr u-boot.bin; " \
  453. "protect off 0xeC000000 +$filesize; " \
  454. "erase 0xEC000000 +$filesize; " \
  455. "cp.b $loadaddr 0xEC000000 $filesize; " \
  456. "cmp.b $loadaddr 0xEC000000 $filesize; " \
  457. "protect on 0xeC000000 +$filesize\0" \
  458. "spi__boot2=fatload mmc $mmcpart $loadaddr u-boot.bin; " \
  459. "protect off 0xeFF80000 +$filesize; " \
  460. "erase 0xEFF80000 +$filesize; " \
  461. "cp.b $loadaddr 0xEFF80000 $filesize; " \
  462. "cmp.b $loadaddr 0xEFF80000 $filesize; " \
  463. "protect on 0xeFF80000 +$filesize\0" \
  464. "spi__bootd=fatload mmc $mmcpart $loadaddr $ubootd; " \
  465. "sf probe 0; sf erase 0x8000 +$filesize; " \
  466. "sf write $loadaddr 0x8000 $filesize\0" \
  467. "spi__cramfs=fatload mmc $mmcpart $loadaddr image.cramfs; " \
  468. "protect off 0xec0a0000 +$filesize; " \
  469. "erase 0xeC0A0000 +$filesize; " \
  470. "cp.b $loadaddr 0xeC0A0000 $filesize; " \
  471. "protect on 0xec0a0000 +$filesize\0" \
  472. "spi__mbr=fatload mmc $mmcpart $loadaddr $mmbr; " \
  473. "sf probe 1; sf erase 0 +$filesize; " \
  474. "sf write $loadaddr 0 $filesize\0" \
  475. "spi__mbrd=fatload mmc $mmcpart $loadaddr $mbr; " \
  476. "sf probe 0; sf erase 0 +$filesize; " \
  477. "sf write $loadaddr 0 $filesize\0" \
  478. "tftpflash=tftpboot $loadaddr $uboot; " \
  479. "protect off " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
  480. "erase " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
  481. "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize; " \
  482. "protect on " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
  483. "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize\0"\
  484. "uboot= " __stringify(CONFIG_UBOOTPATH) "\0" \
  485. "ubootaddr=0x01000000\0" \
  486. "ubootfile=u-boot.bin\0" \
  487. "ubootd=u-boot4dongle.bin\0" \
  488. "upgrade=run flashworking\0" \
  489. "usb_phy_type=ulpi\0 " \
  490. "workingaddr=0x02F00000\0" \
  491. "workingbootargs=root=/dev/mtdblock1 rootfstype=cramfs ro\0"
  492. #else
  493. #if defined(CONFIG_UCP1020T1)
  494. #define CONFIG_EXTRA_ENV_SETTINGS \
  495. "bootcmd=run releasefpga; run norbootworking || run norbootrecovery\0" \
  496. "bootfile=uImage\0" \
  497. "consoledev=ttyS0\0" \
  498. "cramfsfile=image.cramfs\0" \
  499. "dtbaddr=0x00c00000\0" \
  500. "dtbfile=image.dtb\0" \
  501. "ethaddr=" __stringify(CONFIG_ETHADDR) "\0" \
  502. "eth1addr=" __stringify(CONFIG_ETH1ADDR) "\0" \
  503. "eth2addr=" __stringify(CONFIG_ETH2ADDR) "\0" \
  504. "fileaddr=0x01000000\0" \
  505. "filesize=0x00080000\0" \
  506. "flashmbr=sf probe 0; " \
  507. "tftp $loadaddr $mbr; " \
  508. "sf erase $mbr_offset +$filesize; " \
  509. "sf write $loadaddr $mbr_offset $filesize\0" \
  510. "flashrecovery=tftp $recoveryaddr $cramfsfile; " \
  511. "protect off $nor_recoveryaddr +$filesize; " \
  512. "erase $nor_recoveryaddr +$filesize; " \
  513. "cp.b $recoveryaddr $nor_recoveryaddr $filesize; " \
  514. "protect on $nor_recoveryaddr +$filesize\0 " \
  515. "flashuboot=tftp $ubootaddr $ubootfile; " \
  516. "protect off $nor_ubootaddr +$filesize; " \
  517. "erase $nor_ubootaddr +$filesize; " \
  518. "cp.b $ubootaddr $nor_ubootaddr $filesize; " \
  519. "protect on $nor_ubootaddr +$filesize\0 " \
  520. "flashworking=tftp $workingaddr $cramfsfile; " \
  521. "protect off $nor_workingaddr +$filesize; " \
  522. "erase $nor_workingaddr +$filesize; " \
  523. "cp.b $workingaddr $nor_workingaddr $filesize; " \
  524. "protect on $nor_workingaddr +$filesize\0 " \
  525. "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0 " \
  526. "kerneladdr=0x01100000\0" \
  527. "kernelfile=uImage\0" \
  528. "loadaddr=0x01000000\0" \
  529. "mbr=uCP1020.mbr\0" \
  530. "mbr_offset=0x00000000\0" \
  531. "netdev=eth0\0" \
  532. "nor_recoveryaddr=0xEC0A0000\0" \
  533. "nor_ubootaddr=0xEFF80000\0" \
  534. "nor_workingaddr=0xECFA0000\0" \
  535. "norbootrecovery=setenv bootargs $recoverybootargs" \
  536. " console=$consoledev,$baudrate $othbootargs; " \
  537. "run norloadrecovery; " \
  538. "bootm $kerneladdr - $dtbaddr\0" \
  539. "norbootworking=setenv bootargs $workingbootargs" \
  540. " console=$consoledev,$baudrate $othbootargs; " \
  541. "run norloadworking; " \
  542. "bootm $kerneladdr - $dtbaddr\0" \
  543. "norloadrecovery=mw.l $kerneladdr 0x0 0x00a00000; " \
  544. "setenv cramfsaddr $nor_recoveryaddr; " \
  545. "cramfsload $dtbaddr $dtbfile; " \
  546. "cramfsload $kerneladdr $kernelfile\0" \
  547. "norloadworking=mw.l $kerneladdr 0x0 0x00a00000; " \
  548. "setenv cramfsaddr $nor_workingaddr; " \
  549. "cramfsload $dtbaddr $dtbfile; " \
  550. "cramfsload $kerneladdr $kernelfile\0" \
  551. "othbootargs=quiet\0" \
  552. "ramboot=setenv bootargs root=/dev/ram ramdisk_size=$ramdisk_size ro" \
  553. " console=$consoledev,$baudrate $othbootargs; " \
  554. "tftp $rootfsaddr $rootfsfile; " \
  555. "tftp $loadaddr $kernelfile; " \
  556. "tftp $dtbaddr $dtbfile; " \
  557. "bootm $loadaddr $rootfsaddr $dtbaddr\0" \
  558. "ramdisk_size=120000\0" \
  559. "ramdiskfile=rootfs.ext2.gz.uboot\0" \
  560. "recoveryaddr=0x02F00000\0" \
  561. "recoverybootargs=root=/dev/mtdblock0 rootfstype=cramfs ro\0" \
  562. "releasefpga=mw.l 0xffe0f000 0x00400000; mw.l 0xffe0f004 0x00000000; " \
  563. "mw.l 0xffe0f008 0x00400000\0" \
  564. "rootfsaddr=0x02F00000\0" \
  565. "rootfsfile=rootfs.ext2.gz.uboot\0" \
  566. "rootpath=/opt/nfsroot\0" \
  567. "silent=1\0" \
  568. "tftpflash=tftpboot $loadaddr $uboot; " \
  569. "protect off " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
  570. "erase " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
  571. "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize; " \
  572. "protect on " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
  573. "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize\0"\
  574. "uboot= " __stringify(CONFIG_UBOOTPATH) "\0" \
  575. "ubootaddr=0x01000000\0" \
  576. "ubootfile=u-boot.bin\0" \
  577. "upgrade=run flashworking\0" \
  578. "workingaddr=0x02F00000\0" \
  579. "workingbootargs=root=/dev/mtdblock1 rootfstype=cramfs ro\0"
  580. #else /* For Arcturus Modules */
  581. #define CONFIG_EXTRA_ENV_SETTINGS \
  582. "bootcmd=run norkernel\0" \
  583. "bootfile=uImage\0" \
  584. "consoledev=ttyS0\0" \
  585. "dtbaddr=0x00c00000\0" \
  586. "dtbfile=image.dtb\0" \
  587. "ethaddr=" __stringify(CONFIG_ETHADDR) "\0" \
  588. "eth1addr=" __stringify(CONFIG_ETH1ADDR) "\0" \
  589. "eth2addr=" __stringify(CONFIG_ETH2ADDR) "\0" \
  590. "fileaddr=0x01000000\0" \
  591. "filesize=0x00080000\0" \
  592. "flashmbr=sf probe 0; " \
  593. "tftp $loadaddr $mbr; " \
  594. "sf erase $mbr_offset +$filesize; " \
  595. "sf write $loadaddr $mbr_offset $filesize\0" \
  596. "flashuboot=tftp $loadaddr $ubootfile; " \
  597. "protect off $nor_ubootaddr0 +$filesize; " \
  598. "erase $nor_ubootaddr0 +$filesize; " \
  599. "cp.b $loadaddr $nor_ubootaddr0 $filesize; " \
  600. "protect on $nor_ubootaddr0 +$filesize; " \
  601. "protect off $nor_ubootaddr1 +$filesize; " \
  602. "erase $nor_ubootaddr1 +$filesize; " \
  603. "cp.b $loadaddr $nor_ubootaddr1 $filesize; " \
  604. "protect on $nor_ubootaddr1 +$filesize\0 " \
  605. "format0=protect off $part0base +$part0size; " \
  606. "erase $part0base +$part0size\0" \
  607. "format1=protect off $part1base +$part1size; " \
  608. "erase $part1base +$part1size\0" \
  609. "format2=protect off $part2base +$part2size; " \
  610. "erase $part2base +$part2size\0" \
  611. "format3=protect off $part3base +$part3size; " \
  612. "erase $part3base +$part3size\0" \
  613. "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0 " \
  614. "kerneladdr=0x01100000\0" \
  615. "kernelargs=root=/dev/mtdblock1 rootfstype=cramfs ro\0" \
  616. "kernelfile=uImage\0" \
  617. "loadaddr=0x01000000\0" \
  618. "mbr=uCP1020.mbr\0" \
  619. "mbr_offset=0x00000000\0" \
  620. "netdev=eth0\0" \
  621. "nor_ubootaddr0=0xEC000000\0" \
  622. "nor_ubootaddr1=0xEFF80000\0" \
  623. "norkernel=setenv bootargs $kernelargs console=$consoledev,$baudrate; " \
  624. "run norkernelload; " \
  625. "bootm $kerneladdr - $dtbaddr\0" \
  626. "norkernelload=mw.l $kerneladdr 0x0 0x00a00000; " \
  627. "setenv cramfsaddr $part0base; " \
  628. "cramfsload $dtbaddr $dtbfile; " \
  629. "cramfsload $kerneladdr $kernelfile\0" \
  630. "part0base=0xEC100000\0" \
  631. "part0size=0x00700000\0" \
  632. "part1base=0xEC800000\0" \
  633. "part1size=0x02000000\0" \
  634. "part2base=0xEE800000\0" \
  635. "part2size=0x00800000\0" \
  636. "part3base=0xEF000000\0" \
  637. "part3size=0x00F80000\0" \
  638. "partENVbase=0xEC080000\0" \
  639. "partENVsize=0x00080000\0" \
  640. "program0=tftp part0-000000.bin; " \
  641. "protect off $part0base +$filesize; " \
  642. "erase $part0base +$filesize; " \
  643. "cp.b $loadaddr $part0base $filesize; " \
  644. "echo Verifying...; " \
  645. "cmp.b $loadaddr $part0base $filesize\0" \
  646. "program1=tftp part1-000000.bin; " \
  647. "protect off $part1base +$filesize; " \
  648. "erase $part1base +$filesize; " \
  649. "cp.b $loadaddr $part1base $filesize; " \
  650. "echo Verifying...; " \
  651. "cmp.b $loadaddr $part1base $filesize\0" \
  652. "program2=tftp part2-000000.bin; " \
  653. "protect off $part2base +$filesize; " \
  654. "erase $part2base +$filesize; " \
  655. "cp.b $loadaddr $part2base $filesize; " \
  656. "echo Verifying...; " \
  657. "cmp.b $loadaddr $part2base $filesize\0" \
  658. "ramboot=setenv bootargs root=/dev/ram ramdisk_size=$ramdisk_size ro" \
  659. " console=$consoledev,$baudrate $othbootargs; " \
  660. "tftp $rootfsaddr $rootfsfile; " \
  661. "tftp $loadaddr $kernelfile; " \
  662. "tftp $dtbaddr $dtbfile; " \
  663. "bootm $loadaddr $rootfsaddr $dtbaddr\0" \
  664. "ramdisk_size=120000\0" \
  665. "ramdiskfile=rootfs.ext2.gz.uboot\0" \
  666. "releasefpga=mw.l 0xffe0f000 0x00400000; mw.l 0xffe0f004 0x00000000; " \
  667. "mw.l 0xffe0f008 0x00400000\0" \
  668. "rootfsaddr=0x02F00000\0" \
  669. "rootfsfile=rootfs.ext2.gz.uboot\0" \
  670. "rootpath=/opt/nfsroot\0" \
  671. "spi__mbr=fatload mmc $mmcpart $loadaddr $mmbr; " \
  672. "sf probe 0; sf erase 0 +$filesize; " \
  673. "sf write $loadaddr 0 $filesize\0" \
  674. "spi__boot=fatload mmc $mmcpart $loadaddr u-boot.bin; " \
  675. "protect off 0xeC000000 +$filesize; " \
  676. "erase 0xEC000000 +$filesize; " \
  677. "cp.b $loadaddr 0xEC000000 $filesize; " \
  678. "cmp.b $loadaddr 0xEC000000 $filesize; " \
  679. "protect on 0xeC000000 +$filesize\0" \
  680. "tftpflash=tftpboot $loadaddr $uboot; " \
  681. "protect off " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
  682. "erase " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
  683. "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize; " \
  684. "protect on " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
  685. "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize\0"\
  686. "uboot= " __stringify(CONFIG_UBOOTPATH) "\0" \
  687. "ubootfile=u-boot.bin\0" \
  688. "upgrade=run flashuboot\0" \
  689. "usb_phy_type=ulpi\0 " \
  690. "boot_nfs= " \
  691. "setenv bootargs root=/dev/nfs rw " \
  692. "nfsroot=$serverip:$rootpath " \
  693. "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
  694. "console=$consoledev,$baudrate $othbootargs;" \
  695. "tftp $loadaddr $bootfile;" \
  696. "tftp $fdtaddr $fdtfile;" \
  697. "bootm $loadaddr - $fdtaddr\0" \
  698. "boot_hd = " \
  699. "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \
  700. "console=$consoledev,$baudrate $othbootargs;" \
  701. "usb start;" \
  702. "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \
  703. "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \
  704. "bootm $loadaddr - $fdtaddr\0" \
  705. "boot_usb_fat = " \
  706. "setenv bootargs root=/dev/ram rw " \
  707. "console=$consoledev,$baudrate $othbootargs " \
  708. "ramdisk_size=$ramdisk_size;" \
  709. "usb start;" \
  710. "fatload usb 0:2 $loadaddr $bootfile;" \
  711. "fatload usb 0:2 $fdtaddr $fdtfile;" \
  712. "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \
  713. "bootm $loadaddr $ramdiskaddr $fdtaddr\0 " \
  714. "boot_usb_ext2 = " \
  715. "setenv bootargs root=/dev/ram rw " \
  716. "console=$consoledev,$baudrate $othbootargs " \
  717. "ramdisk_size=$ramdisk_size;" \
  718. "usb start;" \
  719. "ext2load usb 0:4 $loadaddr $bootfile;" \
  720. "ext2load usb 0:4 $fdtaddr $fdtfile;" \
  721. "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
  722. "bootm $loadaddr $ramdiskaddr $fdtaddr\0 " \
  723. "boot_nor = " \
  724. "setenv bootargs root=/dev/$jffs2nor rw " \
  725. "console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;" \
  726. "bootm $norbootaddr - $norfdtaddr\0 " \
  727. "boot_ram = " \
  728. "setenv bootargs root=/dev/ram rw " \
  729. "console=$consoledev,$baudrate $othbootargs " \
  730. "ramdisk_size=$ramdisk_size;" \
  731. "tftp $ramdiskaddr $ramdiskfile;" \
  732. "tftp $loadaddr $bootfile;" \
  733. "tftp $fdtaddr $fdtfile;" \
  734. "bootm $loadaddr $ramdiskaddr $fdtaddr\0"
  735. #endif
  736. #endif
  737. #endif /* __CONFIG_H */