sdhci.c 24 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2011, Marvell Semiconductor Inc.
  4. * Lei Wen <leiwen@marvell.com>
  5. *
  6. * Back ported to the 8xx platform (from the 8260 platform) by
  7. * Murray.Jensen@cmst.csiro.au, 27-Jan-01.
  8. */
  9. #include <common.h>
  10. #include <cpu_func.h>
  11. #include <dm.h>
  12. #include <errno.h>
  13. #include <log.h>
  14. #include <malloc.h>
  15. #include <mmc.h>
  16. #include <sdhci.h>
  17. #include <asm/cache.h>
  18. #include <linux/bitops.h>
  19. #include <linux/delay.h>
  20. #include <linux/dma-mapping.h>
  21. #include <phys2bus.h>
  22. #include <power/regulator.h>
  23. static void sdhci_reset(struct sdhci_host *host, u8 mask)
  24. {
  25. unsigned long timeout;
  26. /* Wait max 100 ms */
  27. timeout = 100;
  28. sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
  29. while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
  30. if (timeout == 0) {
  31. printf("%s: Reset 0x%x never completed.\n",
  32. __func__, (int)mask);
  33. return;
  34. }
  35. timeout--;
  36. udelay(1000);
  37. }
  38. }
  39. static void sdhci_cmd_done(struct sdhci_host *host, struct mmc_cmd *cmd)
  40. {
  41. int i;
  42. if (cmd->resp_type & MMC_RSP_136) {
  43. /* CRC is stripped so we need to do some shifting. */
  44. for (i = 0; i < 4; i++) {
  45. cmd->response[i] = sdhci_readl(host,
  46. SDHCI_RESPONSE + (3-i)*4) << 8;
  47. if (i != 3)
  48. cmd->response[i] |= sdhci_readb(host,
  49. SDHCI_RESPONSE + (3-i)*4-1);
  50. }
  51. } else {
  52. cmd->response[0] = sdhci_readl(host, SDHCI_RESPONSE);
  53. }
  54. }
  55. static void sdhci_transfer_pio(struct sdhci_host *host, struct mmc_data *data)
  56. {
  57. int i;
  58. char *offs;
  59. for (i = 0; i < data->blocksize; i += 4) {
  60. offs = data->dest + i;
  61. if (data->flags == MMC_DATA_READ)
  62. *(u32 *)offs = sdhci_readl(host, SDHCI_BUFFER);
  63. else
  64. sdhci_writel(host, *(u32 *)offs, SDHCI_BUFFER);
  65. }
  66. }
  67. #if (defined(CONFIG_MMC_SDHCI_SDMA) || CONFIG_IS_ENABLED(MMC_SDHCI_ADMA))
  68. static void sdhci_prepare_dma(struct sdhci_host *host, struct mmc_data *data,
  69. int *is_aligned, int trans_bytes)
  70. {
  71. dma_addr_t dma_addr;
  72. unsigned char ctrl;
  73. void *buf;
  74. if (data->flags == MMC_DATA_READ)
  75. buf = data->dest;
  76. else
  77. buf = (void *)data->src;
  78. ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
  79. ctrl &= ~SDHCI_CTRL_DMA_MASK;
  80. if (host->flags & USE_ADMA64)
  81. ctrl |= SDHCI_CTRL_ADMA64;
  82. else if (host->flags & USE_ADMA)
  83. ctrl |= SDHCI_CTRL_ADMA32;
  84. sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
  85. if (host->flags & USE_SDMA &&
  86. (host->force_align_buffer ||
  87. (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR &&
  88. ((unsigned long)buf & 0x7) != 0x0))) {
  89. *is_aligned = 0;
  90. if (data->flags != MMC_DATA_READ)
  91. memcpy(host->align_buffer, buf, trans_bytes);
  92. buf = host->align_buffer;
  93. }
  94. host->start_addr = dma_map_single(buf, trans_bytes,
  95. mmc_get_dma_dir(data));
  96. if (host->flags & USE_SDMA) {
  97. dma_addr = dev_phys_to_bus(mmc_to_dev(host->mmc), host->start_addr);
  98. sdhci_writel(host, dma_addr, SDHCI_DMA_ADDRESS);
  99. }
  100. #if CONFIG_IS_ENABLED(MMC_SDHCI_ADMA)
  101. else if (host->flags & (USE_ADMA | USE_ADMA64)) {
  102. sdhci_prepare_adma_table(host->adma_desc_table, data,
  103. host->start_addr);
  104. sdhci_writel(host, lower_32_bits(host->adma_addr),
  105. SDHCI_ADMA_ADDRESS);
  106. if (host->flags & USE_ADMA64)
  107. sdhci_writel(host, upper_32_bits(host->adma_addr),
  108. SDHCI_ADMA_ADDRESS_HI);
  109. }
  110. #endif
  111. }
  112. #else
  113. static void sdhci_prepare_dma(struct sdhci_host *host, struct mmc_data *data,
  114. int *is_aligned, int trans_bytes)
  115. {}
  116. #endif
  117. static int sdhci_transfer_data(struct sdhci_host *host, struct mmc_data *data)
  118. {
  119. dma_addr_t start_addr = host->start_addr;
  120. unsigned int stat, rdy, mask, timeout, block = 0;
  121. bool transfer_done = false;
  122. timeout = 1000000;
  123. rdy = SDHCI_INT_SPACE_AVAIL | SDHCI_INT_DATA_AVAIL;
  124. mask = SDHCI_DATA_AVAILABLE | SDHCI_SPACE_AVAILABLE;
  125. do {
  126. stat = sdhci_readl(host, SDHCI_INT_STATUS);
  127. if (stat & SDHCI_INT_ERROR) {
  128. pr_debug("%s: Error detected in status(0x%X)!\n",
  129. __func__, stat);
  130. return -EIO;
  131. }
  132. if (!transfer_done && (stat & rdy)) {
  133. if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) & mask))
  134. continue;
  135. sdhci_writel(host, rdy, SDHCI_INT_STATUS);
  136. sdhci_transfer_pio(host, data);
  137. data->dest += data->blocksize;
  138. if (++block >= data->blocks) {
  139. /* Keep looping until the SDHCI_INT_DATA_END is
  140. * cleared, even if we finished sending all the
  141. * blocks.
  142. */
  143. transfer_done = true;
  144. continue;
  145. }
  146. }
  147. if ((host->flags & USE_DMA) && !transfer_done &&
  148. (stat & SDHCI_INT_DMA_END)) {
  149. sdhci_writel(host, SDHCI_INT_DMA_END, SDHCI_INT_STATUS);
  150. if (host->flags & USE_SDMA) {
  151. start_addr &=
  152. ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1);
  153. start_addr += SDHCI_DEFAULT_BOUNDARY_SIZE;
  154. start_addr = dev_phys_to_bus(mmc_to_dev(host->mmc),
  155. start_addr);
  156. sdhci_writel(host, start_addr, SDHCI_DMA_ADDRESS);
  157. }
  158. }
  159. if (timeout-- > 0)
  160. udelay(10);
  161. else {
  162. printf("%s: Transfer data timeout\n", __func__);
  163. return -ETIMEDOUT;
  164. }
  165. } while (!(stat & SDHCI_INT_DATA_END));
  166. #if (defined(CONFIG_MMC_SDHCI_SDMA) || CONFIG_IS_ENABLED(MMC_SDHCI_ADMA))
  167. dma_unmap_single(host->start_addr, data->blocks * data->blocksize,
  168. mmc_get_dma_dir(data));
  169. #endif
  170. return 0;
  171. }
  172. /*
  173. * No command will be sent by driver if card is busy, so driver must wait
  174. * for card ready state.
  175. * Every time when card is busy after timeout then (last) timeout value will be
  176. * increased twice but only if it doesn't exceed global defined maximum.
  177. * Each function call will use last timeout value.
  178. */
  179. #define SDHCI_CMD_MAX_TIMEOUT 3200
  180. #define SDHCI_CMD_DEFAULT_TIMEOUT 100
  181. #define SDHCI_READ_STATUS_TIMEOUT 1000
  182. #ifdef CONFIG_DM_MMC
  183. static int sdhci_send_command(struct udevice *dev, struct mmc_cmd *cmd,
  184. struct mmc_data *data)
  185. {
  186. struct mmc *mmc = mmc_get_mmc_dev(dev);
  187. #else
  188. static int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd,
  189. struct mmc_data *data)
  190. {
  191. #endif
  192. struct sdhci_host *host = mmc->priv;
  193. unsigned int stat = 0;
  194. int ret = 0;
  195. int trans_bytes = 0, is_aligned = 1;
  196. u32 mask, flags, mode;
  197. unsigned int time = 0;
  198. int mmc_dev = mmc_get_blk_desc(mmc)->devnum;
  199. ulong start = get_timer(0);
  200. host->start_addr = 0;
  201. /* Timeout unit - ms */
  202. static unsigned int cmd_timeout = SDHCI_CMD_DEFAULT_TIMEOUT;
  203. mask = SDHCI_CMD_INHIBIT | SDHCI_DATA_INHIBIT;
  204. /* We shouldn't wait for data inihibit for stop commands, even
  205. though they might use busy signaling */
  206. if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION ||
  207. ((cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK ||
  208. cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200) && !data))
  209. mask &= ~SDHCI_DATA_INHIBIT;
  210. while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
  211. if (time >= cmd_timeout) {
  212. printf("%s: MMC: %d busy ", __func__, mmc_dev);
  213. if (2 * cmd_timeout <= SDHCI_CMD_MAX_TIMEOUT) {
  214. cmd_timeout += cmd_timeout;
  215. printf("timeout increasing to: %u ms.\n",
  216. cmd_timeout);
  217. } else {
  218. puts("timeout.\n");
  219. return -ECOMM;
  220. }
  221. }
  222. time++;
  223. udelay(1000);
  224. }
  225. sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS);
  226. mask = SDHCI_INT_RESPONSE;
  227. if ((cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK ||
  228. cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200) && !data)
  229. mask = SDHCI_INT_DATA_AVAIL;
  230. if (!(cmd->resp_type & MMC_RSP_PRESENT))
  231. flags = SDHCI_CMD_RESP_NONE;
  232. else if (cmd->resp_type & MMC_RSP_136)
  233. flags = SDHCI_CMD_RESP_LONG;
  234. else if (cmd->resp_type & MMC_RSP_BUSY) {
  235. flags = SDHCI_CMD_RESP_SHORT_BUSY;
  236. mask |= SDHCI_INT_DATA_END;
  237. } else
  238. flags = SDHCI_CMD_RESP_SHORT;
  239. if (cmd->resp_type & MMC_RSP_CRC)
  240. flags |= SDHCI_CMD_CRC;
  241. if (cmd->resp_type & MMC_RSP_OPCODE)
  242. flags |= SDHCI_CMD_INDEX;
  243. if (data || cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK ||
  244. cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200)
  245. flags |= SDHCI_CMD_DATA;
  246. /* Set Transfer mode regarding to data flag */
  247. if (data) {
  248. sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL);
  249. mode = SDHCI_TRNS_BLK_CNT_EN;
  250. trans_bytes = data->blocks * data->blocksize;
  251. if (data->blocks > 1)
  252. mode |= SDHCI_TRNS_MULTI;
  253. if (data->flags == MMC_DATA_READ)
  254. mode |= SDHCI_TRNS_READ;
  255. if (host->flags & USE_DMA) {
  256. mode |= SDHCI_TRNS_DMA;
  257. sdhci_prepare_dma(host, data, &is_aligned, trans_bytes);
  258. }
  259. sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
  260. data->blocksize),
  261. SDHCI_BLOCK_SIZE);
  262. sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
  263. sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
  264. } else if (cmd->resp_type & MMC_RSP_BUSY) {
  265. sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL);
  266. }
  267. sdhci_writel(host, cmd->cmdarg, SDHCI_ARGUMENT);
  268. sdhci_writew(host, SDHCI_MAKE_CMD(cmd->cmdidx, flags), SDHCI_COMMAND);
  269. start = get_timer(0);
  270. do {
  271. stat = sdhci_readl(host, SDHCI_INT_STATUS);
  272. if (stat & SDHCI_INT_ERROR)
  273. break;
  274. if (get_timer(start) >= SDHCI_READ_STATUS_TIMEOUT) {
  275. if (host->quirks & SDHCI_QUIRK_BROKEN_R1B) {
  276. return 0;
  277. } else {
  278. printf("%s: Timeout for status update!\n",
  279. __func__);
  280. return -ETIMEDOUT;
  281. }
  282. }
  283. } while ((stat & mask) != mask);
  284. if ((stat & (SDHCI_INT_ERROR | mask)) == mask) {
  285. sdhci_cmd_done(host, cmd);
  286. sdhci_writel(host, mask, SDHCI_INT_STATUS);
  287. } else
  288. ret = -1;
  289. if (!ret && data)
  290. ret = sdhci_transfer_data(host, data);
  291. if (host->quirks & SDHCI_QUIRK_WAIT_SEND_CMD)
  292. udelay(1000);
  293. stat = sdhci_readl(host, SDHCI_INT_STATUS);
  294. sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS);
  295. if (!ret) {
  296. if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) &&
  297. !is_aligned && (data->flags == MMC_DATA_READ))
  298. memcpy(data->dest, host->align_buffer, trans_bytes);
  299. return 0;
  300. }
  301. sdhci_reset(host, SDHCI_RESET_CMD);
  302. sdhci_reset(host, SDHCI_RESET_DATA);
  303. if (stat & SDHCI_INT_TIMEOUT)
  304. return -ETIMEDOUT;
  305. else
  306. return -ECOMM;
  307. }
  308. #if defined(CONFIG_DM_MMC) && defined(MMC_SUPPORTS_TUNING)
  309. static int sdhci_execute_tuning(struct udevice *dev, uint opcode)
  310. {
  311. int err;
  312. struct mmc *mmc = mmc_get_mmc_dev(dev);
  313. struct sdhci_host *host = mmc->priv;
  314. debug("%s\n", __func__);
  315. if (host->ops && host->ops->platform_execute_tuning) {
  316. err = host->ops->platform_execute_tuning(mmc, opcode);
  317. if (err)
  318. return err;
  319. return 0;
  320. }
  321. return 0;
  322. }
  323. #endif
  324. int sdhci_set_clock(struct mmc *mmc, unsigned int clock)
  325. {
  326. struct sdhci_host *host = mmc->priv;
  327. unsigned int div, clk = 0, timeout;
  328. int ret;
  329. /* Wait max 20 ms */
  330. timeout = 200;
  331. while (sdhci_readl(host, SDHCI_PRESENT_STATE) &
  332. (SDHCI_CMD_INHIBIT | SDHCI_DATA_INHIBIT)) {
  333. if (timeout == 0) {
  334. printf("%s: Timeout to wait cmd & data inhibit\n",
  335. __func__);
  336. return -EBUSY;
  337. }
  338. timeout--;
  339. udelay(100);
  340. }
  341. sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
  342. if (clock == 0)
  343. return 0;
  344. if (host->ops && host->ops->set_delay) {
  345. ret = host->ops->set_delay(host);
  346. if (ret) {
  347. printf("%s: Error while setting tap delay\n", __func__);
  348. return ret;
  349. }
  350. }
  351. if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
  352. /*
  353. * Check if the Host Controller supports Programmable Clock
  354. * Mode.
  355. */
  356. if (host->clk_mul) {
  357. for (div = 1; div <= 1024; div++) {
  358. if ((host->max_clk / div) <= clock)
  359. break;
  360. }
  361. /*
  362. * Set Programmable Clock Mode in the Clock
  363. * Control register.
  364. */
  365. clk = SDHCI_PROG_CLOCK_MODE;
  366. div--;
  367. } else {
  368. /* Version 3.00 divisors must be a multiple of 2. */
  369. if (host->max_clk <= clock) {
  370. div = 1;
  371. } else {
  372. for (div = 2;
  373. div < SDHCI_MAX_DIV_SPEC_300;
  374. div += 2) {
  375. if ((host->max_clk / div) <= clock)
  376. break;
  377. }
  378. }
  379. div >>= 1;
  380. }
  381. } else {
  382. /* Version 2.00 divisors must be a power of 2. */
  383. for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
  384. if ((host->max_clk / div) <= clock)
  385. break;
  386. }
  387. div >>= 1;
  388. }
  389. if (host->ops && host->ops->set_clock)
  390. host->ops->set_clock(host, div);
  391. clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
  392. clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
  393. << SDHCI_DIVIDER_HI_SHIFT;
  394. clk |= SDHCI_CLOCK_INT_EN;
  395. sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
  396. /* Wait max 20 ms */
  397. timeout = 20;
  398. while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
  399. & SDHCI_CLOCK_INT_STABLE)) {
  400. if (timeout == 0) {
  401. printf("%s: Internal clock never stabilised.\n",
  402. __func__);
  403. return -EBUSY;
  404. }
  405. timeout--;
  406. udelay(1000);
  407. }
  408. clk |= SDHCI_CLOCK_CARD_EN;
  409. sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
  410. return 0;
  411. }
  412. static void sdhci_set_power(struct sdhci_host *host, unsigned short power)
  413. {
  414. u8 pwr = 0;
  415. if (power != (unsigned short)-1) {
  416. switch (1 << power) {
  417. case MMC_VDD_165_195:
  418. pwr = SDHCI_POWER_180;
  419. break;
  420. case MMC_VDD_29_30:
  421. case MMC_VDD_30_31:
  422. pwr = SDHCI_POWER_300;
  423. break;
  424. case MMC_VDD_32_33:
  425. case MMC_VDD_33_34:
  426. pwr = SDHCI_POWER_330;
  427. break;
  428. }
  429. }
  430. if (pwr == 0) {
  431. sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
  432. return;
  433. }
  434. pwr |= SDHCI_POWER_ON;
  435. sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
  436. }
  437. void sdhci_set_uhs_timing(struct sdhci_host *host)
  438. {
  439. struct mmc *mmc = host->mmc;
  440. u32 reg;
  441. reg = sdhci_readw(host, SDHCI_HOST_CONTROL2);
  442. reg &= ~SDHCI_CTRL_UHS_MASK;
  443. switch (mmc->selected_mode) {
  444. case UHS_SDR50:
  445. case MMC_HS_52:
  446. reg |= SDHCI_CTRL_UHS_SDR50;
  447. break;
  448. case UHS_DDR50:
  449. case MMC_DDR_52:
  450. reg |= SDHCI_CTRL_UHS_DDR50;
  451. break;
  452. case UHS_SDR104:
  453. case MMC_HS_200:
  454. reg |= SDHCI_CTRL_UHS_SDR104;
  455. break;
  456. case MMC_HS_400:
  457. reg |= SDHCI_CTRL_HS400;
  458. break;
  459. default:
  460. reg |= SDHCI_CTRL_UHS_SDR12;
  461. }
  462. sdhci_writew(host, reg, SDHCI_HOST_CONTROL2);
  463. }
  464. static void sdhci_set_voltage(struct sdhci_host *host)
  465. {
  466. if (IS_ENABLED(CONFIG_MMC_IO_VOLTAGE)) {
  467. struct mmc *mmc = (struct mmc *)host->mmc;
  468. u32 ctrl;
  469. ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
  470. switch (mmc->signal_voltage) {
  471. case MMC_SIGNAL_VOLTAGE_330:
  472. #if CONFIG_IS_ENABLED(DM_REGULATOR)
  473. if (mmc->vqmmc_supply) {
  474. if (regulator_set_enable_if_allowed(mmc->vqmmc_supply, false)) {
  475. pr_err("failed to disable vqmmc-supply\n");
  476. return;
  477. }
  478. if (regulator_set_value(mmc->vqmmc_supply, 3300000)) {
  479. pr_err("failed to set vqmmc-voltage to 3.3V\n");
  480. return;
  481. }
  482. if (regulator_set_enable_if_allowed(mmc->vqmmc_supply, true)) {
  483. pr_err("failed to enable vqmmc-supply\n");
  484. return;
  485. }
  486. }
  487. #endif
  488. if (IS_SD(mmc)) {
  489. ctrl &= ~SDHCI_CTRL_VDD_180;
  490. sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
  491. }
  492. /* Wait for 5ms */
  493. mdelay(5);
  494. /* 3.3V regulator output should be stable within 5 ms */
  495. if (IS_SD(mmc)) {
  496. if (ctrl & SDHCI_CTRL_VDD_180) {
  497. pr_err("3.3V regulator output did not become stable\n");
  498. return;
  499. }
  500. }
  501. break;
  502. case MMC_SIGNAL_VOLTAGE_180:
  503. #if CONFIG_IS_ENABLED(DM_REGULATOR)
  504. if (mmc->vqmmc_supply) {
  505. if (regulator_set_enable_if_allowed(mmc->vqmmc_supply, false)) {
  506. pr_err("failed to disable vqmmc-supply\n");
  507. return;
  508. }
  509. if (regulator_set_value(mmc->vqmmc_supply, 1800000)) {
  510. pr_err("failed to set vqmmc-voltage to 1.8V\n");
  511. return;
  512. }
  513. if (regulator_set_enable_if_allowed(mmc->vqmmc_supply, true)) {
  514. pr_err("failed to enable vqmmc-supply\n");
  515. return;
  516. }
  517. }
  518. #endif
  519. if (IS_SD(mmc)) {
  520. ctrl |= SDHCI_CTRL_VDD_180;
  521. sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
  522. }
  523. /* Wait for 5 ms */
  524. mdelay(5);
  525. /* 1.8V regulator output has to be stable within 5 ms */
  526. if (IS_SD(mmc)) {
  527. if (!(ctrl & SDHCI_CTRL_VDD_180)) {
  528. pr_err("1.8V regulator output did not become stable\n");
  529. return;
  530. }
  531. }
  532. break;
  533. default:
  534. /* No signal voltage switch required */
  535. return;
  536. }
  537. }
  538. }
  539. void sdhci_set_control_reg(struct sdhci_host *host)
  540. {
  541. sdhci_set_voltage(host);
  542. sdhci_set_uhs_timing(host);
  543. }
  544. #ifdef CONFIG_DM_MMC
  545. static int sdhci_set_ios(struct udevice *dev)
  546. {
  547. struct mmc *mmc = mmc_get_mmc_dev(dev);
  548. #else
  549. static int sdhci_set_ios(struct mmc *mmc)
  550. {
  551. #endif
  552. u32 ctrl;
  553. struct sdhci_host *host = mmc->priv;
  554. bool no_hispd_bit = false;
  555. if (host->ops && host->ops->set_control_reg)
  556. host->ops->set_control_reg(host);
  557. if (mmc->clock != host->clock)
  558. sdhci_set_clock(mmc, mmc->clock);
  559. if (mmc->clk_disable)
  560. sdhci_set_clock(mmc, 0);
  561. /* Set bus width */
  562. ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
  563. if (mmc->bus_width == 8) {
  564. ctrl &= ~SDHCI_CTRL_4BITBUS;
  565. if ((SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) ||
  566. (host->quirks & SDHCI_QUIRK_USE_WIDE8))
  567. ctrl |= SDHCI_CTRL_8BITBUS;
  568. } else {
  569. if ((SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) ||
  570. (host->quirks & SDHCI_QUIRK_USE_WIDE8))
  571. ctrl &= ~SDHCI_CTRL_8BITBUS;
  572. if (mmc->bus_width == 4)
  573. ctrl |= SDHCI_CTRL_4BITBUS;
  574. else
  575. ctrl &= ~SDHCI_CTRL_4BITBUS;
  576. }
  577. if ((host->quirks & SDHCI_QUIRK_NO_HISPD_BIT) ||
  578. (host->quirks & SDHCI_QUIRK_BROKEN_HISPD_MODE)) {
  579. ctrl &= ~SDHCI_CTRL_HISPD;
  580. no_hispd_bit = true;
  581. }
  582. if (!no_hispd_bit) {
  583. if (mmc->selected_mode == MMC_HS ||
  584. mmc->selected_mode == SD_HS ||
  585. mmc->selected_mode == MMC_DDR_52 ||
  586. mmc->selected_mode == MMC_HS_200 ||
  587. mmc->selected_mode == MMC_HS_400 ||
  588. mmc->selected_mode == UHS_SDR25 ||
  589. mmc->selected_mode == UHS_SDR50 ||
  590. mmc->selected_mode == UHS_SDR104 ||
  591. mmc->selected_mode == UHS_DDR50)
  592. ctrl |= SDHCI_CTRL_HISPD;
  593. else
  594. ctrl &= ~SDHCI_CTRL_HISPD;
  595. }
  596. sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
  597. /* If available, call the driver specific "post" set_ios() function */
  598. if (host->ops && host->ops->set_ios_post)
  599. return host->ops->set_ios_post(host);
  600. return 0;
  601. }
  602. static int sdhci_init(struct mmc *mmc)
  603. {
  604. struct sdhci_host *host = mmc->priv;
  605. #if CONFIG_IS_ENABLED(DM_MMC) && CONFIG_IS_ENABLED(DM_GPIO)
  606. struct udevice *dev = mmc->dev;
  607. gpio_request_by_name(dev, "cd-gpios", 0,
  608. &host->cd_gpio, GPIOD_IS_IN);
  609. #endif
  610. sdhci_reset(host, SDHCI_RESET_ALL);
  611. #if defined(CONFIG_FIXED_SDHCI_ALIGNED_BUFFER)
  612. host->align_buffer = (void *)CONFIG_FIXED_SDHCI_ALIGNED_BUFFER;
  613. /*
  614. * Always use this bounce-buffer when CONFIG_FIXED_SDHCI_ALIGNED_BUFFER
  615. * is defined.
  616. */
  617. host->force_align_buffer = true;
  618. #else
  619. if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) {
  620. host->align_buffer = memalign(8, 512 * 1024);
  621. if (!host->align_buffer) {
  622. printf("%s: Aligned buffer alloc failed!!!\n",
  623. __func__);
  624. return -ENOMEM;
  625. }
  626. }
  627. #endif
  628. sdhci_set_power(host, fls(mmc->cfg->voltages) - 1);
  629. if (host->ops && host->ops->get_cd)
  630. host->ops->get_cd(host);
  631. /* Enable only interrupts served by the SD controller */
  632. sdhci_writel(host, SDHCI_INT_DATA_MASK | SDHCI_INT_CMD_MASK,
  633. SDHCI_INT_ENABLE);
  634. /* Mask all sdhci interrupt sources */
  635. sdhci_writel(host, 0x0, SDHCI_SIGNAL_ENABLE);
  636. return 0;
  637. }
  638. #ifdef CONFIG_DM_MMC
  639. int sdhci_probe(struct udevice *dev)
  640. {
  641. struct mmc *mmc = mmc_get_mmc_dev(dev);
  642. return sdhci_init(mmc);
  643. }
  644. static int sdhci_deferred_probe(struct udevice *dev)
  645. {
  646. int err;
  647. struct mmc *mmc = mmc_get_mmc_dev(dev);
  648. struct sdhci_host *host = mmc->priv;
  649. if (host->ops && host->ops->deferred_probe) {
  650. err = host->ops->deferred_probe(host);
  651. if (err)
  652. return err;
  653. }
  654. return 0;
  655. }
  656. static int sdhci_get_cd(struct udevice *dev)
  657. {
  658. struct mmc *mmc = mmc_get_mmc_dev(dev);
  659. struct sdhci_host *host = mmc->priv;
  660. int value;
  661. /* If nonremovable, assume that the card is always present. */
  662. if (mmc->cfg->host_caps & MMC_CAP_NONREMOVABLE)
  663. return 1;
  664. /* If polling, assume that the card is always present. */
  665. if (mmc->cfg->host_caps & MMC_CAP_NEEDS_POLL)
  666. return 1;
  667. #if CONFIG_IS_ENABLED(DM_GPIO)
  668. value = dm_gpio_get_value(&host->cd_gpio);
  669. if (value >= 0) {
  670. if (mmc->cfg->host_caps & MMC_CAP_CD_ACTIVE_HIGH)
  671. return !value;
  672. else
  673. return value;
  674. }
  675. #endif
  676. value = !!(sdhci_readl(host, SDHCI_PRESENT_STATE) &
  677. SDHCI_CARD_PRESENT);
  678. if (mmc->cfg->host_caps & MMC_CAP_CD_ACTIVE_HIGH)
  679. return !value;
  680. else
  681. return value;
  682. }
  683. const struct dm_mmc_ops sdhci_ops = {
  684. .send_cmd = sdhci_send_command,
  685. .set_ios = sdhci_set_ios,
  686. .get_cd = sdhci_get_cd,
  687. .deferred_probe = sdhci_deferred_probe,
  688. #ifdef MMC_SUPPORTS_TUNING
  689. .execute_tuning = sdhci_execute_tuning,
  690. #endif
  691. };
  692. #else
  693. static const struct mmc_ops sdhci_ops = {
  694. .send_cmd = sdhci_send_command,
  695. .set_ios = sdhci_set_ios,
  696. .init = sdhci_init,
  697. };
  698. #endif
  699. int sdhci_setup_cfg(struct mmc_config *cfg, struct sdhci_host *host,
  700. u32 f_max, u32 f_min)
  701. {
  702. u32 caps, caps_1 = 0;
  703. #if CONFIG_IS_ENABLED(DM_MMC)
  704. u64 dt_caps, dt_caps_mask;
  705. dt_caps_mask = dev_read_u64_default(host->mmc->dev,
  706. "sdhci-caps-mask", 0);
  707. dt_caps = dev_read_u64_default(host->mmc->dev,
  708. "sdhci-caps", 0);
  709. caps = ~lower_32_bits(dt_caps_mask) &
  710. sdhci_readl(host, SDHCI_CAPABILITIES);
  711. caps |= lower_32_bits(dt_caps);
  712. #else
  713. caps = sdhci_readl(host, SDHCI_CAPABILITIES);
  714. #endif
  715. debug("%s, caps: 0x%x\n", __func__, caps);
  716. #ifdef CONFIG_MMC_SDHCI_SDMA
  717. if ((caps & SDHCI_CAN_DO_SDMA)) {
  718. host->flags |= USE_SDMA;
  719. } else {
  720. debug("%s: Your controller doesn't support SDMA!!\n",
  721. __func__);
  722. }
  723. #endif
  724. #if CONFIG_IS_ENABLED(MMC_SDHCI_ADMA)
  725. if (!(caps & SDHCI_CAN_DO_ADMA2)) {
  726. printf("%s: Your controller doesn't support SDMA!!\n",
  727. __func__);
  728. return -EINVAL;
  729. }
  730. host->adma_desc_table = sdhci_adma_init();
  731. host->adma_addr = (dma_addr_t)host->adma_desc_table;
  732. #ifdef CONFIG_DMA_ADDR_T_64BIT
  733. host->flags |= USE_ADMA64;
  734. #else
  735. host->flags |= USE_ADMA;
  736. #endif
  737. #endif
  738. if (host->quirks & SDHCI_QUIRK_REG32_RW)
  739. host->version =
  740. sdhci_readl(host, SDHCI_HOST_VERSION - 2) >> 16;
  741. else
  742. host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
  743. cfg->name = host->name;
  744. #ifndef CONFIG_DM_MMC
  745. cfg->ops = &sdhci_ops;
  746. #endif
  747. /* Check whether the clock multiplier is supported or not */
  748. if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
  749. #if CONFIG_IS_ENABLED(DM_MMC)
  750. caps_1 = ~upper_32_bits(dt_caps_mask) &
  751. sdhci_readl(host, SDHCI_CAPABILITIES_1);
  752. caps_1 |= upper_32_bits(dt_caps);
  753. #else
  754. caps_1 = sdhci_readl(host, SDHCI_CAPABILITIES_1);
  755. #endif
  756. debug("%s, caps_1: 0x%x\n", __func__, caps_1);
  757. host->clk_mul = (caps_1 & SDHCI_CLOCK_MUL_MASK) >>
  758. SDHCI_CLOCK_MUL_SHIFT;
  759. }
  760. if (host->max_clk == 0) {
  761. if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300)
  762. host->max_clk = (caps & SDHCI_CLOCK_V3_BASE_MASK) >>
  763. SDHCI_CLOCK_BASE_SHIFT;
  764. else
  765. host->max_clk = (caps & SDHCI_CLOCK_BASE_MASK) >>
  766. SDHCI_CLOCK_BASE_SHIFT;
  767. host->max_clk *= 1000000;
  768. if (host->clk_mul)
  769. host->max_clk *= host->clk_mul;
  770. }
  771. if (host->max_clk == 0) {
  772. printf("%s: Hardware doesn't specify base clock frequency\n",
  773. __func__);
  774. return -EINVAL;
  775. }
  776. if (f_max && (f_max < host->max_clk))
  777. cfg->f_max = f_max;
  778. else
  779. cfg->f_max = host->max_clk;
  780. if (f_min)
  781. cfg->f_min = f_min;
  782. else {
  783. if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300)
  784. cfg->f_min = cfg->f_max / SDHCI_MAX_DIV_SPEC_300;
  785. else
  786. cfg->f_min = cfg->f_max / SDHCI_MAX_DIV_SPEC_200;
  787. }
  788. cfg->voltages = 0;
  789. if (caps & SDHCI_CAN_VDD_330)
  790. cfg->voltages |= MMC_VDD_32_33 | MMC_VDD_33_34;
  791. if (caps & SDHCI_CAN_VDD_300)
  792. cfg->voltages |= MMC_VDD_29_30 | MMC_VDD_30_31;
  793. if (caps & SDHCI_CAN_VDD_180)
  794. cfg->voltages |= MMC_VDD_165_195;
  795. if (host->quirks & SDHCI_QUIRK_BROKEN_VOLTAGE)
  796. cfg->voltages |= host->voltages;
  797. if (caps & SDHCI_CAN_DO_HISPD)
  798. cfg->host_caps |= MMC_MODE_HS | MMC_MODE_HS_52MHz;
  799. cfg->host_caps |= MMC_MODE_4BIT;
  800. /* Since Host Controller Version3.0 */
  801. if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
  802. if (!(caps & SDHCI_CAN_DO_8BIT))
  803. cfg->host_caps &= ~MMC_MODE_8BIT;
  804. }
  805. if (host->quirks & SDHCI_QUIRK_BROKEN_HISPD_MODE) {
  806. cfg->host_caps &= ~MMC_MODE_HS;
  807. cfg->host_caps &= ~MMC_MODE_HS_52MHz;
  808. }
  809. if (!(cfg->voltages & MMC_VDD_165_195) ||
  810. (host->quirks & SDHCI_QUIRK_NO_1_8_V))
  811. caps_1 &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
  812. SDHCI_SUPPORT_DDR50);
  813. if (caps_1 & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
  814. SDHCI_SUPPORT_DDR50))
  815. cfg->host_caps |= MMC_CAP(UHS_SDR12) | MMC_CAP(UHS_SDR25);
  816. if (caps_1 & SDHCI_SUPPORT_SDR104) {
  817. cfg->host_caps |= MMC_CAP(UHS_SDR104) | MMC_CAP(UHS_SDR50);
  818. /*
  819. * SD3.0: SDR104 is supported so (for eMMC) the caps2
  820. * field can be promoted to support HS200.
  821. */
  822. cfg->host_caps |= MMC_CAP(MMC_HS_200);
  823. } else if (caps_1 & SDHCI_SUPPORT_SDR50) {
  824. cfg->host_caps |= MMC_CAP(UHS_SDR50);
  825. }
  826. if (caps_1 & SDHCI_SUPPORT_DDR50)
  827. cfg->host_caps |= MMC_CAP(UHS_DDR50);
  828. if (host->host_caps)
  829. cfg->host_caps |= host->host_caps;
  830. cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
  831. return 0;
  832. }
  833. #ifdef CONFIG_BLK
  834. int sdhci_bind(struct udevice *dev, struct mmc *mmc, struct mmc_config *cfg)
  835. {
  836. return mmc_bind(dev, mmc, cfg);
  837. }
  838. #else
  839. int add_sdhci(struct sdhci_host *host, u32 f_max, u32 f_min)
  840. {
  841. int ret;
  842. ret = sdhci_setup_cfg(&host->cfg, host, f_max, f_min);
  843. if (ret)
  844. return ret;
  845. host->mmc = mmc_create(&host->cfg, host);
  846. if (host->mmc == NULL) {
  847. printf("%s: mmc create fail!\n", __func__);
  848. return -ENOMEM;
  849. }
  850. return 0;
  851. }
  852. #endif