fsl_esdhc.c 30 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2007, 2010-2011 Freescale Semiconductor, Inc
  4. * Copyright 2019-2021 NXP
  5. * Andy Fleming
  6. *
  7. * Based vaguely on the pxa mmc code:
  8. * (C) Copyright 2003
  9. * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
  10. */
  11. #include <config.h>
  12. #include <common.h>
  13. #include <command.h>
  14. #include <cpu_func.h>
  15. #include <errno.h>
  16. #include <hwconfig.h>
  17. #include <mmc.h>
  18. #include <part.h>
  19. #include <malloc.h>
  20. #include <fsl_esdhc.h>
  21. #include <fdt_support.h>
  22. #include <asm/cache.h>
  23. #include <asm/global_data.h>
  24. #include <asm/io.h>
  25. #include <dm.h>
  26. #include <dm/device_compat.h>
  27. #include <linux/bitops.h>
  28. #include <linux/delay.h>
  29. #include <linux/dma-mapping.h>
  30. #include <sdhci.h>
  31. DECLARE_GLOBAL_DATA_PTR;
  32. struct fsl_esdhc {
  33. uint dsaddr; /* SDMA system address register */
  34. uint blkattr; /* Block attributes register */
  35. uint cmdarg; /* Command argument register */
  36. uint xfertyp; /* Transfer type register */
  37. uint cmdrsp0; /* Command response 0 register */
  38. uint cmdrsp1; /* Command response 1 register */
  39. uint cmdrsp2; /* Command response 2 register */
  40. uint cmdrsp3; /* Command response 3 register */
  41. uint datport; /* Buffer data port register */
  42. uint prsstat; /* Present state register */
  43. uint proctl; /* Protocol control register */
  44. uint sysctl; /* System Control Register */
  45. uint irqstat; /* Interrupt status register */
  46. uint irqstaten; /* Interrupt status enable register */
  47. uint irqsigen; /* Interrupt signal enable register */
  48. uint autoc12err; /* Auto CMD error status register */
  49. uint hostcapblt; /* Host controller capabilities register */
  50. uint wml; /* Watermark level register */
  51. char reserved1[8]; /* reserved */
  52. uint fevt; /* Force event register */
  53. uint admaes; /* ADMA error status register */
  54. uint adsaddrl; /* ADMA system address low register */
  55. uint adsaddrh; /* ADMA system address high register */
  56. char reserved2[156];
  57. uint hostver; /* Host controller version register */
  58. char reserved3[4]; /* reserved */
  59. uint dmaerraddr; /* DMA error address register */
  60. char reserved4[4]; /* reserved */
  61. uint dmaerrattr; /* DMA error attribute register */
  62. char reserved5[4]; /* reserved */
  63. uint hostcapblt2; /* Host controller capabilities register 2 */
  64. char reserved6[8]; /* reserved */
  65. uint tbctl; /* Tuning block control register */
  66. char reserved7[32]; /* reserved */
  67. uint sdclkctl; /* SD clock control register */
  68. uint sdtimingctl; /* SD timing control register */
  69. char reserved8[20]; /* reserved */
  70. uint dllcfg0; /* DLL config 0 register */
  71. uint dllcfg1; /* DLL config 1 register */
  72. char reserved9[8]; /* reserved */
  73. uint dllstat0; /* DLL status 0 register */
  74. char reserved10[664];/* reserved */
  75. uint esdhcctl; /* eSDHC control register */
  76. };
  77. struct fsl_esdhc_plat {
  78. struct mmc_config cfg;
  79. struct mmc mmc;
  80. };
  81. /**
  82. * struct fsl_esdhc_priv
  83. *
  84. * @esdhc_regs: registers of the sdhc controller
  85. * @sdhc_clk: Current clk of the sdhc controller
  86. * @bus_width: bus width, 1bit, 4bit or 8bit
  87. * @cfg: mmc config
  88. * @mmc: mmc
  89. * Following is used when Driver Model is enabled for MMC
  90. * @dev: pointer for the device
  91. * @cd_gpio: gpio for card detection
  92. * @wp_gpio: gpio for write protection
  93. */
  94. struct fsl_esdhc_priv {
  95. struct fsl_esdhc *esdhc_regs;
  96. unsigned int sdhc_clk;
  97. bool is_sdhc_per_clk;
  98. unsigned int clock;
  99. #if !CONFIG_IS_ENABLED(DM_MMC)
  100. struct mmc *mmc;
  101. #endif
  102. struct udevice *dev;
  103. struct sdhci_adma_desc *adma_desc_table;
  104. dma_addr_t dma_addr;
  105. };
  106. /* Return the XFERTYP flags for a given command and data packet */
  107. static uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data *data)
  108. {
  109. uint xfertyp = 0;
  110. if (data) {
  111. xfertyp |= XFERTYP_DPSEL;
  112. if (!IS_ENABLED(CONFIG_SYS_FSL_ESDHC_USE_PIO) &&
  113. cmd->cmdidx != MMC_CMD_SEND_TUNING_BLOCK &&
  114. cmd->cmdidx != MMC_CMD_SEND_TUNING_BLOCK_HS200)
  115. xfertyp |= XFERTYP_DMAEN;
  116. if (data->blocks > 1) {
  117. xfertyp |= XFERTYP_MSBSEL;
  118. xfertyp |= XFERTYP_BCEN;
  119. if (IS_ENABLED(CONFIG_SYS_FSL_ERRATUM_ESDHC111))
  120. xfertyp |= XFERTYP_AC12EN;
  121. }
  122. if (data->flags & MMC_DATA_READ)
  123. xfertyp |= XFERTYP_DTDSEL;
  124. }
  125. if (cmd->resp_type & MMC_RSP_CRC)
  126. xfertyp |= XFERTYP_CCCEN;
  127. if (cmd->resp_type & MMC_RSP_OPCODE)
  128. xfertyp |= XFERTYP_CICEN;
  129. if (cmd->resp_type & MMC_RSP_136)
  130. xfertyp |= XFERTYP_RSPTYP_136;
  131. else if (cmd->resp_type & MMC_RSP_BUSY)
  132. xfertyp |= XFERTYP_RSPTYP_48_BUSY;
  133. else if (cmd->resp_type & MMC_RSP_PRESENT)
  134. xfertyp |= XFERTYP_RSPTYP_48;
  135. if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
  136. xfertyp |= XFERTYP_CMDTYP_ABORT;
  137. return XFERTYP_CMD(cmd->cmdidx) | xfertyp;
  138. }
  139. /*
  140. * PIO Read/Write Mode reduce the performace as DMA is not used in this mode.
  141. */
  142. static void esdhc_pio_read_write(struct fsl_esdhc_priv *priv,
  143. struct mmc_data *data)
  144. {
  145. struct fsl_esdhc *regs = priv->esdhc_regs;
  146. uint blocks;
  147. char *buffer;
  148. uint databuf;
  149. uint size;
  150. uint irqstat;
  151. ulong start;
  152. if (data->flags & MMC_DATA_READ) {
  153. blocks = data->blocks;
  154. buffer = data->dest;
  155. while (blocks) {
  156. start = get_timer(0);
  157. size = data->blocksize;
  158. irqstat = esdhc_read32(&regs->irqstat);
  159. while (!(esdhc_read32(&regs->prsstat) & PRSSTAT_BREN)) {
  160. if (get_timer(start) > PIO_TIMEOUT) {
  161. printf("\nData Read Failed in PIO Mode.");
  162. return;
  163. }
  164. }
  165. while (size && (!(irqstat & IRQSTAT_TC))) {
  166. udelay(100); /* Wait before last byte transfer complete */
  167. irqstat = esdhc_read32(&regs->irqstat);
  168. databuf = in_le32(&regs->datport);
  169. *((uint *)buffer) = databuf;
  170. buffer += 4;
  171. size -= 4;
  172. }
  173. blocks--;
  174. }
  175. } else {
  176. blocks = data->blocks;
  177. buffer = (char *)data->src;
  178. while (blocks) {
  179. start = get_timer(0);
  180. size = data->blocksize;
  181. irqstat = esdhc_read32(&regs->irqstat);
  182. while (!(esdhc_read32(&regs->prsstat) & PRSSTAT_BWEN)) {
  183. if (get_timer(start) > PIO_TIMEOUT) {
  184. printf("\nData Write Failed in PIO Mode.");
  185. return;
  186. }
  187. }
  188. while (size && (!(irqstat & IRQSTAT_TC))) {
  189. udelay(100); /* Wait before last byte transfer complete */
  190. databuf = *((uint *)buffer);
  191. buffer += 4;
  192. size -= 4;
  193. irqstat = esdhc_read32(&regs->irqstat);
  194. out_le32(&regs->datport, databuf);
  195. }
  196. blocks--;
  197. }
  198. }
  199. }
  200. static void esdhc_setup_watermark_level(struct fsl_esdhc_priv *priv,
  201. struct mmc_data *data)
  202. {
  203. struct fsl_esdhc *regs = priv->esdhc_regs;
  204. uint wml_value = data->blocksize / 4;
  205. if (data->flags & MMC_DATA_READ) {
  206. if (wml_value > WML_RD_WML_MAX)
  207. wml_value = WML_RD_WML_MAX_VAL;
  208. esdhc_clrsetbits32(&regs->wml, WML_RD_WML_MASK, wml_value);
  209. } else {
  210. if (wml_value > WML_WR_WML_MAX)
  211. wml_value = WML_WR_WML_MAX_VAL;
  212. esdhc_clrsetbits32(&regs->wml, WML_WR_WML_MASK,
  213. wml_value << 16);
  214. }
  215. }
  216. static void esdhc_setup_dma(struct fsl_esdhc_priv *priv, struct mmc_data *data)
  217. {
  218. uint trans_bytes = data->blocksize * data->blocks;
  219. struct fsl_esdhc *regs = priv->esdhc_regs;
  220. phys_addr_t adma_addr;
  221. void *buf;
  222. if (data->flags & MMC_DATA_WRITE)
  223. buf = (void *)data->src;
  224. else
  225. buf = data->dest;
  226. priv->dma_addr = dma_map_single(buf, trans_bytes,
  227. mmc_get_dma_dir(data));
  228. if (IS_ENABLED(CONFIG_FSL_ESDHC_SUPPORT_ADMA2) &&
  229. priv->adma_desc_table) {
  230. debug("Using ADMA2\n");
  231. /* prefer ADMA2 if it is available */
  232. sdhci_prepare_adma_table(priv->adma_desc_table, data,
  233. priv->dma_addr);
  234. adma_addr = virt_to_phys(priv->adma_desc_table);
  235. esdhc_write32(&regs->adsaddrl, lower_32_bits(adma_addr));
  236. if (IS_ENABLED(CONFIG_DMA_ADDR_T_64BIT))
  237. esdhc_write32(&regs->adsaddrh, upper_32_bits(adma_addr));
  238. esdhc_clrsetbits32(&regs->proctl, PROCTL_DMAS_MASK,
  239. PROCTL_DMAS_ADMA2);
  240. } else {
  241. debug("Using SDMA\n");
  242. if (upper_32_bits(priv->dma_addr))
  243. printf("Cannot use 64 bit addresses with SDMA\n");
  244. esdhc_write32(&regs->dsaddr, lower_32_bits(priv->dma_addr));
  245. esdhc_clrsetbits32(&regs->proctl, PROCTL_DMAS_MASK,
  246. PROCTL_DMAS_SDMA);
  247. }
  248. esdhc_write32(&regs->blkattr, data->blocks << 16 | data->blocksize);
  249. }
  250. static int esdhc_setup_data(struct fsl_esdhc_priv *priv, struct mmc *mmc,
  251. struct mmc_data *data)
  252. {
  253. int timeout;
  254. bool is_write = data->flags & MMC_DATA_WRITE;
  255. struct fsl_esdhc *regs = priv->esdhc_regs;
  256. if (is_write && !(esdhc_read32(&regs->prsstat) & PRSSTAT_WPSPL)) {
  257. printf("Can not write to locked SD card.\n");
  258. return -EINVAL;
  259. }
  260. if (IS_ENABLED(CONFIG_SYS_FSL_ESDHC_USE_PIO))
  261. esdhc_setup_watermark_level(priv, data);
  262. else
  263. esdhc_setup_dma(priv, data);
  264. /* Calculate the timeout period for data transactions */
  265. /*
  266. * 1)Timeout period = (2^(timeout+13)) SD Clock cycles
  267. * 2)Timeout period should be minimum 0.250sec as per SD Card spec
  268. * So, Number of SD Clock cycles for 0.25sec should be minimum
  269. * (SD Clock/sec * 0.25 sec) SD Clock cycles
  270. * = (mmc->clock * 1/4) SD Clock cycles
  271. * As 1) >= 2)
  272. * => (2^(timeout+13)) >= mmc->clock * 1/4
  273. * Taking log2 both the sides
  274. * => timeout + 13 >= log2(mmc->clock/4)
  275. * Rounding up to next power of 2
  276. * => timeout + 13 = log2(mmc->clock/4) + 1
  277. * => timeout + 13 = fls(mmc->clock/4)
  278. *
  279. * However, the MMC spec "It is strongly recommended for hosts to
  280. * implement more than 500ms timeout value even if the card
  281. * indicates the 250ms maximum busy length." Even the previous
  282. * value of 300ms is known to be insufficient for some cards.
  283. * So, we use
  284. * => timeout + 13 = fls(mmc->clock/2)
  285. */
  286. timeout = fls(mmc->clock/2);
  287. timeout -= 13;
  288. if (timeout > 14)
  289. timeout = 14;
  290. if (timeout < 0)
  291. timeout = 0;
  292. if (IS_ENABLED(CONFIG_SYS_FSL_ERRATUM_ESDHC_A001) &&
  293. (timeout == 4 || timeout == 8 || timeout == 12))
  294. timeout++;
  295. if (IS_ENABLED(ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE))
  296. timeout = 0xE;
  297. esdhc_clrsetbits32(&regs->sysctl, SYSCTL_TIMEOUT_MASK, timeout << 16);
  298. return 0;
  299. }
  300. /*
  301. * Sends a command out on the bus. Takes the mmc pointer,
  302. * a command pointer, and an optional data pointer.
  303. */
  304. static int esdhc_send_cmd_common(struct fsl_esdhc_priv *priv, struct mmc *mmc,
  305. struct mmc_cmd *cmd, struct mmc_data *data)
  306. {
  307. int err = 0;
  308. uint xfertyp;
  309. uint irqstat;
  310. u32 flags = IRQSTAT_CC | IRQSTAT_CTOE;
  311. struct fsl_esdhc *regs = priv->esdhc_regs;
  312. unsigned long start;
  313. if (IS_ENABLED(CONFIG_SYS_FSL_ERRATUM_ESDHC111) &&
  314. cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
  315. return 0;
  316. esdhc_write32(&regs->irqstat, -1);
  317. sync();
  318. /* Wait for the bus to be idle */
  319. while ((esdhc_read32(&regs->prsstat) & PRSSTAT_CICHB) ||
  320. (esdhc_read32(&regs->prsstat) & PRSSTAT_CIDHB))
  321. ;
  322. while (esdhc_read32(&regs->prsstat) & PRSSTAT_DLA)
  323. ;
  324. /* Set up for a data transfer if we have one */
  325. if (data) {
  326. err = esdhc_setup_data(priv, mmc, data);
  327. if(err)
  328. return err;
  329. }
  330. /* Figure out the transfer arguments */
  331. xfertyp = esdhc_xfertyp(cmd, data);
  332. /* Mask all irqs */
  333. esdhc_write32(&regs->irqsigen, 0);
  334. /* Send the command */
  335. esdhc_write32(&regs->cmdarg, cmd->cmdarg);
  336. esdhc_write32(&regs->xfertyp, xfertyp);
  337. if (cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK ||
  338. cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200)
  339. flags = IRQSTAT_BRR;
  340. /* Wait for the command to complete */
  341. start = get_timer(0);
  342. while (!(esdhc_read32(&regs->irqstat) & flags)) {
  343. if (get_timer(start) > 1000) {
  344. err = -ETIMEDOUT;
  345. goto out;
  346. }
  347. }
  348. irqstat = esdhc_read32(&regs->irqstat);
  349. if (irqstat & CMD_ERR) {
  350. err = -ECOMM;
  351. goto out;
  352. }
  353. if (irqstat & IRQSTAT_CTOE) {
  354. err = -ETIMEDOUT;
  355. goto out;
  356. }
  357. /* Workaround for ESDHC errata ENGcm03648 */
  358. if (!data && (cmd->resp_type & MMC_RSP_BUSY)) {
  359. int timeout = 6000;
  360. /* Poll on DATA0 line for cmd with busy signal for 600 ms */
  361. while (timeout > 0 && !(esdhc_read32(&regs->prsstat) &
  362. PRSSTAT_DAT0)) {
  363. udelay(100);
  364. timeout--;
  365. }
  366. if (timeout <= 0) {
  367. printf("Timeout waiting for DAT0 to go high!\n");
  368. err = -ETIMEDOUT;
  369. goto out;
  370. }
  371. }
  372. /* Copy the response to the response buffer */
  373. if (cmd->resp_type & MMC_RSP_136) {
  374. u32 cmdrsp3, cmdrsp2, cmdrsp1, cmdrsp0;
  375. cmdrsp3 = esdhc_read32(&regs->cmdrsp3);
  376. cmdrsp2 = esdhc_read32(&regs->cmdrsp2);
  377. cmdrsp1 = esdhc_read32(&regs->cmdrsp1);
  378. cmdrsp0 = esdhc_read32(&regs->cmdrsp0);
  379. cmd->response[0] = (cmdrsp3 << 8) | (cmdrsp2 >> 24);
  380. cmd->response[1] = (cmdrsp2 << 8) | (cmdrsp1 >> 24);
  381. cmd->response[2] = (cmdrsp1 << 8) | (cmdrsp0 >> 24);
  382. cmd->response[3] = (cmdrsp0 << 8);
  383. } else
  384. cmd->response[0] = esdhc_read32(&regs->cmdrsp0);
  385. /* Wait until all of the blocks are transferred */
  386. if (data) {
  387. if (IS_ENABLED(CONFIG_SYS_FSL_ESDHC_USE_PIO)) {
  388. esdhc_pio_read_write(priv, data);
  389. } else {
  390. flags = DATA_COMPLETE;
  391. if (cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK ||
  392. cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200)
  393. flags = IRQSTAT_BRR;
  394. do {
  395. irqstat = esdhc_read32(&regs->irqstat);
  396. if (irqstat & IRQSTAT_DTOE) {
  397. err = -ETIMEDOUT;
  398. goto out;
  399. }
  400. if (irqstat & DATA_ERR) {
  401. err = -ECOMM;
  402. goto out;
  403. }
  404. } while ((irqstat & flags) != flags);
  405. /*
  406. * Need invalidate the dcache here again to avoid any
  407. * cache-fill during the DMA operations such as the
  408. * speculative pre-fetching etc.
  409. */
  410. dma_unmap_single(priv->dma_addr,
  411. data->blocks * data->blocksize,
  412. mmc_get_dma_dir(data));
  413. }
  414. }
  415. out:
  416. /* Reset CMD and DATA portions on error */
  417. if (err) {
  418. esdhc_write32(&regs->sysctl, esdhc_read32(&regs->sysctl) |
  419. SYSCTL_RSTC);
  420. while (esdhc_read32(&regs->sysctl) & SYSCTL_RSTC)
  421. ;
  422. if (data) {
  423. esdhc_write32(&regs->sysctl,
  424. esdhc_read32(&regs->sysctl) |
  425. SYSCTL_RSTD);
  426. while ((esdhc_read32(&regs->sysctl) & SYSCTL_RSTD))
  427. ;
  428. }
  429. }
  430. esdhc_write32(&regs->irqstat, -1);
  431. return err;
  432. }
  433. static void set_sysctl(struct fsl_esdhc_priv *priv, struct mmc *mmc, uint clock)
  434. {
  435. struct fsl_esdhc *regs = priv->esdhc_regs;
  436. int div = 1;
  437. int pre_div = 2;
  438. unsigned int sdhc_clk = priv->sdhc_clk;
  439. u32 time_out;
  440. u32 value;
  441. uint clk;
  442. if (clock < mmc->cfg->f_min)
  443. clock = mmc->cfg->f_min;
  444. while (sdhc_clk / (16 * pre_div) > clock && pre_div < 256)
  445. pre_div *= 2;
  446. while (sdhc_clk / (div * pre_div) > clock && div < 16)
  447. div++;
  448. if (IS_ENABLED(CONFIG_SYS_FSL_ERRATUM_A011334) &&
  449. clock == 200000000 && mmc->selected_mode == MMC_HS_400) {
  450. u32 div_ratio = pre_div * div;
  451. if (div_ratio <= 4) {
  452. pre_div = 4;
  453. div = 1;
  454. } else if (div_ratio <= 8) {
  455. pre_div = 4;
  456. div = 2;
  457. } else if (div_ratio <= 12) {
  458. pre_div = 4;
  459. div = 3;
  460. } else {
  461. printf("unsupported clock division.\n");
  462. }
  463. }
  464. mmc->clock = sdhc_clk / pre_div / div;
  465. priv->clock = mmc->clock;
  466. pre_div >>= 1;
  467. div -= 1;
  468. clk = (pre_div << 8) | (div << 4);
  469. esdhc_clrbits32(&regs->sysctl, SYSCTL_CKEN);
  470. esdhc_clrsetbits32(&regs->sysctl, SYSCTL_CLOCK_MASK, clk);
  471. time_out = 20;
  472. value = PRSSTAT_SDSTB;
  473. while (!(esdhc_read32(&regs->prsstat) & value)) {
  474. if (time_out == 0) {
  475. printf("fsl_esdhc: Internal clock never stabilised.\n");
  476. break;
  477. }
  478. time_out--;
  479. mdelay(1);
  480. }
  481. esdhc_setbits32(&regs->sysctl, SYSCTL_PEREN | SYSCTL_CKEN);
  482. }
  483. static void esdhc_clock_control(struct fsl_esdhc_priv *priv, bool enable)
  484. {
  485. struct fsl_esdhc *regs = priv->esdhc_regs;
  486. u32 value;
  487. u32 time_out;
  488. value = esdhc_read32(&regs->sysctl);
  489. if (enable)
  490. value |= SYSCTL_CKEN;
  491. else
  492. value &= ~SYSCTL_CKEN;
  493. esdhc_write32(&regs->sysctl, value);
  494. time_out = 20;
  495. value = PRSSTAT_SDSTB;
  496. while (!(esdhc_read32(&regs->prsstat) & value)) {
  497. if (time_out == 0) {
  498. printf("fsl_esdhc: Internal clock never stabilised.\n");
  499. break;
  500. }
  501. time_out--;
  502. mdelay(1);
  503. }
  504. }
  505. static void esdhc_flush_async_fifo(struct fsl_esdhc_priv *priv)
  506. {
  507. struct fsl_esdhc *regs = priv->esdhc_regs;
  508. u32 time_out;
  509. esdhc_setbits32(&regs->esdhcctl, ESDHCCTL_FAF);
  510. time_out = 20;
  511. while (esdhc_read32(&regs->esdhcctl) & ESDHCCTL_FAF) {
  512. if (time_out == 0) {
  513. printf("fsl_esdhc: Flush asynchronous FIFO timeout.\n");
  514. break;
  515. }
  516. time_out--;
  517. mdelay(1);
  518. }
  519. }
  520. static void esdhc_tuning_block_enable(struct fsl_esdhc_priv *priv,
  521. bool en)
  522. {
  523. struct fsl_esdhc *regs = priv->esdhc_regs;
  524. esdhc_clock_control(priv, false);
  525. esdhc_flush_async_fifo(priv);
  526. if (en)
  527. esdhc_setbits32(&regs->tbctl, TBCTL_TB_EN);
  528. else
  529. esdhc_clrbits32(&regs->tbctl, TBCTL_TB_EN);
  530. esdhc_clock_control(priv, true);
  531. }
  532. static void esdhc_exit_hs400(struct fsl_esdhc_priv *priv)
  533. {
  534. struct fsl_esdhc *regs = priv->esdhc_regs;
  535. esdhc_clrbits32(&regs->sdtimingctl, FLW_CTL_BG);
  536. esdhc_clrbits32(&regs->sdclkctl, CMD_CLK_CTL);
  537. esdhc_clock_control(priv, false);
  538. esdhc_clrbits32(&regs->tbctl, HS400_MODE);
  539. esdhc_clock_control(priv, true);
  540. esdhc_clrbits32(&regs->dllcfg0, DLL_FREQ_SEL | DLL_ENABLE);
  541. esdhc_clrbits32(&regs->tbctl, HS400_WNDW_ADJUST);
  542. esdhc_tuning_block_enable(priv, false);
  543. }
  544. static int esdhc_set_timing(struct fsl_esdhc_priv *priv, enum bus_mode mode)
  545. {
  546. struct fsl_esdhc *regs = priv->esdhc_regs;
  547. ulong start;
  548. u32 val;
  549. /* Exit HS400 mode before setting any other mode */
  550. if (esdhc_read32(&regs->tbctl) & HS400_MODE &&
  551. mode != MMC_HS_400)
  552. esdhc_exit_hs400(priv);
  553. esdhc_clock_control(priv, false);
  554. if (mode == MMC_HS_200)
  555. esdhc_clrsetbits32(&regs->autoc12err, UHSM_MASK,
  556. UHSM_SDR104_HS200);
  557. if (mode == MMC_HS_400) {
  558. esdhc_setbits32(&regs->tbctl, HS400_MODE);
  559. esdhc_setbits32(&regs->sdclkctl, CMD_CLK_CTL);
  560. esdhc_clock_control(priv, true);
  561. if (priv->clock == 200000000)
  562. esdhc_setbits32(&regs->dllcfg0, DLL_FREQ_SEL);
  563. esdhc_setbits32(&regs->dllcfg0, DLL_ENABLE);
  564. esdhc_setbits32(&regs->dllcfg0, DLL_RESET);
  565. udelay(1);
  566. esdhc_clrbits32(&regs->dllcfg0, DLL_RESET);
  567. start = get_timer(0);
  568. val = DLL_STS_SLV_LOCK;
  569. while (!(esdhc_read32(&regs->dllstat0) & val)) {
  570. if (get_timer(start) > 1000) {
  571. printf("fsl_esdhc: delay chain lock timeout\n");
  572. return -ETIMEDOUT;
  573. }
  574. }
  575. esdhc_setbits32(&regs->tbctl, HS400_WNDW_ADJUST);
  576. esdhc_clock_control(priv, false);
  577. esdhc_flush_async_fifo(priv);
  578. }
  579. esdhc_clock_control(priv, true);
  580. return 0;
  581. }
  582. static int esdhc_set_ios_common(struct fsl_esdhc_priv *priv, struct mmc *mmc)
  583. {
  584. struct fsl_esdhc *regs = priv->esdhc_regs;
  585. int ret;
  586. if (priv->is_sdhc_per_clk) {
  587. /* Select to use peripheral clock */
  588. esdhc_clock_control(priv, false);
  589. esdhc_setbits32(&regs->esdhcctl, ESDHCCTL_PCS);
  590. esdhc_clock_control(priv, true);
  591. }
  592. if (mmc->selected_mode == MMC_HS_400)
  593. esdhc_tuning_block_enable(priv, true);
  594. /* Set the clock speed */
  595. if (priv->clock != mmc->clock)
  596. set_sysctl(priv, mmc, mmc->clock);
  597. /* Set timing */
  598. ret = esdhc_set_timing(priv, mmc->selected_mode);
  599. if (ret)
  600. return ret;
  601. /* Set the bus width */
  602. esdhc_clrbits32(&regs->proctl, PROCTL_DTW_4 | PROCTL_DTW_8);
  603. if (mmc->bus_width == 4)
  604. esdhc_setbits32(&regs->proctl, PROCTL_DTW_4);
  605. else if (mmc->bus_width == 8)
  606. esdhc_setbits32(&regs->proctl, PROCTL_DTW_8);
  607. return 0;
  608. }
  609. static void esdhc_enable_cache_snooping(struct fsl_esdhc *regs)
  610. {
  611. #ifdef CONFIG_ARCH_MPC830X
  612. immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
  613. sysconf83xx_t *sysconf = &immr->sysconf;
  614. setbits_be32(&sysconf->sdhccr, 0x02000000);
  615. #else
  616. esdhc_write32(&regs->esdhcctl, 0x00000040);
  617. #endif
  618. }
  619. static int esdhc_init_common(struct fsl_esdhc_priv *priv, struct mmc *mmc)
  620. {
  621. struct fsl_esdhc *regs = priv->esdhc_regs;
  622. ulong start;
  623. /* Reset the entire host controller */
  624. esdhc_setbits32(&regs->sysctl, SYSCTL_RSTA);
  625. /* Wait until the controller is available */
  626. start = get_timer(0);
  627. while ((esdhc_read32(&regs->sysctl) & SYSCTL_RSTA)) {
  628. if (get_timer(start) > 1000)
  629. return -ETIMEDOUT;
  630. }
  631. /* Clean TBCTL[TB_EN] which is not able to be reset by reset all */
  632. esdhc_clrbits32(&regs->tbctl, TBCTL_TB_EN);
  633. esdhc_enable_cache_snooping(regs);
  634. esdhc_setbits32(&regs->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN);
  635. /* Set the initial clock speed */
  636. set_sysctl(priv, mmc, 400000);
  637. /* Disable the BRR and BWR bits in IRQSTAT */
  638. esdhc_clrbits32(&regs->irqstaten, IRQSTATEN_BRR | IRQSTATEN_BWR);
  639. /* Put the PROCTL reg back to the default */
  640. esdhc_write32(&regs->proctl, PROCTL_INIT);
  641. /* Set timout to the maximum value */
  642. esdhc_clrsetbits32(&regs->sysctl, SYSCTL_TIMEOUT_MASK, 14 << 16);
  643. if (IS_ENABLED(CONFIG_SYS_FSL_ESDHC_UNRELIABLE_PULSE_DETECTION_WORKAROUND))
  644. esdhc_clrbits32(&regs->dllcfg1, DLL_PD_PULSE_STRETCH_SEL);
  645. return 0;
  646. }
  647. static int esdhc_getcd_common(struct fsl_esdhc_priv *priv)
  648. {
  649. struct fsl_esdhc *regs = priv->esdhc_regs;
  650. #ifdef CONFIG_ESDHC_DETECT_QUIRK
  651. if (CONFIG_ESDHC_DETECT_QUIRK)
  652. return 1;
  653. #endif
  654. if (esdhc_read32(&regs->prsstat) & PRSSTAT_CINS)
  655. return 1;
  656. return 0;
  657. }
  658. static void fsl_esdhc_get_cfg_common(struct fsl_esdhc_priv *priv,
  659. struct mmc_config *cfg)
  660. {
  661. struct fsl_esdhc *regs = priv->esdhc_regs;
  662. u32 caps;
  663. caps = esdhc_read32(&regs->hostcapblt);
  664. /*
  665. * For eSDHC, power supply is through peripheral circuit. Some eSDHC
  666. * versions have value 0 of the bit but that does not reflect the
  667. * truth. 3.3V is common for SD/MMC, and is supported for all boards
  668. * with eSDHC in current u-boot. So, make 3.3V is supported in
  669. * default in code. CONFIG_FSL_ESDHC_VS33_NOT_SUPPORT can be enabled
  670. * if future board does not support 3.3V.
  671. */
  672. caps |= HOSTCAPBLT_VS33;
  673. if (IS_ENABLED(CONFIG_FSL_ESDHC_VS33_NOT_SUPPORT))
  674. caps &= ~HOSTCAPBLT_VS33;
  675. if (IS_ENABLED(CONFIG_SYS_FSL_ERRATUM_ESDHC135))
  676. caps &= ~(HOSTCAPBLT_SRS | HOSTCAPBLT_VS18 | HOSTCAPBLT_VS30);
  677. if (caps & HOSTCAPBLT_VS18)
  678. cfg->voltages |= MMC_VDD_165_195;
  679. if (caps & HOSTCAPBLT_VS30)
  680. cfg->voltages |= MMC_VDD_29_30 | MMC_VDD_30_31;
  681. if (caps & HOSTCAPBLT_VS33)
  682. cfg->voltages |= MMC_VDD_32_33 | MMC_VDD_33_34;
  683. cfg->name = "FSL_SDHC";
  684. if (caps & HOSTCAPBLT_HSS)
  685. cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
  686. cfg->f_min = 400000;
  687. cfg->f_max = min(priv->sdhc_clk, (u32)200000000);
  688. cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
  689. }
  690. #ifdef CONFIG_OF_LIBFDT
  691. __weak int esdhc_status_fixup(void *blob, const char *compat)
  692. {
  693. if (IS_ENABLED(CONFIG_FSL_ESDHC_PIN_MUX) && !hwconfig("esdhc")) {
  694. do_fixup_by_compat(blob, compat, "status", "disabled",
  695. sizeof("disabled"), 1);
  696. return 1;
  697. }
  698. return 0;
  699. }
  700. #if CONFIG_IS_ENABLED(DM_MMC)
  701. static int fsl_esdhc_get_cd(struct udevice *dev);
  702. static void esdhc_disable_for_no_card(void *blob)
  703. {
  704. struct udevice *dev;
  705. for (uclass_first_device(UCLASS_MMC, &dev);
  706. dev;
  707. uclass_next_device(&dev)) {
  708. char esdhc_path[50];
  709. if (fsl_esdhc_get_cd(dev))
  710. continue;
  711. snprintf(esdhc_path, sizeof(esdhc_path), "/soc/esdhc@%lx",
  712. (unsigned long)dev_read_addr(dev));
  713. do_fixup_by_path(blob, esdhc_path, "status", "disabled",
  714. sizeof("disabled"), 1);
  715. }
  716. }
  717. #else
  718. static void esdhc_disable_for_no_card(void *blob)
  719. {
  720. }
  721. #endif
  722. void fdt_fixup_esdhc(void *blob, struct bd_info *bd)
  723. {
  724. const char *compat = "fsl,esdhc";
  725. if (esdhc_status_fixup(blob, compat))
  726. return;
  727. if (IS_ENABLED(CONFIG_FSL_ESDHC_33V_IO_RELIABILITY_WORKAROUND))
  728. esdhc_disable_for_no_card(blob);
  729. do_fixup_by_compat_u32(blob, compat, "clock-frequency",
  730. gd->arch.sdhc_clk, 1);
  731. }
  732. #endif
  733. #if !CONFIG_IS_ENABLED(DM_MMC)
  734. static int esdhc_getcd(struct mmc *mmc)
  735. {
  736. struct fsl_esdhc_priv *priv = mmc->priv;
  737. return esdhc_getcd_common(priv);
  738. }
  739. static int esdhc_init(struct mmc *mmc)
  740. {
  741. struct fsl_esdhc_priv *priv = mmc->priv;
  742. return esdhc_init_common(priv, mmc);
  743. }
  744. static int esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
  745. struct mmc_data *data)
  746. {
  747. struct fsl_esdhc_priv *priv = mmc->priv;
  748. return esdhc_send_cmd_common(priv, mmc, cmd, data);
  749. }
  750. static int esdhc_set_ios(struct mmc *mmc)
  751. {
  752. struct fsl_esdhc_priv *priv = mmc->priv;
  753. return esdhc_set_ios_common(priv, mmc);
  754. }
  755. static const struct mmc_ops esdhc_ops = {
  756. .getcd = esdhc_getcd,
  757. .init = esdhc_init,
  758. .send_cmd = esdhc_send_cmd,
  759. .set_ios = esdhc_set_ios,
  760. };
  761. int fsl_esdhc_initialize(struct bd_info *bis, struct fsl_esdhc_cfg *cfg)
  762. {
  763. struct fsl_esdhc_plat *plat;
  764. struct fsl_esdhc_priv *priv;
  765. struct mmc_config *mmc_cfg;
  766. struct mmc *mmc;
  767. if (!cfg)
  768. return -EINVAL;
  769. priv = calloc(sizeof(struct fsl_esdhc_priv), 1);
  770. if (!priv)
  771. return -ENOMEM;
  772. plat = calloc(sizeof(struct fsl_esdhc_plat), 1);
  773. if (!plat) {
  774. free(priv);
  775. return -ENOMEM;
  776. }
  777. priv->esdhc_regs = (struct fsl_esdhc *)(unsigned long)(cfg->esdhc_base);
  778. priv->sdhc_clk = cfg->sdhc_clk;
  779. if (gd->arch.sdhc_per_clk)
  780. priv->is_sdhc_per_clk = true;
  781. mmc_cfg = &plat->cfg;
  782. if (cfg->max_bus_width == 8) {
  783. mmc_cfg->host_caps |= MMC_MODE_1BIT | MMC_MODE_4BIT |
  784. MMC_MODE_8BIT;
  785. } else if (cfg->max_bus_width == 4) {
  786. mmc_cfg->host_caps |= MMC_MODE_1BIT | MMC_MODE_4BIT;
  787. } else if (cfg->max_bus_width == 1) {
  788. mmc_cfg->host_caps |= MMC_MODE_1BIT;
  789. } else {
  790. mmc_cfg->host_caps |= MMC_MODE_1BIT | MMC_MODE_4BIT |
  791. MMC_MODE_8BIT;
  792. printf("No max bus width provided. Assume 8-bit supported.\n");
  793. }
  794. if (IS_ENABLED(CONFIG_ESDHC_DETECT_8_BIT_QUIRK))
  795. mmc_cfg->host_caps &= ~MMC_MODE_8BIT;
  796. mmc_cfg->ops = &esdhc_ops;
  797. fsl_esdhc_get_cfg_common(priv, mmc_cfg);
  798. mmc = mmc_create(mmc_cfg, priv);
  799. if (!mmc)
  800. return -EIO;
  801. priv->mmc = mmc;
  802. return 0;
  803. }
  804. int fsl_esdhc_mmc_init(struct bd_info *bis)
  805. {
  806. struct fsl_esdhc_cfg *cfg;
  807. cfg = calloc(sizeof(struct fsl_esdhc_cfg), 1);
  808. cfg->esdhc_base = CONFIG_SYS_FSL_ESDHC_ADDR;
  809. /* Prefer peripheral clock which provides higher frequency. */
  810. if (gd->arch.sdhc_per_clk)
  811. cfg->sdhc_clk = gd->arch.sdhc_per_clk;
  812. else
  813. cfg->sdhc_clk = gd->arch.sdhc_clk;
  814. return fsl_esdhc_initialize(bis, cfg);
  815. }
  816. #else /* DM_MMC */
  817. static int fsl_esdhc_probe(struct udevice *dev)
  818. {
  819. struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
  820. struct fsl_esdhc_plat *plat = dev_get_plat(dev);
  821. struct fsl_esdhc_priv *priv = dev_get_priv(dev);
  822. u32 caps, hostver;
  823. fdt_addr_t addr;
  824. struct mmc *mmc;
  825. int ret;
  826. addr = dev_read_addr(dev);
  827. if (addr == FDT_ADDR_T_NONE)
  828. return -EINVAL;
  829. #ifdef CONFIG_PPC
  830. priv->esdhc_regs = (struct fsl_esdhc *)lower_32_bits(addr);
  831. #else
  832. priv->esdhc_regs = (struct fsl_esdhc *)addr;
  833. #endif
  834. priv->dev = dev;
  835. if (IS_ENABLED(CONFIG_FSL_ESDHC_SUPPORT_ADMA2)) {
  836. /*
  837. * Only newer eSDHC controllers can do ADMA2 if the ADMA flag
  838. * is set in the host capabilities register.
  839. */
  840. caps = esdhc_read32(&priv->esdhc_regs->hostcapblt);
  841. hostver = esdhc_read32(&priv->esdhc_regs->hostver);
  842. if (caps & HOSTCAPBLT_DMAS &&
  843. HOSTVER_VENDOR(hostver) > VENDOR_V_22) {
  844. priv->adma_desc_table = sdhci_adma_init();
  845. if (!priv->adma_desc_table)
  846. debug("Could not allocate ADMA tables, falling back to SDMA\n");
  847. }
  848. }
  849. if (gd->arch.sdhc_per_clk) {
  850. priv->sdhc_clk = gd->arch.sdhc_per_clk;
  851. priv->is_sdhc_per_clk = true;
  852. } else {
  853. priv->sdhc_clk = gd->arch.sdhc_clk;
  854. }
  855. if (priv->sdhc_clk <= 0) {
  856. dev_err(dev, "Unable to get clk for %s\n", dev->name);
  857. return -EINVAL;
  858. }
  859. fsl_esdhc_get_cfg_common(priv, &plat->cfg);
  860. mmc_of_parse(dev, &plat->cfg);
  861. mmc = &plat->mmc;
  862. mmc->cfg = &plat->cfg;
  863. mmc->dev = dev;
  864. upriv->mmc = mmc;
  865. ret = esdhc_init_common(priv, mmc);
  866. if (ret)
  867. return ret;
  868. if (IS_ENABLED(CONFIG_FSL_ESDHC_33V_IO_RELIABILITY_WORKAROUND) &&
  869. !fsl_esdhc_get_cd(dev))
  870. esdhc_setbits32(&priv->esdhc_regs->proctl, PROCTL_VOLT_SEL);
  871. return 0;
  872. }
  873. static int fsl_esdhc_get_cd(struct udevice *dev)
  874. {
  875. struct fsl_esdhc_plat *plat = dev_get_plat(dev);
  876. struct fsl_esdhc_priv *priv = dev_get_priv(dev);
  877. if (plat->cfg.host_caps & MMC_CAP_NONREMOVABLE)
  878. return 1;
  879. return esdhc_getcd_common(priv);
  880. }
  881. static int fsl_esdhc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
  882. struct mmc_data *data)
  883. {
  884. struct fsl_esdhc_plat *plat = dev_get_plat(dev);
  885. struct fsl_esdhc_priv *priv = dev_get_priv(dev);
  886. return esdhc_send_cmd_common(priv, &plat->mmc, cmd, data);
  887. }
  888. static int fsl_esdhc_set_ios(struct udevice *dev)
  889. {
  890. struct fsl_esdhc_plat *plat = dev_get_plat(dev);
  891. struct fsl_esdhc_priv *priv = dev_get_priv(dev);
  892. return esdhc_set_ios_common(priv, &plat->mmc);
  893. }
  894. static int fsl_esdhc_reinit(struct udevice *dev)
  895. {
  896. struct fsl_esdhc_plat *plat = dev_get_plat(dev);
  897. struct fsl_esdhc_priv *priv = dev_get_priv(dev);
  898. return esdhc_init_common(priv, &plat->mmc);
  899. }
  900. #ifdef MMC_SUPPORTS_TUNING
  901. static int fsl_esdhc_execute_tuning(struct udevice *dev, uint32_t opcode)
  902. {
  903. struct fsl_esdhc_plat *plat = dev_get_plat(dev);
  904. struct fsl_esdhc_priv *priv = dev_get_priv(dev);
  905. struct fsl_esdhc *regs = priv->esdhc_regs;
  906. struct mmc *mmc = &plat->mmc;
  907. u32 val, irqstaten;
  908. int i;
  909. if (IS_ENABLED(CONFIG_SYS_FSL_ERRATUM_A011334) &&
  910. plat->mmc.hs400_tuning)
  911. set_sysctl(priv, mmc, mmc->clock);
  912. esdhc_tuning_block_enable(priv, true);
  913. esdhc_setbits32(&regs->autoc12err, EXECUTE_TUNING);
  914. irqstaten = esdhc_read32(&regs->irqstaten);
  915. esdhc_write32(&regs->irqstaten, IRQSTATEN_BRR);
  916. for (i = 0; i < MAX_TUNING_LOOP; i++) {
  917. mmc_send_tuning(mmc, opcode, NULL);
  918. mdelay(1);
  919. val = esdhc_read32(&regs->autoc12err);
  920. if (!(val & EXECUTE_TUNING)) {
  921. if (val & SMPCLKSEL)
  922. break;
  923. }
  924. }
  925. esdhc_write32(&regs->irqstaten, irqstaten);
  926. if (i != MAX_TUNING_LOOP) {
  927. if (plat->mmc.hs400_tuning)
  928. esdhc_setbits32(&regs->sdtimingctl, FLW_CTL_BG);
  929. return 0;
  930. }
  931. printf("fsl_esdhc: tuning failed!\n");
  932. esdhc_clrbits32(&regs->autoc12err, SMPCLKSEL);
  933. esdhc_clrbits32(&regs->autoc12err, EXECUTE_TUNING);
  934. esdhc_tuning_block_enable(priv, false);
  935. return -ETIMEDOUT;
  936. }
  937. #endif
  938. int fsl_esdhc_hs400_prepare_ddr(struct udevice *dev)
  939. {
  940. struct fsl_esdhc_priv *priv = dev_get_priv(dev);
  941. esdhc_tuning_block_enable(priv, false);
  942. return 0;
  943. }
  944. static const struct dm_mmc_ops fsl_esdhc_ops = {
  945. .get_cd = fsl_esdhc_get_cd,
  946. .send_cmd = fsl_esdhc_send_cmd,
  947. .set_ios = fsl_esdhc_set_ios,
  948. #ifdef MMC_SUPPORTS_TUNING
  949. .execute_tuning = fsl_esdhc_execute_tuning,
  950. #endif
  951. .reinit = fsl_esdhc_reinit,
  952. .hs400_prepare_ddr = fsl_esdhc_hs400_prepare_ddr,
  953. };
  954. static const struct udevice_id fsl_esdhc_ids[] = {
  955. { .compatible = "fsl,esdhc", },
  956. { /* sentinel */ }
  957. };
  958. static int fsl_esdhc_bind(struct udevice *dev)
  959. {
  960. struct fsl_esdhc_plat *plat = dev_get_plat(dev);
  961. return mmc_bind(dev, &plat->mmc, &plat->cfg);
  962. }
  963. U_BOOT_DRIVER(fsl_esdhc) = {
  964. .name = "fsl-esdhc-mmc",
  965. .id = UCLASS_MMC,
  966. .of_match = fsl_esdhc_ids,
  967. .ops = &fsl_esdhc_ops,
  968. .bind = fsl_esdhc_bind,
  969. .probe = fsl_esdhc_probe,
  970. .plat_auto = sizeof(struct fsl_esdhc_plat),
  971. .priv_auto = sizeof(struct fsl_esdhc_priv),
  972. };
  973. #endif