tlb.c 3.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2013-2015 Arcturus Networks, Inc
  4. * http://www.arcturusnetworks.com/products/ucp1020/
  5. * based on board/freescale/p1_p2_rdb_pc/tlb.c
  6. * original copyright follows:
  7. * Copyright 2010-2011 Freescale Semiconductor, Inc.
  8. */
  9. #include <common.h>
  10. #include <asm/mmu.h>
  11. struct fsl_e_tlb_entry tlb_table[] = {
  12. /* TLB 0 - for temp stack in cache */
  13. SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
  14. CONFIG_SYS_INIT_RAM_ADDR_PHYS,
  15. MAS3_SX | MAS3_SW | MAS3_SR, 0,
  16. 0, 0, BOOKE_PAGESZ_4K, 0),
  17. SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
  18. CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
  19. MAS3_SX | MAS3_SW | MAS3_SR, 0,
  20. 0, 0, BOOKE_PAGESZ_4K, 0),
  21. SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
  22. CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
  23. MAS3_SX | MAS3_SW | MAS3_SR, 0,
  24. 0, 0, BOOKE_PAGESZ_4K, 0),
  25. SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
  26. CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
  27. MAS3_SX | MAS3_SW | MAS3_SR, 0,
  28. 0, 0, BOOKE_PAGESZ_4K, 0),
  29. /* TLB 1 */
  30. /* *I*** - Covers boot page */
  31. SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
  32. MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I,
  33. 0, 0, BOOKE_PAGESZ_4K, 1),
  34. /* *I*G* - CCSRBAR */
  35. SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
  36. MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
  37. 0, 1, BOOKE_PAGESZ_1M, 1),
  38. #ifndef CONFIG_SPL_BUILD
  39. /* W**G* - Flash/promjet, localbus */
  40. /* This will be changed to *I*G* after relocation to RAM. */
  41. SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
  42. MAS3_SX | MAS3_SR, MAS2_W | MAS2_G,
  43. 0, 2, BOOKE_PAGESZ_64M, 1),
  44. #ifdef CONFIG_PCI
  45. /* *I*G* - PCI memory 1.5G */
  46. SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
  47. MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
  48. 0, 3, BOOKE_PAGESZ_1G, 1),
  49. /* *I*G* - PCI I/O effective: 192K */
  50. SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
  51. MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
  52. 0, 4, BOOKE_PAGESZ_256K, 1),
  53. #endif
  54. #ifdef CONFIG_VSC7385_ENET
  55. /* *I*G - VSC7385 Switch */
  56. SET_TLB_ENTRY(1, CONFIG_SYS_VSC7385_BASE, CONFIG_SYS_VSC7385_BASE_PHYS,
  57. MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
  58. 0, 5, BOOKE_PAGESZ_1M, 1),
  59. #endif
  60. #endif /* not SPL */
  61. #ifdef CONFIG_SYS_NAND_BASE
  62. /* *I*G - NAND */
  63. SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
  64. MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
  65. 0, 7, BOOKE_PAGESZ_1M, 1),
  66. #endif
  67. #if defined(CONFIG_SYS_RAMBOOT) || \
  68. (defined(CONFIG_SPL) && !defined(CONFIG_SPL_COMMON_INIT_DDR))
  69. /* *I*G - eSDHC/eSPI/NAND boot */
  70. SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
  71. MAS3_SX | MAS3_SW | MAS3_SR, MAS2_M,
  72. 0, 8, BOOKE_PAGESZ_1G, 1),
  73. #endif /* RAMBOOT/SPL */
  74. #ifdef CONFIG_SYS_INIT_L2_ADDR
  75. /* *I*G - L2SRAM */
  76. SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS,
  77. MAS3_SX | MAS3_SW | MAS3_SR, MAS2_G,
  78. 0, 11, BOOKE_PAGESZ_256K, 1),
  79. #if CONFIG_SYS_L2_SIZE >= (256 << 10)
  80. SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR + 0x40000,
  81. CONFIG_SYS_INIT_L2_ADDR_PHYS + 0x40000,
  82. MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
  83. 0, 12, BOOKE_PAGESZ_256K, 1)
  84. #endif
  85. #endif
  86. };
  87. int num_tlb_entries = ARRAY_SIZE(tlb_table);