tpm-v2.h 15 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Defines APIs and structures that allow software to interact with a
  4. * TPM2 device
  5. *
  6. * Copyright (c) 2020 Linaro
  7. * Copyright (c) 2018 Bootlin
  8. *
  9. * https://trustedcomputinggroup.org/resource/tss-overview-common-structures-specification/
  10. *
  11. * Author: Miquel Raynal <miquel.raynal@bootlin.com>
  12. */
  13. #ifndef __TPM_V2_H
  14. #define __TPM_V2_H
  15. #include <tpm-common.h>
  16. struct udevice;
  17. #define TPM2_DIGEST_LEN 32
  18. #define TPM2_SHA1_DIGEST_SIZE 20
  19. #define TPM2_SHA256_DIGEST_SIZE 32
  20. #define TPM2_SHA384_DIGEST_SIZE 48
  21. #define TPM2_SHA512_DIGEST_SIZE 64
  22. #define TPM2_SM3_256_DIGEST_SIZE 32
  23. #define TPM2_MAX_PCRS 32
  24. #define TPM2_PCR_SELECT_MAX ((TPM2_MAX_PCRS + 7) / 8)
  25. #define TPM2_MAX_CAP_BUFFER 1024
  26. #define TPM2_MAX_TPM_PROPERTIES ((TPM2_MAX_CAP_BUFFER - sizeof(u32) /* TPM2_CAP */ - \
  27. sizeof(u32)) / sizeof(struct tpms_tagged_property))
  28. /*
  29. * We deviate from this draft of the specification by increasing the value of
  30. * TPM2_NUM_PCR_BANKS from 3 to 16 to ensure compatibility with TPM2
  31. * implementations that have enabled a larger than typical number of PCR
  32. * banks. This larger value for TPM2_NUM_PCR_BANKS is expected to be included
  33. * in a future revision of the specification.
  34. */
  35. #define TPM2_NUM_PCR_BANKS 16
  36. /* Definition of (UINT32) TPM2_CAP Constants */
  37. #define TPM2_CAP_PCRS 0x00000005U
  38. #define TPM2_CAP_TPM_PROPERTIES 0x00000006U
  39. /* Definition of (UINT32) TPM2_PT Constants */
  40. #define TPM2_PT_GROUP (u32)(0x00000100)
  41. #define TPM2_PT_FIXED (u32)(TPM2_PT_GROUP * 1)
  42. #define TPM2_PT_MANUFACTURER (u32)(TPM2_PT_FIXED + 5)
  43. #define TPM2_PT_PCR_COUNT (u32)(TPM2_PT_FIXED + 18)
  44. #define TPM2_PT_MAX_COMMAND_SIZE (u32)(TPM2_PT_FIXED + 30)
  45. #define TPM2_PT_MAX_RESPONSE_SIZE (u32)(TPM2_PT_FIXED + 31)
  46. /* event types */
  47. #define EV_POST_CODE ((u32)0x00000001)
  48. #define EV_NO_ACTION ((u32)0x00000003)
  49. #define EV_SEPARATOR ((u32)0x00000004)
  50. #define EV_S_CRTM_CONTENTS ((u32)0x00000007)
  51. #define EV_S_CRTM_VERSION ((u32)0x00000008)
  52. #define EV_CPU_MICROCODE ((u32)0x00000009)
  53. #define EV_TABLE_OF_DEVICES ((u32)0x0000000B)
  54. /* TPMS_TAGGED_PROPERTY Structure */
  55. struct tpms_tagged_property {
  56. u32 property;
  57. u32 value;
  58. } __packed;
  59. /* TPMS_PCR_SELECTION Structure */
  60. struct tpms_pcr_selection {
  61. u16 hash;
  62. u8 size_of_select;
  63. u8 pcr_select[TPM2_PCR_SELECT_MAX];
  64. } __packed;
  65. /* TPML_PCR_SELECTION Structure */
  66. struct tpml_pcr_selection {
  67. u32 count;
  68. struct tpms_pcr_selection selection[TPM2_NUM_PCR_BANKS];
  69. } __packed;
  70. /* TPML_TAGGED_TPM_PROPERTY Structure */
  71. struct tpml_tagged_tpm_property {
  72. u32 count;
  73. struct tpms_tagged_property tpm_property[TPM2_MAX_TPM_PROPERTIES];
  74. } __packed;
  75. /* TPMU_CAPABILITIES Union */
  76. union tpmu_capabilities {
  77. /*
  78. * Non exhaustive. Only added the structs needed for our
  79. * current code
  80. */
  81. struct tpml_pcr_selection assigned_pcr;
  82. struct tpml_tagged_tpm_property tpm_properties;
  83. } __packed;
  84. /* TPMS_CAPABILITY_DATA Structure */
  85. struct tpms_capability_data {
  86. u32 capability;
  87. union tpmu_capabilities data;
  88. } __packed;
  89. /**
  90. * SHA1 Event Log Entry Format
  91. *
  92. * @pcr_index: PCRIndex event extended to
  93. * @event_type: Type of event (see EFI specs)
  94. * @digest: Value extended into PCR index
  95. * @event_size: Size of event
  96. * @event: Event data
  97. */
  98. struct tcg_pcr_event {
  99. u32 pcr_index;
  100. u32 event_type;
  101. u8 digest[TPM2_SHA1_DIGEST_SIZE];
  102. u32 event_size;
  103. u8 event[];
  104. } __packed;
  105. /**
  106. * Definition of TPMU_HA Union
  107. */
  108. union tmpu_ha {
  109. u8 sha1[TPM2_SHA1_DIGEST_SIZE];
  110. u8 sha256[TPM2_SHA256_DIGEST_SIZE];
  111. u8 sm3_256[TPM2_SM3_256_DIGEST_SIZE];
  112. u8 sha384[TPM2_SHA384_DIGEST_SIZE];
  113. u8 sha512[TPM2_SHA512_DIGEST_SIZE];
  114. } __packed;
  115. /**
  116. * Definition of TPMT_HA Structure
  117. *
  118. * @hash_alg: Hash algorithm defined in enum tpm2_algorithms
  119. * @digest: Digest value for a given algorithm
  120. */
  121. struct tpmt_ha {
  122. u16 hash_alg;
  123. union tmpu_ha digest;
  124. } __packed;
  125. /**
  126. * Definition of TPML_DIGEST_VALUES Structure
  127. *
  128. * @count: Number of algorithms supported by hardware
  129. * @digests: struct for algorithm id and hash value
  130. */
  131. struct tpml_digest_values {
  132. u32 count;
  133. struct tpmt_ha digests[TPM2_NUM_PCR_BANKS];
  134. } __packed;
  135. /**
  136. * Crypto Agile Log Entry Format
  137. *
  138. * @pcr_index: PCRIndex event extended to
  139. * @event_type: Type of event
  140. * @digests: List of digestsextended to PCR index
  141. * @event_size: Size of the event data
  142. * @event: Event data
  143. */
  144. struct tcg_pcr_event2 {
  145. u32 pcr_index;
  146. u32 event_type;
  147. struct tpml_digest_values digests;
  148. u32 event_size;
  149. u8 event[];
  150. } __packed;
  151. /**
  152. * TPM2 Structure Tags for command/response buffers.
  153. *
  154. * @TPM2_ST_NO_SESSIONS: the command does not need an authentication.
  155. * @TPM2_ST_SESSIONS: the command needs an authentication.
  156. */
  157. enum tpm2_structures {
  158. TPM2_ST_NO_SESSIONS = 0x8001,
  159. TPM2_ST_SESSIONS = 0x8002,
  160. };
  161. /**
  162. * TPM2 type of boolean.
  163. */
  164. enum tpm2_yes_no {
  165. TPMI_YES = 1,
  166. TPMI_NO = 0,
  167. };
  168. /**
  169. * TPM2 startup values.
  170. *
  171. * @TPM2_SU_CLEAR: reset the internal state.
  172. * @TPM2_SU_STATE: restore saved state (if any).
  173. */
  174. enum tpm2_startup_types {
  175. TPM2_SU_CLEAR = 0x0000,
  176. TPM2_SU_STATE = 0x0001,
  177. };
  178. /**
  179. * TPM2 permanent handles.
  180. *
  181. * @TPM2_RH_OWNER: refers to the 'owner' hierarchy.
  182. * @TPM2_RS_PW: indicates a password.
  183. * @TPM2_RH_LOCKOUT: refers to the 'lockout' hierarchy.
  184. * @TPM2_RH_ENDORSEMENT: refers to the 'endorsement' hierarchy.
  185. * @TPM2_RH_PLATFORM: refers to the 'platform' hierarchy.
  186. */
  187. enum tpm2_handles {
  188. TPM2_RH_OWNER = 0x40000001,
  189. TPM2_RS_PW = 0x40000009,
  190. TPM2_RH_LOCKOUT = 0x4000000A,
  191. TPM2_RH_ENDORSEMENT = 0x4000000B,
  192. TPM2_RH_PLATFORM = 0x4000000C,
  193. };
  194. /**
  195. * TPM2 command codes used at the beginning of a buffer, gives the command.
  196. *
  197. * @TPM2_CC_STARTUP: TPM2_Startup().
  198. * @TPM2_CC_SELF_TEST: TPM2_SelfTest().
  199. * @TPM2_CC_CLEAR: TPM2_Clear().
  200. * @TPM2_CC_CLEARCONTROL: TPM2_ClearControl().
  201. * @TPM2_CC_HIERCHANGEAUTH: TPM2_HierarchyChangeAuth().
  202. * @TPM2_CC_PCR_SETAUTHPOL: TPM2_PCR_SetAuthPolicy().
  203. * @TPM2_CC_DAM_RESET: TPM2_DictionaryAttackLockReset().
  204. * @TPM2_CC_DAM_PARAMETERS: TPM2_DictionaryAttackParameters().
  205. * @TPM2_CC_GET_CAPABILITY: TPM2_GetCapibility().
  206. * @TPM2_CC_GET_RANDOM: TPM2_GetRandom().
  207. * @TPM2_CC_PCR_READ: TPM2_PCR_Read().
  208. * @TPM2_CC_PCR_EXTEND: TPM2_PCR_Extend().
  209. * @TPM2_CC_PCR_SETAUTHVAL: TPM2_PCR_SetAuthValue().
  210. */
  211. enum tpm2_command_codes {
  212. TPM2_CC_STARTUP = 0x0144,
  213. TPM2_CC_SELF_TEST = 0x0143,
  214. TPM2_CC_CLEAR = 0x0126,
  215. TPM2_CC_CLEARCONTROL = 0x0127,
  216. TPM2_CC_HIERCHANGEAUTH = 0x0129,
  217. TPM2_CC_NV_DEFINE_SPACE = 0x012a,
  218. TPM2_CC_PCR_SETAUTHPOL = 0x012C,
  219. TPM2_CC_NV_WRITE = 0x0137,
  220. TPM2_CC_NV_WRITELOCK = 0x0138,
  221. TPM2_CC_DAM_RESET = 0x0139,
  222. TPM2_CC_DAM_PARAMETERS = 0x013A,
  223. TPM2_CC_NV_READ = 0x014E,
  224. TPM2_CC_GET_CAPABILITY = 0x017A,
  225. TPM2_CC_GET_RANDOM = 0x017B,
  226. TPM2_CC_PCR_READ = 0x017E,
  227. TPM2_CC_PCR_EXTEND = 0x0182,
  228. TPM2_CC_PCR_SETAUTHVAL = 0x0183,
  229. };
  230. /**
  231. * TPM2 return codes.
  232. */
  233. enum tpm2_return_codes {
  234. TPM2_RC_SUCCESS = 0x0000,
  235. TPM2_RC_BAD_TAG = 0x001E,
  236. TPM2_RC_FMT1 = 0x0080,
  237. TPM2_RC_HASH = TPM2_RC_FMT1 + 0x0003,
  238. TPM2_RC_VALUE = TPM2_RC_FMT1 + 0x0004,
  239. TPM2_RC_SIZE = TPM2_RC_FMT1 + 0x0015,
  240. TPM2_RC_BAD_AUTH = TPM2_RC_FMT1 + 0x0022,
  241. TPM2_RC_HANDLE = TPM2_RC_FMT1 + 0x000B,
  242. TPM2_RC_VER1 = 0x0100,
  243. TPM2_RC_INITIALIZE = TPM2_RC_VER1 + 0x0000,
  244. TPM2_RC_FAILURE = TPM2_RC_VER1 + 0x0001,
  245. TPM2_RC_DISABLED = TPM2_RC_VER1 + 0x0020,
  246. TPM2_RC_AUTH_MISSING = TPM2_RC_VER1 + 0x0025,
  247. TPM2_RC_COMMAND_CODE = TPM2_RC_VER1 + 0x0043,
  248. TPM2_RC_AUTHSIZE = TPM2_RC_VER1 + 0x0044,
  249. TPM2_RC_AUTH_CONTEXT = TPM2_RC_VER1 + 0x0045,
  250. TPM2_RC_NEEDS_TEST = TPM2_RC_VER1 + 0x0053,
  251. TPM2_RC_WARN = 0x0900,
  252. TPM2_RC_TESTING = TPM2_RC_WARN + 0x000A,
  253. TPM2_RC_REFERENCE_H0 = TPM2_RC_WARN + 0x0010,
  254. TPM2_RC_LOCKOUT = TPM2_RC_WARN + 0x0021,
  255. };
  256. /**
  257. * TPM2 algorithms.
  258. */
  259. enum tpm2_algorithms {
  260. TPM2_ALG_SHA1 = 0x04,
  261. TPM2_ALG_XOR = 0x0A,
  262. TPM2_ALG_SHA256 = 0x0B,
  263. TPM2_ALG_SHA384 = 0x0C,
  264. TPM2_ALG_SHA512 = 0x0D,
  265. TPM2_ALG_NULL = 0x10,
  266. TPM2_ALG_SM3_256 = 0x12,
  267. };
  268. /* NV index attributes */
  269. enum tpm_index_attrs {
  270. TPMA_NV_PPWRITE = 1UL << 0,
  271. TPMA_NV_OWNERWRITE = 1UL << 1,
  272. TPMA_NV_AUTHWRITE = 1UL << 2,
  273. TPMA_NV_POLICYWRITE = 1UL << 3,
  274. TPMA_NV_COUNTER = 1UL << 4,
  275. TPMA_NV_BITS = 1UL << 5,
  276. TPMA_NV_EXTEND = 1UL << 6,
  277. TPMA_NV_POLICY_DELETE = 1UL << 10,
  278. TPMA_NV_WRITELOCKED = 1UL << 11,
  279. TPMA_NV_WRITEALL = 1UL << 12,
  280. TPMA_NV_WRITEDEFINE = 1UL << 13,
  281. TPMA_NV_WRITE_STCLEAR = 1UL << 14,
  282. TPMA_NV_GLOBALLOCK = 1UL << 15,
  283. TPMA_NV_PPREAD = 1UL << 16,
  284. TPMA_NV_OWNERREAD = 1UL << 17,
  285. TPMA_NV_AUTHREAD = 1UL << 18,
  286. TPMA_NV_POLICYREAD = 1UL << 19,
  287. TPMA_NV_NO_DA = 1UL << 25,
  288. TPMA_NV_ORDERLY = 1UL << 26,
  289. TPMA_NV_CLEAR_STCLEAR = 1UL << 27,
  290. TPMA_NV_READLOCKED = 1UL << 28,
  291. TPMA_NV_WRITTEN = 1UL << 29,
  292. TPMA_NV_PLATFORMCREATE = 1UL << 30,
  293. TPMA_NV_READ_STCLEAR = 1UL << 31,
  294. TPMA_NV_MASK_READ = TPMA_NV_PPREAD | TPMA_NV_OWNERREAD |
  295. TPMA_NV_AUTHREAD | TPMA_NV_POLICYREAD,
  296. TPMA_NV_MASK_WRITE = TPMA_NV_PPWRITE | TPMA_NV_OWNERWRITE |
  297. TPMA_NV_AUTHWRITE | TPMA_NV_POLICYWRITE,
  298. };
  299. enum {
  300. TPM_ACCESS_VALID = 1 << 7,
  301. TPM_ACCESS_ACTIVE_LOCALITY = 1 << 5,
  302. TPM_ACCESS_REQUEST_PENDING = 1 << 2,
  303. TPM_ACCESS_REQUEST_USE = 1 << 1,
  304. TPM_ACCESS_ESTABLISHMENT = 1 << 0,
  305. };
  306. enum {
  307. TPM_STS_FAMILY_SHIFT = 26,
  308. TPM_STS_FAMILY_MASK = 0x3 << TPM_STS_FAMILY_SHIFT,
  309. TPM_STS_FAMILY_TPM2 = 1 << TPM_STS_FAMILY_SHIFT,
  310. TPM_STS_RESE_TESTABLISMENT_BIT = 1 << 25,
  311. TPM_STS_COMMAND_CANCEL = 1 << 24,
  312. TPM_STS_BURST_COUNT_SHIFT = 8,
  313. TPM_STS_BURST_COUNT_MASK = 0xffff << TPM_STS_BURST_COUNT_SHIFT,
  314. TPM_STS_VALID = 1 << 7,
  315. TPM_STS_COMMAND_READY = 1 << 6,
  316. TPM_STS_GO = 1 << 5,
  317. TPM_STS_DATA_AVAIL = 1 << 4,
  318. TPM_STS_DATA_EXPECT = 1 << 3,
  319. TPM_STS_SELF_TEST_DONE = 1 << 2,
  320. TPM_STS_RESPONSE_RETRY = 1 << 1,
  321. };
  322. enum {
  323. TPM_CMD_COUNT_OFFSET = 2,
  324. TPM_CMD_ORDINAL_OFFSET = 6,
  325. TPM_MAX_BUF_SIZE = 1260,
  326. };
  327. enum {
  328. /* Secure storage for firmware settings */
  329. TPM_HT_PCR = 0,
  330. TPM_HT_NV_INDEX,
  331. TPM_HT_HMAC_SESSION,
  332. TPM_HT_POLICY_SESSION,
  333. HR_SHIFT = 24,
  334. HR_PCR = TPM_HT_PCR << HR_SHIFT,
  335. HR_HMAC_SESSION = TPM_HT_HMAC_SESSION << HR_SHIFT,
  336. HR_POLICY_SESSION = TPM_HT_POLICY_SESSION << HR_SHIFT,
  337. HR_NV_INDEX = TPM_HT_NV_INDEX << HR_SHIFT,
  338. };
  339. /**
  340. * Issue a TPM2_Startup command.
  341. *
  342. * @dev TPM device
  343. * @mode TPM startup mode
  344. *
  345. * @return code of the operation
  346. */
  347. u32 tpm2_startup(struct udevice *dev, enum tpm2_startup_types mode);
  348. /**
  349. * Issue a TPM2_SelfTest command.
  350. *
  351. * @dev TPM device
  352. * @full_test Asking to perform all tests or only the untested ones
  353. *
  354. * @return code of the operation
  355. */
  356. u32 tpm2_self_test(struct udevice *dev, enum tpm2_yes_no full_test);
  357. /**
  358. * Issue a TPM2_Clear command.
  359. *
  360. * @dev TPM device
  361. * @handle Handle
  362. * @pw Password
  363. * @pw_sz Length of the password
  364. *
  365. * @return code of the operation
  366. */
  367. u32 tpm2_clear(struct udevice *dev, u32 handle, const char *pw,
  368. const ssize_t pw_sz);
  369. /**
  370. * Issue a TPM_NV_DefineSpace command
  371. *
  372. * This allows a space to be defined with given attributes and policy
  373. *
  374. * @dev TPM device
  375. * @space_index index of the area
  376. * @space_size size of area in bytes
  377. * @nv_attributes TPM_NV_ATTRIBUTES of the area
  378. * @nv_policy policy to use
  379. * @nv_policy_size size of the policy
  380. * @return return code of the operation
  381. */
  382. u32 tpm2_nv_define_space(struct udevice *dev, u32 space_index,
  383. size_t space_size, u32 nv_attributes,
  384. const u8 *nv_policy, size_t nv_policy_size);
  385. /**
  386. * Issue a TPM2_PCR_Extend command.
  387. *
  388. * @dev TPM device
  389. * @index Index of the PCR
  390. * @algorithm Algorithm used, defined in 'enum tpm2_algorithms'
  391. * @digest Value representing the event to be recorded
  392. * @digest_len len of the hash
  393. *
  394. * @return code of the operation
  395. */
  396. u32 tpm2_pcr_extend(struct udevice *dev, u32 index, u32 algorithm,
  397. const u8 *digest, u32 digest_len);
  398. /**
  399. * Read data from the secure storage
  400. *
  401. * @dev TPM device
  402. * @index Index of data to read
  403. * @data Place to put data
  404. * @count Number of bytes of data
  405. * @return code of the operation
  406. */
  407. u32 tpm2_nv_read_value(struct udevice *dev, u32 index, void *data, u32 count);
  408. /**
  409. * Write data to the secure storage
  410. *
  411. * @dev TPM device
  412. * @index Index of data to write
  413. * @data Data to write
  414. * @count Number of bytes of data
  415. * @return code of the operation
  416. */
  417. u32 tpm2_nv_write_value(struct udevice *dev, u32 index, const void *data,
  418. u32 count);
  419. /**
  420. * Issue a TPM2_PCR_Read command.
  421. *
  422. * @dev TPM device
  423. * @idx Index of the PCR
  424. * @idx_min_sz Minimum size in bytes of the pcrSelect array
  425. * @data Output buffer for contents of the named PCR
  426. * @updates Optional out parameter: number of updates for this PCR
  427. *
  428. * @return code of the operation
  429. */
  430. u32 tpm2_pcr_read(struct udevice *dev, u32 idx, unsigned int idx_min_sz,
  431. void *data, unsigned int *updates);
  432. /**
  433. * Issue a TPM2_GetCapability command. This implementation is limited
  434. * to query property index that is 4-byte wide.
  435. *
  436. * @dev TPM device
  437. * @capability Partition of capabilities
  438. * @property Further definition of capability, limited to be 4 bytes wide
  439. * @buf Output buffer for capability information
  440. * @prop_count Size of output buffer
  441. *
  442. * @return code of the operation
  443. */
  444. u32 tpm2_get_capability(struct udevice *dev, u32 capability, u32 property,
  445. void *buf, size_t prop_count);
  446. /**
  447. * Issue a TPM2_DictionaryAttackLockReset command.
  448. *
  449. * @dev TPM device
  450. * @pw Password
  451. * @pw_sz Length of the password
  452. *
  453. * @return code of the operation
  454. */
  455. u32 tpm2_dam_reset(struct udevice *dev, const char *pw, const ssize_t pw_sz);
  456. /**
  457. * Issue a TPM2_DictionaryAttackParameters command.
  458. *
  459. * @dev TPM device
  460. * @pw Password
  461. * @pw_sz Length of the password
  462. * @max_tries Count of authorizations before lockout
  463. * @recovery_time Time before decrementation of the failure count
  464. * @lockout_recovery Time to wait after a lockout
  465. *
  466. * @return code of the operation
  467. */
  468. u32 tpm2_dam_parameters(struct udevice *dev, const char *pw,
  469. const ssize_t pw_sz, unsigned int max_tries,
  470. unsigned int recovery_time,
  471. unsigned int lockout_recovery);
  472. /**
  473. * Issue a TPM2_HierarchyChangeAuth command.
  474. *
  475. * @dev TPM device
  476. * @handle Handle
  477. * @newpw New password
  478. * @newpw_sz Length of the new password
  479. * @oldpw Old password
  480. * @oldpw_sz Length of the old password
  481. *
  482. * @return code of the operation
  483. */
  484. int tpm2_change_auth(struct udevice *dev, u32 handle, const char *newpw,
  485. const ssize_t newpw_sz, const char *oldpw,
  486. const ssize_t oldpw_sz);
  487. /**
  488. * Issue a TPM_PCR_SetAuthPolicy command.
  489. *
  490. * @dev TPM device
  491. * @pw Platform password
  492. * @pw_sz Length of the password
  493. * @index Index of the PCR
  494. * @digest New key to access the PCR
  495. *
  496. * @return code of the operation
  497. */
  498. u32 tpm2_pcr_setauthpolicy(struct udevice *dev, const char *pw,
  499. const ssize_t pw_sz, u32 index, const char *key);
  500. /**
  501. * Issue a TPM_PCR_SetAuthValue command.
  502. *
  503. * @dev TPM device
  504. * @pw Platform password
  505. * @pw_sz Length of the password
  506. * @index Index of the PCR
  507. * @digest New key to access the PCR
  508. * @key_sz Length of the new key
  509. *
  510. * @return code of the operation
  511. */
  512. u32 tpm2_pcr_setauthvalue(struct udevice *dev, const char *pw,
  513. const ssize_t pw_sz, u32 index, const char *key,
  514. const ssize_t key_sz);
  515. /**
  516. * Issue a TPM2_GetRandom command.
  517. *
  518. * @dev TPM device
  519. * @param data output buffer for the random bytes
  520. * @param count size of output buffer
  521. *
  522. * @return return code of the operation
  523. */
  524. u32 tpm2_get_random(struct udevice *dev, void *data, u32 count);
  525. /**
  526. * Lock data in the TPM
  527. *
  528. * Once locked the data cannot be written until after a reboot
  529. *
  530. * @dev TPM device
  531. * @index Index of data to lock
  532. * @return code of the operation
  533. */
  534. u32 tpm2_write_lock(struct udevice *dev, u32 index);
  535. #endif /* __TPM_V2_H */