starfive-jh7110.h 6.8 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219
  1. /* SPDX-License-Identifier: GPL-2.0 OR MIT */
  2. /*
  3. * Copyright (C) 2022-2023 StarFive Technology Co., Ltd.
  4. * Author: samin <samin.guo@starfivetech.com>
  5. * yanhong <yanhong.wang@starfivetech.com>
  6. */
  7. #ifndef __DT_BINDINGS_RESET_STARFIVE_JH7110_H__
  8. #define __DT_BINDINGS_RESET_STARFIVE_JH7110_H__
  9. /*
  10. * group[0]: syscrg: assert0
  11. */
  12. #define RSTN_U0_JTAG2APB_PRESETN 0
  13. #define RSTN_U0_SYS_SYSCON_PRESETN 1
  14. #define RSTN_U0_SYS_IOMUX_PRESETN 2
  15. #define RSTN_U0_U7MC_RST_BUS 3
  16. #define RSTN_U0_U7MC_DEBUG 4
  17. #define RSTN_U0_U7MC_CORE0 5
  18. #define RSTN_U0_U7MC_CORE1 6
  19. #define RSTN_U0_U7MC_CORE2 7
  20. #define RSTN_U0_U7MC_CORE3 8
  21. #define RSTN_U0_U7MC_CORE4 9
  22. #define RSTN_U0_U7MC_CORE0_ST 10
  23. #define RSTN_U0_U7MC_CORE1_ST 11
  24. #define RSTN_U0_U7MC_CORE2_ST 12
  25. #define RSTN_U0_U7MC_CORE3_ST 13
  26. #define RSTN_U0_U7MC_CORE4_ST 14
  27. #define RSTN_U0_U7MC_TRACE_RST0 15
  28. #define RSTN_U0_U7MC_TRACE_RST1 16
  29. #define RSTN_U0_U7MC_TRACE_RST2 17
  30. #define RSTN_U0_U7MC_TRACE_RST3 18
  31. #define RSTN_U0_U7MC_TRACE_RST4 19
  32. #define RSTN_U0_U7MC_TRACE_COM 20
  33. #define RSTN_U0_IMG_GPU_APB 21
  34. #define RSTN_U0_IMG_GPU_DOMA 22
  35. #define RSTN_U0_NOC_BUS_APB_BUS_N 23
  36. #define RSTN_U0_NOC_BUS_AXICFG0_AXI_N 24
  37. #define RSTN_U0_NOC_BUS_CPU_AXI_N 25
  38. #define RSTN_U0_NOC_BUS_DISP_AXI_N 26
  39. #define RSTN_U0_NOC_BUS_GPU_AXI_N 27
  40. #define RSTN_U0_NOC_BUS_ISP_AXI_N 28
  41. #define RSTN_U0_NOC_BUS_DDRC_N 29
  42. #define RSTN_U0_NOC_BUS_STG_AXI_N 30
  43. #define RSTN_U0_NOC_BUS_VDEC_AXI_N 31
  44. /*
  45. * group[1]: syscrg: assert1
  46. */
  47. #define RSTN_U0_NOC_BUS_VENC_AXI_N 32
  48. #define RSTN_U0_AXI_CFG1_DEC_AHB 33
  49. #define RSTN_U0_AXI_CFG1_DEC_MAIN 34
  50. #define RSTN_U0_AXI_CFG0_DEC_MAIN 35
  51. #define RSTN_U0_AXI_CFG0_DEC_MAIN_DIV 36
  52. #define RSTN_U0_AXI_CFG0_DEC_HIFI4 37
  53. #define RSTN_U0_DDR_AXI 38
  54. #define RSTN_U0_DDR_OSC 39
  55. #define RSTN_U0_DDR_APB 40
  56. #define RSTN_U0_DOM_ISP_TOP_N 41
  57. #define RSTN_U0_DOM_ISP_TOP_AXI 42
  58. #define RSTN_U0_DOM_VOUT_TOP_SRC 43
  59. #define RSTN_U0_CODAJ12_AXI 44
  60. #define RSTN_U0_CODAJ12_CORE 45
  61. #define RSTN_U0_CODAJ12_APB 46
  62. #define RSTN_U0_WAVE511_AXI 47
  63. #define RSTN_U0_WAVE511_BPU 48
  64. #define RSTN_U0_WAVE511_VCE 49
  65. #define RSTN_U0_WAVE511_APB 50
  66. #define RSTN_U0_VDEC_JPG_ARB_JPG 51
  67. #define RSTN_U0_VDEC_JPG_ARB_MAIN 52
  68. #define RSTN_U0_AXIMEM_128B_AXI 53
  69. #define RSTN_U0_WAVE420L_AXI 54
  70. #define RSTN_U0_WAVE420L_BPU 55
  71. #define RSTN_U0_WAVE420L_VCE 56
  72. #define RSTN_U0_WAVE420L_APB 57
  73. #define RSTN_U1_AXIMEM_128B_AXI 58
  74. #define RSTN_U2_AXIMEM_128B_AXI 59
  75. #define RSTN_U0_INTMEM_ROM_SRAM_ROM 60
  76. #define RSTN_U0_CDNS_QSPI_AHB 61
  77. #define RSTN_U0_CDNS_QSPI_APB 62
  78. #define RSTN_U0_CDNS_QSPI_REF 63
  79. /*
  80. * group[2]: syscrg: assert2
  81. */
  82. #define RSTN_U0_DW_SDIO_AHB 64
  83. #define RSTN_U1_DW_SDIO_AHB 65
  84. #define RSTN_U1_DW_GMAC5_AXI64_A_I 66
  85. #define RSTN_U1_DW_GMAC5_AXI64_H_N 67
  86. #define RSTN_U0_MAILBOX_RRESETN 68
  87. #define RSTN_U0_SSP_SPI_APB 69
  88. #define RSTN_U1_SSP_SPI_APB 70
  89. #define RSTN_U2_SSP_SPI_APB 71
  90. #define RSTN_U3_SSP_SPI_APB 72
  91. #define RSTN_U4_SSP_SPI_APB 73
  92. #define RSTN_U5_SSP_SPI_APB 74
  93. #define RSTN_U6_SSP_SPI_APB 75
  94. #define RSTN_U0_DW_I2C_APB 76
  95. #define RSTN_U1_DW_I2C_APB 77
  96. #define RSTN_U2_DW_I2C_APB 78
  97. #define RSTN_U3_DW_I2C_APB 79
  98. #define RSTN_U4_DW_I2C_APB 80
  99. #define RSTN_U5_DW_I2C_APB 81
  100. #define RSTN_U6_DW_I2C_APB 82
  101. #define RSTN_U0_DW_UART_APB 83
  102. #define RSTN_U0_DW_UART_CORE 84
  103. #define RSTN_U1_DW_UART_APB 85
  104. #define RSTN_U1_DW_UART_CORE 86
  105. #define RSTN_U2_DW_UART_APB 87
  106. #define RSTN_U2_DW_UART_CORE 88
  107. #define RSTN_U3_DW_UART_APB 89
  108. #define RSTN_U3_DW_UART_CORE 90
  109. #define RSTN_U4_DW_UART_APB 91
  110. #define RSTN_U4_DW_UART_CORE 92
  111. #define RSTN_U5_DW_UART_APB 93
  112. #define RSTN_U5_DW_UART_CORE 94
  113. #define RSTN_U0_CDNS_SPDIF_APB 95
  114. /*
  115. * group[3]: syscrg: assert3
  116. */
  117. #define RSTN_U0_PWMDAC_APB 96
  118. #define RSTN_U0_PDM_4MIC_DMIC 97
  119. #define RSTN_U0_PDM_4MIC_APB 98
  120. #define RSTN_U0_I2SRX_3CH_APB 99
  121. #define RSTN_U0_I2SRX_3CH_BCLK 100
  122. #define RSTN_U0_I2STX_4CH_APB 101
  123. #define RSTN_U0_I2STX_4CH_BCLK 102
  124. #define RSTN_U1_I2STX_4CH_APB 103
  125. #define RSTN_U1_I2STX_4CH_BCLK 104
  126. #define RSTN_U0_TDM16SLOT_AHB 105
  127. #define RSTN_U0_TDM16SLOT_TDM 106
  128. #define RSTN_U0_TDM16SLOT_APB 107
  129. #define RSTN_U0_PWM_8CH_APB 108
  130. #define RSTN_U0_DSKIT_WDT_APB 109
  131. #define RSTN_U0_DSKIT_WDT_CORE 110
  132. #define RSTN_U0_CAN_CTRL_APB 111
  133. #define RSTN_U0_CAN_CTRL_CORE 112
  134. #define RSTN_U0_CAN_CTRL_TIMER 113
  135. #define RSTN_U1_CAN_CTRL_APB 114
  136. #define RSTN_U1_CAN_CTRL_CORE 115
  137. #define RSTN_U1_CAN_CTRL_TIMER 116
  138. #define RSTN_U0_SI5_TIMER_APB 117
  139. #define RSTN_U0_SI5_TIMER_TIMER0 118
  140. #define RSTN_U0_SI5_TIMER_TIMER1 119
  141. #define RSTN_U0_SI5_TIMER_TIMER2 120
  142. #define RSTN_U0_SI5_TIMER_TIMER3 121
  143. #define RSTN_U0_INT_CTRL_APB 122
  144. #define RSTN_U0_TEMP_SENSOR_APB 123
  145. #define RSTN_U0_TEMP_SENSOR_TEMP 124
  146. #define RSTN_U0_JTAG_CERTIFICATION_N 125
  147. /*
  148. * group[4]: stgcrg
  149. */
  150. #define RSTN_U0_STG_SYSCON_PRESETN 128
  151. #define RSTN_U0_HIFI4_CORE 129
  152. #define RSTN_U0_HIFI4_AXI 130
  153. #define RSTN_U0_SEC_TOP_HRESETN 131
  154. #define RSTN_U0_E24_CORE 132
  155. #define RSTN_U0_DW_DMA1P_AXI 133
  156. #define RSTN_U0_DW_DMA1P_AHB 134
  157. #define RSTN_U0_CDN_USB_AXI 135
  158. #define RSTN_U0_CDN_USB_APB 136
  159. #define RSTN_U0_CDN_USB_UTMI_APB 137
  160. #define RSTN_U0_CDN_USB_PWRUP 138
  161. #define RSTN_U0_PLDA_PCIE_AXI_MST0 139
  162. #define RSTN_U0_PLDA_PCIE_AXI_SLV0 140
  163. #define RSTN_U0_PLDA_PCIE_AXI_SLV 141
  164. #define RSTN_U0_PLDA_PCIE_BRG 142
  165. #define RSTN_U0_PLDA_PCIE_CORE 143
  166. #define RSTN_U0_PLDA_PCIE_APB 144
  167. #define RSTN_U1_PLDA_PCIE_AXI_MST0 145
  168. #define RSTN_U1_PLDA_PCIE_AXI_SLV0 146
  169. #define RSTN_U1_PLDA_PCIE_AXI_SLV 147
  170. #define RSTN_U1_PLDA_PCIE_BRG 148
  171. #define RSTN_U1_PLDA_PCIE_CORE 149
  172. #define RSTN_U1_PLDA_PCIE_APB 150
  173. /*
  174. * group[5]: aoncrg
  175. */
  176. #define RSTN_U0_DW_GMAC5_AXI64_AXI 160
  177. #define RSTN_U0_DW_GMAC5_AXI64_AHB 161
  178. #define RSTN_U0_AON_IOMUX_PRESETN 162
  179. #define RSTN_U0_PMU_APB 163
  180. #define RSTN_U0_PMU_WKUP 164
  181. #define RSTN_U0_RTC_HMS_APB 165
  182. #define RSTN_U0_RTC_HMS_CAL 166
  183. #define RSTN_U0_RTC_HMS_OSC32K 167
  184. /*
  185. * group[6]: ispcrg
  186. */
  187. #define RSTN_U0_ISPV2_TOP_WRAPPER_P 192
  188. #define RSTN_U0_ISPV2_TOP_WRAPPER_C 193
  189. #define RSTN_U0_M31DPHY_HW 194
  190. #define RSTN_U0_M31DPHY_B09_ALWAYS_ON 195
  191. #define RSTN_U0_VIN_N_PCLK 196
  192. #define RSTN_U0_VIN_N_PIXEL_CLK_IF0 197
  193. #define RSTN_U0_VIN_N_PIXEL_CLK_IF1 198
  194. #define RSTN_U0_VIN_N_PIXEL_CLK_IF2 199
  195. #define RSTN_U0_VIN_N_PIXEL_CLK_IF3 200
  196. #define RSTN_U0_VIN_N_SYS_CLK 201
  197. #define RSTN_U0_VIN_P_AXIRD 202
  198. #define RSTN_U0_VIN_P_AXIWR 203
  199. /*
  200. * group[7]: voutcrg
  201. */
  202. #define RSTN_U0_DC8200_AXI 224
  203. #define RSTN_U0_DC8200_AHB 225
  204. #define RSTN_U0_DC8200_CORE 226
  205. #define RSTN_U0_CDNS_DSITX_DPI 227
  206. #define RSTN_U0_CDNS_DSITX_APB 228
  207. #define RSTN_U0_CDNS_DSITX_RXESC 229
  208. #define RSTN_U0_CDNS_DSITX_SYS 230
  209. #define RSTN_U0_CDNS_DSITX_TXBYTEHS 231
  210. #define RSTN_U0_CDNS_DSITX_TXESC 232
  211. #define RSTN_U0_HDMI_TX_HDMI 233
  212. #define RSTN_U0_MIPITX_DPHY_SYS 234
  213. #define RSTN_U0_MIPITX_DPHY_TXBYTEHS 235
  214. #define RSTN_JH7110_RESET_END 236
  215. #endif /* __DT_BINDINGS_RESET_STARFIVE_JH7110_H__ */