starfive-jh7110-isp.h 1.9 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354
  1. /* SPDX-License-Identifier: GPL-2.0 OR MIT */
  2. /*
  3. * Copyright (C) 2022-2023 StarFive Technology Co., Ltd.
  4. * Author: XingYu Wu <xingyu.wu@starfivetech.com>
  5. */
  6. #ifndef __DT_BINDINGS_CLOCK_STARFIVE_JH7110_ISP_H__
  7. #define __DT_BINDINGS_CLOCK_STARFIVE_JH7110_ISP_H__
  8. /* regisger */
  9. #define JH7110_DOM4_APB_FUNC 0
  10. #define JH7110_MIPI_RX0_PXL 1
  11. #define JH7110_DVP_INV 2
  12. #define JH7110_U0_M31DPHY_CFGCLK_IN 3
  13. #define JH7110_U0_M31DPHY_REFCLK_IN 4
  14. #define JH7110_U0_M31DPHY_TXCLKESC_LAN0 5
  15. #define JH7110_U0_VIN_PCLK 6
  16. #define JH7110_U0_VIN_SYS_CLK 7
  17. #define JH7110_U0_VIN_PIXEL_CLK_IF0 8
  18. #define JH7110_U0_VIN_PIXEL_CLK_IF1 9
  19. #define JH7110_U0_VIN_PIXEL_CLK_IF2 10
  20. #define JH7110_U0_VIN_PIXEL_CLK_IF3 11
  21. #define JH7110_U0_VIN_CLK_P_AXIWR 12
  22. #define JH7110_U0_ISPV2_TOP_WRAPPER_CLK_C 13
  23. #define JH7110_CLK_ISP_REG_END 14
  24. /* other */
  25. #define JH7110_U3_PCLK_MUX_FUNC_PCLK 14
  26. #define JH7110_U3_PCLK_MUX_BIST_PCLK 15
  27. #define JH7110_DOM4_APB 16
  28. #define JH7110_U0_VIN_PCLK_FREE 17
  29. #define JH7110_U0_VIN_CLK_P_AXIRD 18
  30. #define JH7110_U0_VIN_ACLK 19
  31. #define JH7110_U0_ISPV2_TOP_WRAPPER_CLK_ISP_AXI_IN 20
  32. #define JH7110_U0_ISPV2_TOP_WRAPPER_CLK_ISP_X2 21
  33. #define JH7110_U0_ISPV2_TOP_WRAPPER_CLK_ISP 22
  34. #define JH7110_U0_ISPV2_TOP_WRAPPER_CLK_P 23
  35. #define JH7110_U0_CRG_PCLK 24
  36. #define JH7110_U0_SYSCON_PCLK 25
  37. #define JH7110_U0_M31DPHY_APBCFG_PCLK 26
  38. #define JH7110_U0_AXI2APB_BRIDGE_CLK_DOM4_APB 27
  39. #define JH7110_U0_AXI2APB_BRIDGE_ISP_AXI4SLV_CLK 28
  40. #define JH7110_U3_PCLK_MUX_PCLK 29
  41. #define JH7110_CLK_ISP_END 30
  42. /* external clocks */
  43. #define JH7110_ISP_TOP_CLK_ISPCORE_2X_CLKGEN (JH7110_CLK_ISP_END + 0)
  44. #define JH7110_ISP_TOP_CLK_ISP_AXI_CLKGEN (JH7110_CLK_ISP_END + 1)
  45. #define JH7110_ISP_TOP_CLK_BIST_APB_CLKGEN (JH7110_CLK_ISP_END + 2)
  46. #define JH7110_ISP_TOP_CLK_DVP_CLKGEN (JH7110_CLK_ISP_END + 3)
  47. #endif /* __DT_BINDINGS_CLOCK_STARFIVE_JH7110_H__ */