starfive-jh7110-clkgen.h 22 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 OR MIT */
  2. /*
  3. * Copyright (C) 2022-2023 StarFive Technology Co., Ltd.
  4. * Author: XingYu Wu <xingyu.wu@starfivetech.com>
  5. */
  6. #ifndef __DT_BINDINGS_CLOCK_STARFIVE_JH7110_CLKGEN_H__
  7. #define __DT_BINDINGS_CLOCK_STARFIVE_JH7110_CLKGEN_H__
  8. /* sys regisger */
  9. #define JH7110_CPU_ROOT 0
  10. #define JH7110_CPU_CORE 1
  11. #define JH7110_CPU_BUS 2
  12. #define JH7110_GPU_ROOT 3
  13. #define JH7110_PERH_ROOT 4
  14. #define JH7110_BUS_ROOT 5
  15. #define JH7110_NOCSTG_BUS 6
  16. #define JH7110_AXI_CFG0 7
  17. #define JH7110_STG_AXIAHB 8
  18. #define JH7110_AHB0 9
  19. #define JH7110_AHB1 10
  20. #define JH7110_APB_BUS_FUNC 11
  21. #define JH7110_APB0 12
  22. #define JH7110_PLL0_DIV2 13
  23. #define JH7110_PLL1_DIV2 14
  24. #define JH7110_PLL2_DIV2 15
  25. #define JH7110_AUDIO_ROOT 16
  26. #define JH7110_MCLK_INNER 17
  27. #define JH7110_MCLK 18
  28. #define JH7110_MCLK_OUT 19
  29. #define JH7110_ISP_2X 20
  30. #define JH7110_ISP_AXI 21
  31. #define JH7110_GCLK0 22
  32. #define JH7110_GCLK1 23
  33. #define JH7110_GCLK2 24
  34. #define JH7110_U7_CORE_CLK 25
  35. #define JH7110_U7_CORE_CLK1 26
  36. #define JH7110_U7_CORE_CLK2 27
  37. #define JH7110_U7_CORE_CLK3 28
  38. #define JH7110_U7_CORE_CLK4 29
  39. #define JH7110_U7_DEBUG_CLK 30
  40. #define JH7110_U7_RTC_TOGGLE 31
  41. #define JH7110_U7_TRACE_CLK0 32
  42. #define JH7110_U7_TRACE_CLK1 33
  43. #define JH7110_U7_TRACE_CLK2 34
  44. #define JH7110_U7_TRACE_CLK3 35
  45. #define JH7110_U7_TRACE_CLK4 36
  46. #define JH7110_U7_TRACE_COM_CLK 37
  47. #define JH7110_NOC_BUS_CLK_CPU_AXI 38
  48. #define JH7110_NOC_BUS_CLK_AXICFG0_AXI 39
  49. #define JH7110_OSC_DIV2 40
  50. #define JH7110_PLL1_DIV4 41
  51. #define JH7110_PLL1_DIV8 42
  52. #define JH7110_DDR_BUS 43
  53. #define JH7110_DDR_CLK_AXI 44
  54. #define JH7110_GPU_CORE 45
  55. #define JH7110_GPU_CORE_CLK 46
  56. #define JH7110_GPU_SYS_CLK 47
  57. #define JH7110_GPU_CLK_APB 48
  58. #define JH7110_GPU_RTC_TOGGLE 49
  59. #define JH7110_NOC_BUS_CLK_GPU_AXI 50
  60. #define JH7110_ISP_TOP_CLK_ISPCORE_2X 51
  61. #define JH7110_ISP_TOP_CLK_ISP_AXI 52
  62. #define JH7110_NOC_BUS_CLK_ISP_AXI 53
  63. #define JH7110_HIFI4_CORE 54
  64. #define JH7110_HIFI4_AXI 55
  65. #define JH7110_AXI_CFG1_DEC_CLK_MAIN 56
  66. #define JH7110_AXI_CFG1_DEC_CLK_AHB 57
  67. #define JH7110_VOUT_SRC 58
  68. #define JH7110_VOUT_AXI 59
  69. #define JH7110_NOC_BUS_CLK_DISP_AXI 60
  70. #define JH7110_VOUT_TOP_CLK_VOUT_AHB 61
  71. #define JH7110_VOUT_TOP_CLK_VOUT_AXI 62
  72. #define JH7110_VOUT_TOP_CLK_HDMITX0_MCLK 63
  73. #define JH7110_VOUT_TOP_CLK_MIPIPHY_REF 64
  74. #define JH7110_JPEGC_AXI 65
  75. #define JH7110_CODAJ12_CLK_AXI 66
  76. #define JH7110_CODAJ12_CLK_CORE 67
  77. #define JH7110_CODAJ12_CLK_APB 68
  78. #define JH7110_VDEC_AXI 69
  79. #define JH7110_WAVE511_CLK_AXI 70
  80. #define JH7110_WAVE511_CLK_BPU 71
  81. #define JH7110_WAVE511_CLK_VCE 72
  82. #define JH7110_WAVE511_CLK_APB 73
  83. #define JH7110_VDEC_JPG_ARB_JPGCLK 74
  84. #define JH7110_VDEC_JPG_ARB_MAINCLK 75
  85. #define JH7110_NOC_BUS_CLK_VDEC_AXI 76
  86. #define JH7110_VENC_AXI 77
  87. #define JH7110_WAVE420L_CLK_AXI 78
  88. #define JH7110_WAVE420L_CLK_BPU 79
  89. #define JH7110_WAVE420L_CLK_VCE 80
  90. #define JH7110_WAVE420L_CLK_APB 81
  91. #define JH7110_NOC_BUS_CLK_VENC_AXI 82
  92. #define JH7110_AXI_CFG0_DEC_CLK_MAIN_DIV 83
  93. #define JH7110_AXI_CFG0_DEC_CLK_MAIN 84
  94. #define JH7110_AXI_CFG0_DEC_CLK_HIFI4 85
  95. #define JH7110_AXIMEM2_128B_CLK_AXI 86
  96. #define JH7110_QSPI_CLK_AHB 87
  97. #define JH7110_QSPI_CLK_APB 88
  98. #define JH7110_QSPI_REF_SRC 89
  99. #define JH7110_QSPI_CLK_REF 90
  100. #define JH7110_SDIO0_CLK_AHB 91
  101. #define JH7110_SDIO1_CLK_AHB 92
  102. #define JH7110_SDIO0_CLK_SDCARD 93
  103. #define JH7110_SDIO1_CLK_SDCARD 94
  104. #define JH7110_USB_125M 95
  105. #define JH7110_NOC_BUS_CLK_STG_AXI 96
  106. #define JH7110_GMAC5_CLK_AHB 97
  107. #define JH7110_GMAC5_CLK_AXI 98
  108. #define JH7110_GMAC_SRC 99
  109. #define JH7110_GMAC1_GTXCLK 100
  110. #define JH7110_GMAC1_RMII_RTX 101
  111. #define JH7110_GMAC5_CLK_PTP 102
  112. #define JH7110_GMAC5_CLK_RX 103
  113. #define JH7110_GMAC5_CLK_RX_INV 104
  114. #define JH7110_GMAC5_CLK_TX 105
  115. #define JH7110_GMAC5_CLK_TX_INV 106
  116. #define JH7110_GMAC1_GTXC 107
  117. #define JH7110_GMAC0_GTXCLK 108
  118. #define JH7110_GMAC0_PTP 109
  119. #define JH7110_GMAC_PHY 110
  120. #define JH7110_GMAC0_GTXC 111
  121. #define JH7110_SYS_IOMUX_PCLK 112
  122. #define JH7110_MAILBOX_CLK_APB 113
  123. #define JH7110_INT_CTRL_CLK_APB 114
  124. #define JH7110_CAN0_CTRL_CLK_APB 115
  125. #define JH7110_CAN0_CTRL_CLK_TIMER 116
  126. #define JH7110_CAN0_CTRL_CLK_CAN 117
  127. #define JH7110_CAN1_CTRL_CLK_APB 118
  128. #define JH7110_CAN1_CTRL_CLK_TIMER 119
  129. #define JH7110_CAN1_CTRL_CLK_CAN 120
  130. #define JH7110_PWM_CLK_APB 121
  131. #define JH7110_DSKIT_WDT_CLK_APB 122
  132. #define JH7110_DSKIT_WDT_CLK_WDT 123
  133. #define JH7110_TIMER_CLK_APB 124
  134. #define JH7110_TIMER_CLK_TIMER0 125
  135. #define JH7110_TIMER_CLK_TIMER1 126
  136. #define JH7110_TIMER_CLK_TIMER2 127
  137. #define JH7110_TIMER_CLK_TIMER3 128
  138. #define JH7110_TEMP_SENSOR_CLK_APB 129
  139. #define JH7110_TEMP_SENSOR_CLK_TEMP 130
  140. #define JH7110_SPI0_CLK_APB 131
  141. #define JH7110_SPI1_CLK_APB 132
  142. #define JH7110_SPI2_CLK_APB 133
  143. #define JH7110_SPI3_CLK_APB 134
  144. #define JH7110_SPI4_CLK_APB 135
  145. #define JH7110_SPI5_CLK_APB 136
  146. #define JH7110_SPI6_CLK_APB 137
  147. #define JH7110_I2C0_CLK_APB 138
  148. #define JH7110_I2C1_CLK_APB 139
  149. #define JH7110_I2C2_CLK_APB 140
  150. #define JH7110_I2C3_CLK_APB 141
  151. #define JH7110_I2C4_CLK_APB 142
  152. #define JH7110_I2C5_CLK_APB 143
  153. #define JH7110_I2C6_CLK_APB 144
  154. #define JH7110_UART0_CLK_APB 145
  155. #define JH7110_UART0_CLK_CORE 146
  156. #define JH7110_UART1_CLK_APB 147
  157. #define JH7110_UART1_CLK_CORE 148
  158. #define JH7110_UART2_CLK_APB 149
  159. #define JH7110_UART2_CLK_CORE 150
  160. #define JH7110_UART3_CLK_APB 151
  161. #define JH7110_UART3_CLK_CORE 152
  162. #define JH7110_UART4_CLK_APB 153
  163. #define JH7110_UART4_CLK_CORE 154
  164. #define JH7110_UART5_CLK_APB 155
  165. #define JH7110_UART5_CLK_CORE 156
  166. #define JH7110_PWMDAC_CLK_APB 157
  167. #define JH7110_PWMDAC_CLK_CORE 158
  168. #define JH7110_SPDIF_CLK_APB 159
  169. #define JH7110_SPDIF_CLK_CORE 160
  170. #define JH7110_I2STX0_4CHCLK_APB 161
  171. #define JH7110_I2STX_4CH0_BCLK_MST 162
  172. #define JH7110_I2STX_4CH0_BCLK_MST_INV 163
  173. #define JH7110_I2STX_4CH0_LRCK_MST 164
  174. #define JH7110_I2STX0_4CHBCLK 165
  175. #define JH7110_I2STX0_4CHBCLK_N 166
  176. #define JH7110_I2STX0_4CHLRCK 167
  177. #define JH7110_I2STX1_4CHCLK_APB 168
  178. #define JH7110_I2STX_4CH1_BCLK_MST 169
  179. #define JH7110_I2STX_4CH1_BCLK_MST_INV 170
  180. #define JH7110_I2STX_4CH1_LRCK_MST 171
  181. #define JH7110_I2STX1_4CHBCLK 172
  182. #define JH7110_I2STX1_4CHBCLK_N 173
  183. #define JH7110_I2STX1_4CHLRCK 174
  184. #define JH7110_I2SRX0_3CH_CLK_APB 175
  185. #define JH7110_I2SRX_3CH_BCLK_MST 176
  186. #define JH7110_I2SRX_3CH_BCLK_MST_INV 177
  187. #define JH7110_I2SRX_3CH_LRCK_MST 178
  188. #define JH7110_I2SRX0_3CH_BCLK 179
  189. #define JH7110_I2SRX0_3CH_BCLK_N 180
  190. #define JH7110_I2SRX0_3CH_LRCK 181
  191. #define JH7110_PDM_CLK_DMIC 182
  192. #define JH7110_PDM_CLK_APB 183
  193. #define JH7110_TDM_CLK_AHB 184
  194. #define JH7110_TDM_CLK_APB 185
  195. #define JH7110_TDM_INTERNAL 186
  196. #define JH7110_TDM_CLK_TDM 187
  197. #define JH7110_TDM_CLK_TDM_N 188
  198. #define JH7110_JTAG_CERTIFICATION_TRNG_CLK 189
  199. #define JH7110_CLK_SYS_REG_END 190
  200. /* stg regisger */
  201. #define JH7110_HIFI4_CLK_CORE 190
  202. #define JH7110_USB0_CLK_USB_APB 191
  203. #define JH7110_USB0_CLK_UTMI_APB 192
  204. #define JH7110_USB0_CLK_AXI 193
  205. #define JH7110_USB0_CLK_LPM 194
  206. #define JH7110_USB0_CLK_STB 195
  207. #define JH7110_USB0_CLK_APP_125 196
  208. #define JH7110_USB0_REFCLK 197
  209. #define JH7110_PCIE0_CLK_AXI_MST0 198
  210. #define JH7110_PCIE0_CLK_APB 199
  211. #define JH7110_PCIE0_CLK_TL 200
  212. #define JH7110_PCIE1_CLK_AXI_MST0 201
  213. #define JH7110_PCIE1_CLK_APB 202
  214. #define JH7110_PCIE1_CLK_TL 203
  215. #define JH7110_PCIE01_SLV_DEC_MAINCLK 204
  216. #define JH7110_SEC_HCLK 205
  217. #define JH7110_SEC_MISCAHB_CLK 206
  218. #define JH7110_STG_MTRX_GRP0_CLK_MAIN 207
  219. #define JH7110_STG_MTRX_GRP0_CLK_BUS 208
  220. #define JH7110_STG_MTRX_GRP0_CLK_STG 209
  221. #define JH7110_STG_MTRX_GRP1_CLK_MAIN 210
  222. #define JH7110_STG_MTRX_GRP1_CLK_BUS 211
  223. #define JH7110_STG_MTRX_GRP1_CLK_STG 212
  224. #define JH7110_STG_MTRX_GRP1_CLK_HIFI 213
  225. #define JH7110_E2_RTC_CLK 214
  226. #define JH7110_E2_CLK_CORE 215
  227. #define JH7110_E2_CLK_DBG 216
  228. #define JH7110_DMA1P_CLK_AXI 217
  229. #define JH7110_DMA1P_CLK_AHB 218
  230. #define JH7110_CLK_STG_REG_END 219
  231. /* aon regisger */
  232. #define JH7110_OSC_DIV4 219
  233. #define JH7110_AON_APB_FUNC 220
  234. #define JH7110_U0_GMAC5_CLK_AHB 221
  235. #define JH7110_U0_GMAC5_CLK_AXI 222
  236. #define JH7110_GMAC0_RMII_RTX 223
  237. #define JH7110_U0_GMAC5_CLK_TX 224
  238. #define JH7110_U0_GMAC5_CLK_TX_INV 225
  239. #define JH7110_U0_GMAC5_CLK_RX 226
  240. #define JH7110_U0_GMAC5_CLK_RX_INV 227
  241. #define JH7110_OTPC_CLK_APB 228
  242. #define JH7110_RTC_HMS_CLK_APB 229
  243. #define JH7110_RTC_INTERNAL 230
  244. #define JH7110_RTC_HMS_CLK_OSC32K 231
  245. #define JH7110_RTC_HMS_CLK_CAL 232
  246. #define JH7110_CLK_REG_END 233
  247. /* sys other */
  248. #define JH7110_PLL0_OUT 233
  249. #define JH7110_PLL1_OUT 234
  250. #define JH7110_PLL2_OUT 235
  251. #define JH7110_AON_APB 236
  252. #define JH7110_RESET1_CTRL_CLK_SRC 237
  253. #define JH7110_DDR_ROOT 238
  254. #define JH7110_VDEC_ROOT 239
  255. #define JH7110_VENC_ROOT 240
  256. #define JH7110_VOUT_ROOT 241
  257. #define JH7110_GMACUSB_ROOT 242
  258. #define JH7110_PCLK2_MUX_FUNC_PCLK 243
  259. #define JH7110_PCLK2_MUX_BIST_PCLK 244
  260. #define JH7110_APB_BUS 245
  261. #define JH7110_APB12 246
  262. #define JH7110_AXI_CFG1 247
  263. #define JH7110_PLL_WRAP_CRG_GCLK0 248
  264. #define JH7110_PLL_WRAP_CRG_GCLK1 249
  265. #define JH7110_PLL_WRAP_CRG_GCLK2 250
  266. #define JH7110_JTAG2APB_PCLK 251
  267. #define JH7110_U7_BUS_CLK 252
  268. #define JH7110_U7_IRQ_SYNC_BUS_CLK 253
  269. #define JH7110_NOC_BUS_CLK2_CPU_AXI 254
  270. #define JH7110_NOC_BUS_CLK_APB_BUS 255
  271. #define JH7110_NOC_BUS_CLK2_APB_BUS 256
  272. #define JH7110_NOC_BUS_CLK2_AXICFG0_AXI 257
  273. #define JH7110_DDR_CLK_DDRPHY_PLL_BYPASS 258
  274. #define JH7110_DDR_CLK_OSC 259
  275. #define JH7110_DDR_CLK_APB 260
  276. #define JH7110_NOC_BUS_CLK_DDRC 261
  277. #define JH7110_NOC_BUS_CLK2_DDRC 262
  278. #define JH7110_SYS_AHB_DEC_CLK_AHB 263
  279. #define JH7110_STG_AHB_DEC_CLK_AHB 264
  280. #define JH7110_NOC_BUS_CLK2_GPU_AXI 265
  281. #define JH7110_ISP_TOP_CLK_DVP 266
  282. #define JH7110_NOC_BUS_CLK2_ISP_AXI 267
  283. #define JH7110_ISP_TOP_CLK_BIST_APB 268
  284. #define JH7110_NOC_BUS_CLK2_DISP_AXI 269
  285. #define JH7110_VOUT_TOP_CLK_HDMITX0_BCLK 270
  286. #define JH7110_VOUT_TOP_U0_HDMI_TX_PIN_WS 271
  287. #define JH7110_VOUT_TOP_CLK_HDMIPHY_REF 272
  288. #define JH7110_VOUT_TOP_BIST_PCLK 273
  289. #define JH7110_AXIMEM0_128B_CLK_AXI 274
  290. #define JH7110_VDEC_INTSRAM_CLK_VDEC_AXI 275
  291. #define JH7110_NOC_BUS_CLK2_VDEC_AXI 276
  292. #define JH7110_AXIMEM1_128B_CLK_AXI 277
  293. #define JH7110_VENC_INTSRAM_CLK_VENC_AXI 278
  294. #define JH7110_NOC_BUS_CLK2_VENC_AXI 279
  295. #define JH7110_SRAM_CLK_ROM 280
  296. #define JH7110_NOC_BUS_CLK2_STG_AXI 281
  297. #define JH7110_GMAC5_CLK_RMII 282
  298. #define JH7110_AON_AHB 283
  299. #define JH7110_SYS_CRG_PCLK 284
  300. #define JH7110_SYS_SYSCON_PCLK 285
  301. #define JH7110_SPI0_CLK_CORE 286
  302. #define JH7110_SPI1_CLK_CORE 287
  303. #define JH7110_SPI2_CLK_CORE 288
  304. #define JH7110_SPI3_CLK_CORE 289
  305. #define JH7110_SPI4_CLK_CORE 290
  306. #define JH7110_SPI5_CLK_CORE 291
  307. #define JH7110_SPI6_CLK_CORE 292
  308. #define JH7110_I2C0_CLK_CORE 293
  309. #define JH7110_I2C1_CLK_CORE 294
  310. #define JH7110_I2C2_CLK_CORE 295
  311. #define JH7110_I2C3_CLK_CORE 296
  312. #define JH7110_I2C4_CLK_CORE 297
  313. #define JH7110_I2C5_CLK_CORE 298
  314. #define JH7110_I2C6_CLK_CORE 299
  315. #define JH7110_I2STX_BCLK_MST 300
  316. #define JH7110_I2STX_LRCK_MST 301
  317. #define JH7110_I2SRX_BCLK_MST 302
  318. #define JH7110_I2SRX_LRCK_MST 303
  319. #define JH7110_PDM_CLK_DMIC0_BCLK_SLV 304
  320. #define JH7110_PDM_CLK_DMIC0_LRCK_SLV 305
  321. #define JH7110_PDM_CLK_DMIC1_BCLK_SLV 306
  322. #define JH7110_PDM_CLK_DMIC1_LRCK_SLV 307
  323. #define JH7110_TDM_CLK_MST 308
  324. #define JH7110_AHB2APB_CLK_AHB 309
  325. #define JH7110_P2P_ASYNC_CLK_APBS 310
  326. #define JH7110_P2P_ASYNC_CLK_APBM 311
  327. #define JH7110_JTAG_DAISY_CHAIN_JTAG_TCK 312
  328. #define JH7110_U7_DEBUG_SYSTEMJTAG_JTAG_TCK 313
  329. #define JH7110_E2_DEBUG_SYSTEMJTAG_TCK 314
  330. #define JH7110_JTAG_CERTIFICATION_TCK 315
  331. #define JH7110_SEC_SKP_CLK 316
  332. #define JH7110_U2_PCLK_MUX_PCLK 317
  333. #define JH7110_CLK_SYS_END 318
  334. /* stg other */
  335. #define JH7110_PCIE0_CLK_AXI_SLV0 318
  336. #define JH7110_PCIE0_CLK_AXI_SLV 319
  337. #define JH7110_PCIE0_CLK_OSC 320
  338. #define JH7110_PCIE1_CLK_AXI_SLV0 321
  339. #define JH7110_PCIE1_CLK_AXI_SLV 322
  340. #define JH7110_PCIE1_CLK_OSC 323
  341. #define JH7110_E2_IRQ_SYNC_CLK_CORE 324
  342. #define JH7110_STG_CRG_PCLK 325
  343. #define JH7110_STG_SYSCON_PCLK 326
  344. #define JH7110_CLK_STG_END 327
  345. /* aon other */
  346. #define JH7110_U0_GMAC5_CLK_PTP 327
  347. #define JH7110_U0_GMAC5_CLK_RMII 328
  348. #define JH7110_AON_SYSCON_PCLK 329
  349. #define JH7110_AON_IOMUX_PCLK 330
  350. #define JH7110_AON_CRG_PCLK 331
  351. #define JH7110_PMU_CLK_APB 332
  352. #define JH7110_PMU_CLK_WKUP 333
  353. #define JH7110_RTC_HMS_CLK_OSC32K_G 334
  354. #define JH7110_32K_OUT 335
  355. #define JH7110_RESET0_CTRL_CLK_SRC 336
  356. /* aon other and source */
  357. #define JH7110_PCLK_MUX_FUNC_PCLK 337
  358. #define JH7110_PCLK_MUX_BIST_PCLK 338
  359. #define JH7110_CLK_END 339
  360. /* sys external clocks */
  361. #define JH7110_OSC (JH7110_CLK_END + 0)
  362. #define JH7110_GMAC1_RMII_REFIN (JH7110_CLK_END + 1)
  363. #define JH7110_GMAC1_RGMII_RXIN (JH7110_CLK_END + 2)
  364. #define JH7110_I2STX_BCLK_EXT (JH7110_CLK_END + 3)
  365. #define JH7110_I2STX_LRCK_EXT (JH7110_CLK_END + 4)
  366. #define JH7110_I2SRX_BCLK_EXT (JH7110_CLK_END + 5)
  367. #define JH7110_I2SRX_LRCK_EXT (JH7110_CLK_END + 6)
  368. #define JH7110_TDM_EXT (JH7110_CLK_END + 7)
  369. #define JH7110_MCLK_EXT (JH7110_CLK_END + 8)
  370. #define JH7110_JTAG_TCK_INNER (JH7110_CLK_END + 9)
  371. #define JH7110_BIST_APB (JH7110_CLK_END + 10)
  372. /* stg external clocks */
  373. #define JH7110_STG_APB (JH7110_CLK_END + 11)
  374. /* aon external clocks */
  375. #define JH7110_GMAC0_RMII_REFIN (JH7110_CLK_END + 12)
  376. #define JH7110_GMAC0_RGMII_RXIN (JH7110_CLK_END + 13)
  377. #define JH7110_CLK_RTC (JH7110_CLK_END + 14)
  378. #define JH7110_CLK_VOUT_START (JH7110_CLK_RTC + 1)
  379. /* vout regisger */
  380. #define JH7110_APB (JH7110_CLK_VOUT_START + 0)
  381. #define JH7110_DC8200_PIX0 (JH7110_CLK_VOUT_START + 1)
  382. #define JH7110_DSI_SYS (JH7110_CLK_VOUT_START + 2)
  383. #define JH7110_TX_ESC (JH7110_CLK_VOUT_START + 3)
  384. #define JH7110_U0_DC8200_CLK_AXI (JH7110_CLK_VOUT_START + 4)
  385. #define JH7110_U0_DC8200_CLK_CORE (JH7110_CLK_VOUT_START + 5)
  386. #define JH7110_U0_DC8200_CLK_AHB (JH7110_CLK_VOUT_START + 6)
  387. #define JH7110_U0_DC8200_CLK_PIX0 (JH7110_CLK_VOUT_START + 7)
  388. #define JH7110_U0_DC8200_CLK_PIX1 (JH7110_CLK_VOUT_START + 8)
  389. #define JH7110_DOM_VOUT_TOP_LCD_CLK (JH7110_CLK_VOUT_START + 9)
  390. #define JH7110_U0_CDNS_DSITX_CLK_APB (JH7110_CLK_VOUT_START + 10)
  391. #define JH7110_U0_CDNS_DSITX_CLK_SYS (JH7110_CLK_VOUT_START + 11)
  392. #define JH7110_U0_CDNS_DSITX_CLK_DPI (JH7110_CLK_VOUT_START + 12)
  393. #define JH7110_U0_CDNS_DSITX_CLK_TXESC (JH7110_CLK_VOUT_START + 13)
  394. #define JH7110_U0_MIPITX_DPHY_CLK_TXESC (JH7110_CLK_VOUT_START + 14)
  395. #define JH7110_U0_HDMI_TX_CLK_MCLK (JH7110_CLK_VOUT_START + 15)
  396. #define JH7110_U0_HDMI_TX_CLK_BCLK (JH7110_CLK_VOUT_START + 16)
  397. #define JH7110_U0_HDMI_TX_CLK_SYS (JH7110_CLK_VOUT_START + 17)
  398. #define JH7110_CLK_VOUT_REG_END (JH7110_CLK_VOUT_START + 18)
  399. /* vout other */
  400. #define JH7110_DISP_ROOT (JH7110_CLK_VOUT_START + 18)
  401. #define JH7110_DISP_AXI (JH7110_CLK_VOUT_START + 19)
  402. #define JH7110_DISP_AHB (JH7110_CLK_VOUT_START + 20)
  403. #define JH7110_HDMI_PHY_REF (JH7110_CLK_VOUT_START + 21)
  404. #define JH7110_HDMITX0_MCLK (JH7110_CLK_VOUT_START + 22)
  405. #define JH7110_HDMITX0_SCK (JH7110_CLK_VOUT_START + 23)
  406. #define JH7110_MIPI_DPHY_REF (JH7110_CLK_VOUT_START + 24)
  407. #define JH7110_U0_PCLK_MUX_BIST_PCLK (JH7110_CLK_VOUT_START + 25)
  408. #define JH7110_DISP_APB (JH7110_CLK_VOUT_START + 26)
  409. #define JH7110_U0_PCLK_MUX_FUNC_PCLK (JH7110_CLK_VOUT_START + 27)
  410. #define JH7110_U0_DOM_VOUT_CRG_PCLK (JH7110_CLK_VOUT_START + 28)
  411. #define JH7110_U0_DOM_VOUT_SYSCON_PCLK (JH7110_CLK_VOUT_START + 29)
  412. #define JH7110_U0_SAIF_AMBA_DOM_VOUT_AHB_DEC_CLK_AHB (JH7110_CLK_VOUT_START + 30)
  413. #define JH7110_U0_AHB2APB_CLK_AHB (JH7110_CLK_VOUT_START + 31)
  414. #define JH7110_U0_P2P_ASYNC_CLK_APBS (JH7110_CLK_VOUT_START + 32)
  415. #define JH7110_U0_CDNS_DSITX_CLK_RXESC (JH7110_CLK_VOUT_START + 33)
  416. #define JH7110_U0_CDNS_DSITX_CLK_TXBYTEHS (JH7110_CLK_VOUT_START + 34)
  417. #define JH7110_U0_MIPITX_DPHY_CLK_SYS (JH7110_CLK_VOUT_START + 35)
  418. #define JH7110_U0_MIPITX_DPHY_CLK_DPHY_REF (JH7110_CLK_VOUT_START + 36)
  419. #define JH7110_U0_MIPITX_APBIF_PCLK (JH7110_CLK_VOUT_START + 37)
  420. #define JH7110_HDMI_TX_CLK_REF (JH7110_CLK_VOUT_START + 38)
  421. #define JH7110_U0_DC8200_CLK_PIX0_OUT (JH7110_CLK_VOUT_START + 39)
  422. #define JH7110_U0_DC8200_CLK_PIX1_OUT (JH7110_CLK_VOUT_START + 40)
  423. #define JH7110_CLK_VOUT_END (JH7110_CLK_VOUT_START + 41)
  424. /* vout external clocks */
  425. #define JH7110_HDMITX0_PIXELCLK (JH7110_CLK_VOUT_END + 0)
  426. #define JH7110_MIPITX_DPHY_RXESC (JH7110_CLK_VOUT_END + 1)
  427. #define JH7110_MIPITX_DPHY_TXBYTEHS (JH7110_CLK_VOUT_END + 2)
  428. #endif /* __DT_BINDINGS_CLOCK_STARFIVE_JH7110_H__ */