gadget.h 44 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * USBSS device controller driver header file
  4. *
  5. * Copyright (C) 2018-2019 Cadence.
  6. * Copyright (C) 2017-2018 NXP
  7. *
  8. * Author: Pawel Laszczak <pawell@cadence.com>
  9. * Pawel Jez <pjez@cadence.com>
  10. * Peter Chen <peter.chen@nxp.com>
  11. */
  12. #ifndef __LINUX_CDNS3_GADGET
  13. #define __LINUX_CDNS3_GADGET
  14. #include <linux/bitops.h>
  15. #include <linux/usb/gadget.h>
  16. /*
  17. * USBSS-DEV register interface.
  18. * This corresponds to the USBSS Device Controller Interface
  19. */
  20. /**
  21. * struct cdns3_usb_regs - device controller registers.
  22. * @usb_conf: Global Configuration.
  23. * @usb_sts: Global Status.
  24. * @usb_cmd: Global Command.
  25. * @usb_itpn: ITP/SOF number.
  26. * @usb_lpm: Global Command.
  27. * @usb_ien: USB Interrupt Enable.
  28. * @usb_ists: USB Interrupt Status.
  29. * @ep_sel: Endpoint Select.
  30. * @ep_traddr: Endpoint Transfer Ring Address.
  31. * @ep_cfg: Endpoint Configuration.
  32. * @ep_cmd: Endpoint Command.
  33. * @ep_sts: Endpoint Status.
  34. * @ep_sts_sid: Endpoint Status.
  35. * @ep_sts_en: Endpoint Status Enable.
  36. * @drbl: Doorbell.
  37. * @ep_ien: EP Interrupt Enable.
  38. * @ep_ists: EP Interrupt Status.
  39. * @usb_pwr: Global Power Configuration.
  40. * @usb_conf2: Global Configuration 2.
  41. * @usb_cap1: Capability 1.
  42. * @usb_cap2: Capability 2.
  43. * @usb_cap3: Capability 3.
  44. * @usb_cap4: Capability 4.
  45. * @usb_cap5: Capability 5.
  46. * @usb_cap6: Capability 6.
  47. * @usb_cpkt1: Custom Packet 1.
  48. * @usb_cpkt2: Custom Packet 2.
  49. * @usb_cpkt3: Custom Packet 3.
  50. * @ep_dma_ext_addr: Upper address for DMA operations.
  51. * @buf_addr: Address for On-chip Buffer operations.
  52. * @buf_data: Data for On-chip Buffer operations.
  53. * @buf_ctrl: On-chip Buffer Access Control.
  54. * @dtrans: DMA Transfer Mode.
  55. * @tdl_from_trb: Source of TD Configuration.
  56. * @tdl_beh: TDL Behavior Configuration.
  57. * @ep_tdl: Endpoint TDL.
  58. * @tdl_beh2: TDL Behavior 2 Configuration.
  59. * @dma_adv_td: DMA Advance TD Configuration.
  60. * @reserved1: Reserved.
  61. * @cfg_regs: Configuration.
  62. * @reserved2: Reserved.
  63. * @dma_axi_ctrl: AXI Control.
  64. * @dma_axi_id: AXI ID register.
  65. * @dma_axi_cap: AXI Capability.
  66. * @dma_axi_ctrl0: AXI Control 0.
  67. * @dma_axi_ctrl1: AXI Control 1.
  68. */
  69. struct cdns3_usb_regs {
  70. __le32 usb_conf;
  71. __le32 usb_sts;
  72. __le32 usb_cmd;
  73. __le32 usb_itpn;
  74. __le32 usb_lpm;
  75. __le32 usb_ien;
  76. __le32 usb_ists;
  77. __le32 ep_sel;
  78. __le32 ep_traddr;
  79. __le32 ep_cfg;
  80. __le32 ep_cmd;
  81. __le32 ep_sts;
  82. __le32 ep_sts_sid;
  83. __le32 ep_sts_en;
  84. __le32 drbl;
  85. __le32 ep_ien;
  86. __le32 ep_ists;
  87. __le32 usb_pwr;
  88. __le32 usb_conf2;
  89. __le32 usb_cap1;
  90. __le32 usb_cap2;
  91. __le32 usb_cap3;
  92. __le32 usb_cap4;
  93. __le32 usb_cap5;
  94. __le32 usb_cap6;
  95. __le32 usb_cpkt1;
  96. __le32 usb_cpkt2;
  97. __le32 usb_cpkt3;
  98. __le32 ep_dma_ext_addr;
  99. __le32 buf_addr;
  100. __le32 buf_data;
  101. __le32 buf_ctrl;
  102. __le32 dtrans;
  103. __le32 tdl_from_trb;
  104. __le32 tdl_beh;
  105. __le32 ep_tdl;
  106. __le32 tdl_beh2;
  107. __le32 dma_adv_td;
  108. __le32 reserved1[26];
  109. __le32 cfg_reg1;
  110. __le32 dbg_link1;
  111. __le32 dbg_link2;
  112. __le32 cfg_regs[74];
  113. __le32 reserved2[51];
  114. __le32 dma_axi_ctrl;
  115. __le32 dma_axi_id;
  116. __le32 dma_axi_cap;
  117. __le32 dma_axi_ctrl0;
  118. __le32 dma_axi_ctrl1;
  119. };
  120. /* USB_CONF - bitmasks */
  121. /* Reset USB device configuration. */
  122. #define USB_CONF_CFGRST BIT(0)
  123. /* Set Configuration. */
  124. #define USB_CONF_CFGSET BIT(1)
  125. /* Disconnect USB device in SuperSpeed. */
  126. #define USB_CONF_USB3DIS BIT(3)
  127. /* Disconnect USB device in HS/FS */
  128. #define USB_CONF_USB2DIS BIT(4)
  129. /* Little Endian access - default */
  130. #define USB_CONF_LENDIAN BIT(5)
  131. /*
  132. * Big Endian access. Driver assume that byte order for
  133. * SFRs access always is as Little Endian so this bit
  134. * is not used.
  135. */
  136. #define USB_CONF_BENDIAN BIT(6)
  137. /* Device software reset. */
  138. #define USB_CONF_SWRST BIT(7)
  139. /* Singular DMA transfer mode. Only for VER < DEV_VER_V3*/
  140. #define USB_CONF_DSING BIT(8)
  141. /* Multiple DMA transfers mode. Only for VER < DEV_VER_V3 */
  142. #define USB_CONF_DMULT BIT(9)
  143. /* DMA clock turn-off enable. */
  144. #define USB_CONF_DMAOFFEN BIT(10)
  145. /* DMA clock turn-off disable. */
  146. #define USB_CONF_DMAOFFDS BIT(11)
  147. /* Clear Force Full Speed. */
  148. #define USB_CONF_CFORCE_FS BIT(12)
  149. /* Set Force Full Speed. */
  150. #define USB_CONF_SFORCE_FS BIT(13)
  151. /* Device enable. */
  152. #define USB_CONF_DEVEN BIT(14)
  153. /* Device disable. */
  154. #define USB_CONF_DEVDS BIT(15)
  155. /* L1 LPM state entry enable (used in HS/FS mode). */
  156. #define USB_CONF_L1EN BIT(16)
  157. /* L1 LPM state entry disable (used in HS/FS mode). */
  158. #define USB_CONF_L1DS BIT(17)
  159. /* USB 2.0 clock gate disable. */
  160. #define USB_CONF_CLK2OFFEN BIT(18)
  161. /* USB 2.0 clock gate enable. */
  162. #define USB_CONF_CLK2OFFDS BIT(19)
  163. /* L0 LPM state entry request (used in HS/FS mode). */
  164. #define USB_CONF_LGO_L0 BIT(20)
  165. /* USB 3.0 clock gate disable. */
  166. #define USB_CONF_CLK3OFFEN BIT(21)
  167. /* USB 3.0 clock gate enable. */
  168. #define USB_CONF_CLK3OFFDS BIT(22)
  169. /* Bit 23 is reserved*/
  170. /* U1 state entry enable (used in SS mode). */
  171. #define USB_CONF_U1EN BIT(24)
  172. /* U1 state entry disable (used in SS mode). */
  173. #define USB_CONF_U1DS BIT(25)
  174. /* U2 state entry enable (used in SS mode). */
  175. #define USB_CONF_U2EN BIT(26)
  176. /* U2 state entry disable (used in SS mode). */
  177. #define USB_CONF_U2DS BIT(27)
  178. /* U0 state entry request (used in SS mode). */
  179. #define USB_CONF_LGO_U0 BIT(28)
  180. /* U1 state entry request (used in SS mode). */
  181. #define USB_CONF_LGO_U1 BIT(29)
  182. /* U2 state entry request (used in SS mode). */
  183. #define USB_CONF_LGO_U2 BIT(30)
  184. /* SS.Inactive state entry request (used in SS mode) */
  185. #define USB_CONF_LGO_SSINACT BIT(31)
  186. /* USB_STS - bitmasks */
  187. /*
  188. * Configuration status.
  189. * 1 - device is in the configured state.
  190. * 0 - device is not configured.
  191. */
  192. #define USB_STS_CFGSTS_MASK BIT(0)
  193. #define USB_STS_CFGSTS(p) ((p) & USB_STS_CFGSTS_MASK)
  194. /*
  195. * On-chip memory overflow.
  196. * 0 - On-chip memory status OK.
  197. * 1 - On-chip memory overflow.
  198. */
  199. #define USB_STS_OV_MASK BIT(1)
  200. #define USB_STS_OV(p) ((p) & USB_STS_OV_MASK)
  201. /*
  202. * SuperSpeed connection status.
  203. * 0 - USB in SuperSpeed mode disconnected.
  204. * 1 - USB in SuperSpeed mode connected.
  205. */
  206. #define USB_STS_USB3CONS_MASK BIT(2)
  207. #define USB_STS_USB3CONS(p) ((p) & USB_STS_USB3CONS_MASK)
  208. /*
  209. * DMA transfer configuration status.
  210. * 0 - single request.
  211. * 1 - multiple TRB chain
  212. * Supported only for controller version < DEV_VER_V3
  213. */
  214. #define USB_STS_DTRANS_MASK BIT(3)
  215. #define USB_STS_DTRANS(p) ((p) & USB_STS_DTRANS_MASK)
  216. /*
  217. * Device speed.
  218. * 0 - Undefined (value after reset).
  219. * 1 - Low speed
  220. * 2 - Full speed
  221. * 3 - High speed
  222. * 4 - Super speed
  223. */
  224. #define USB_STS_USBSPEED_MASK GENMASK(6, 4)
  225. #define USB_STS_USBSPEED(p) (((p) & USB_STS_USBSPEED_MASK) >> 4)
  226. #define USB_STS_LS (0x1 << 4)
  227. #define USB_STS_FS (0x2 << 4)
  228. #define USB_STS_HS (0x3 << 4)
  229. #define USB_STS_SS (0x4 << 4)
  230. #define DEV_UNDEFSPEED(p) (((p) & USB_STS_USBSPEED_MASK) == (0x0 << 4))
  231. #define DEV_LOWSPEED(p) (((p) & USB_STS_USBSPEED_MASK) == USB_STS_LS)
  232. #define DEV_FULLSPEED(p) (((p) & USB_STS_USBSPEED_MASK) == USB_STS_FS)
  233. #define DEV_HIGHSPEED(p) (((p) & USB_STS_USBSPEED_MASK) == USB_STS_HS)
  234. #define DEV_SUPERSPEED(p) (((p) & USB_STS_USBSPEED_MASK) == USB_STS_SS)
  235. /*
  236. * Endianness for SFR access.
  237. * 0 - Little Endian order (default after hardware reset).
  238. * 1 - Big Endian order
  239. */
  240. #define USB_STS_ENDIAN_MASK BIT(7)
  241. #define USB_STS_ENDIAN(p) ((p) & USB_STS_ENDIAN_MASK)
  242. /*
  243. * HS/FS clock turn-off status.
  244. * 0 - hsfs clock is always on.
  245. * 1 - hsfs clock turn-off in L2 (HS/FS mode) is enabled
  246. * (default after hardware reset).
  247. */
  248. #define USB_STS_CLK2OFF_MASK BIT(8)
  249. #define USB_STS_CLK2OFF(p) ((p) & USB_STS_CLK2OFF_MASK)
  250. /*
  251. * PCLK clock turn-off status.
  252. * 0 - pclk clock is always on.
  253. * 1 - pclk clock turn-off in U3 (SS mode) is enabled
  254. * (default after hardware reset).
  255. */
  256. #define USB_STS_CLK3OFF_MASK BIT(9)
  257. #define USB_STS_CLK3OFF(p) ((p) & USB_STS_CLK3OFF_MASK)
  258. /*
  259. * Controller in reset state.
  260. * 0 - Internal reset is active.
  261. * 1 - Internal reset is not active and controller is fully operational.
  262. */
  263. #define USB_STS_IN_RST_MASK BIT(10)
  264. #define USB_STS_IN_RST(p) ((p) & USB_STS_IN_RST_MASK)
  265. /*
  266. * Status of the "TDL calculation basing on TRB" feature.
  267. * 0 - disabled
  268. * 1 - enabled
  269. * Supported only for DEV_VER_V2 controller version.
  270. */
  271. #define USB_STS_TDL_TRB_ENABLED BIT(11)
  272. /*
  273. * Device enable Status.
  274. * 0 - USB device is disabled (VBUS input is disconnected from internal logic).
  275. * 1 - USB device is enabled (VBUS input is connected to the internal logic).
  276. */
  277. #define USB_STS_DEVS_MASK BIT(14)
  278. #define USB_STS_DEVS(p) ((p) & USB_STS_DEVS_MASK)
  279. /*
  280. * Address status.
  281. * 0 - USB device is default state.
  282. * 1 - USB device is at least in address state.
  283. */
  284. #define USB_STS_ADDRESSED_MASK BIT(15)
  285. #define USB_STS_ADDRESSED(p) ((p) & USB_STS_ADDRESSED_MASK)
  286. /*
  287. * L1 LPM state enable status (used in HS/FS mode).
  288. * 0 - Entering to L1 LPM state disabled.
  289. * 1 - Entering to L1 LPM state enabled.
  290. */
  291. #define USB_STS_L1ENS_MASK BIT(16)
  292. #define USB_STS_L1ENS(p) ((p) & USB_STS_L1ENS_MASK)
  293. /*
  294. * Internal VBUS connection status (used both in HS/FS and SS mode).
  295. * 0 - internal VBUS is not detected.
  296. * 1 - internal VBUS is detected.
  297. */
  298. #define USB_STS_VBUSS_MASK BIT(17)
  299. #define USB_STS_VBUSS(p) ((p) & USB_STS_VBUSS_MASK)
  300. /*
  301. * HS/FS LPM state (used in FS/HS mode).
  302. * 0 - L0 State
  303. * 1 - L1 State
  304. * 2 - L2 State
  305. * 3 - L3 State
  306. */
  307. #define USB_STS_LPMST_MASK GENMASK(19, 18)
  308. #define DEV_L0_STATE(p) (((p) & USB_STS_LPMST_MASK) == (0x0 << 18))
  309. #define DEV_L1_STATE(p) (((p) & USB_STS_LPMST_MASK) == (0x1 << 18))
  310. #define DEV_L2_STATE(p) (((p) & USB_STS_LPMST_MASK) == (0x2 << 18))
  311. #define DEV_L3_STATE(p) (((p) & USB_STS_LPMST_MASK) == (0x3 << 18))
  312. /*
  313. * Disable HS status (used in FS/HS mode).
  314. * 0 - the disconnect bit for HS/FS mode is set .
  315. * 1 - the disconnect bit for HS/FS mode is not set.
  316. */
  317. #define USB_STS_USB2CONS_MASK BIT(20)
  318. #define USB_STS_USB2CONS(p) ((p) & USB_STS_USB2CONS_MASK)
  319. /*
  320. * HS/FS mode connection status (used in FS/HS mode).
  321. * 0 - High Speed operations in USB2.0 (FS/HS) mode not disabled.
  322. * 1 - High Speed operations in USB2.0 (FS/HS).
  323. */
  324. #define USB_STS_DISABLE_HS_MASK BIT(21)
  325. #define USB_STS_DISABLE_HS(p) ((p) & USB_STS_DISABLE_HS_MASK)
  326. /*
  327. * U1 state enable status (used in SS mode).
  328. * 0 - Entering to U1 state disabled.
  329. * 1 - Entering to U1 state enabled.
  330. */
  331. #define USB_STS_U1ENS_MASK BIT(24)
  332. #define USB_STS_U1ENS(p) ((p) & USB_STS_U1ENS_MASK)
  333. /*
  334. * U2 state enable status (used in SS mode).
  335. * 0 - Entering to U2 state disabled.
  336. * 1 - Entering to U2 state enabled.
  337. */
  338. #define USB_STS_U2ENS_MASK BIT(25)
  339. #define USB_STS_U2ENS(p) ((p) & USB_STS_U2ENS_MASK)
  340. /*
  341. * SuperSpeed Link LTSSM state. This field reflects USBSS-DEV current
  342. * SuperSpeed link state
  343. */
  344. #define USB_STS_LST_MASK GENMASK(29, 26)
  345. #define DEV_LST_U0 (((p) & USB_STS_LST_MASK) == (0x0 << 26))
  346. #define DEV_LST_U1 (((p) & USB_STS_LST_MASK) == (0x1 << 26))
  347. #define DEV_LST_U2 (((p) & USB_STS_LST_MASK) == (0x2 << 26))
  348. #define DEV_LST_U3 (((p) & USB_STS_LST_MASK) == (0x3 << 26))
  349. #define DEV_LST_DISABLED (((p) & USB_STS_LST_MASK) == (0x4 << 26))
  350. #define DEV_LST_RXDETECT (((p) & USB_STS_LST_MASK) == (0x5 << 26))
  351. #define DEV_LST_INACTIVE (((p) & USB_STS_LST_MASK) == (0x6 << 26))
  352. #define DEV_LST_POLLING (((p) & USB_STS_LST_MASK) == (0x7 << 26))
  353. #define DEV_LST_RECOVERY (((p) & USB_STS_LST_MASK) == (0x8 << 26))
  354. #define DEV_LST_HOT_RESET (((p) & USB_STS_LST_MASK) == (0x9 << 26))
  355. #define DEV_LST_COMP_MODE (((p) & USB_STS_LST_MASK) == (0xa << 26))
  356. #define DEV_LST_LB_STATE (((p) & USB_STS_LST_MASK) == (0xb << 26))
  357. /*
  358. * DMA clock turn-off status.
  359. * 0 - DMA clock is always on (default after hardware reset).
  360. * 1 - DMA clock turn-off in U1, U2 and U3 (SS mode) is enabled.
  361. */
  362. #define USB_STS_DMAOFF_MASK BIT(30)
  363. #define USB_STS_DMAOFF(p) ((p) & USB_STS_DMAOFF_MASK)
  364. /*
  365. * SFR Endian status.
  366. * 0 - Little Endian order (default after hardware reset).
  367. * 1 - Big Endian order.
  368. */
  369. #define USB_STS_ENDIAN2_MASK BIT(31)
  370. #define USB_STS_ENDIAN2(p) ((p) & USB_STS_ENDIAN2_MASK)
  371. /* USB_CMD - bitmasks */
  372. /* Set Function Address */
  373. #define USB_CMD_SET_ADDR BIT(0)
  374. /*
  375. * Function Address This field is saved to the device only when the field
  376. * SET_ADDR is set '1 ' during write to USB_CMD register.
  377. * Software is responsible for entering the address of the device during
  378. * SET_ADDRESS request service. This field should be set immediately after
  379. * the SETUP packet is decoded, and prior to confirmation of the status phase
  380. */
  381. #define USB_CMD_FADDR_MASK GENMASK(7, 1)
  382. #define USB_CMD_FADDR(p) (((p) << 1) & USB_CMD_FADDR_MASK)
  383. /* Send Function Wake Device Notification TP (used only in SS mode). */
  384. #define USB_CMD_SDNFW BIT(8)
  385. /* Set Test Mode (used only in HS/FS mode). */
  386. #define USB_CMD_STMODE BIT(9)
  387. /* Test mode selector (used only in HS/FS mode) */
  388. #define USB_STS_TMODE_SEL_MASK GENMASK(11, 10)
  389. #define USB_STS_TMODE_SEL(p) (((p) << 10) & USB_STS_TMODE_SEL_MASK)
  390. /*
  391. * Send Latency Tolerance Message Device Notification TP (used only
  392. * in SS mode).
  393. */
  394. #define USB_CMD_SDNLTM BIT(12)
  395. /* Send Custom Transaction Packet (used only in SS mode) */
  396. #define USB_CMD_SPKT BIT(13)
  397. /*Device Notification 'Function Wake' - Interface value (only in SS mode. */
  398. #define USB_CMD_DNFW_INT_MASK GENMASK(23, 16)
  399. #define USB_STS_DNFW_INT(p) (((p) << 16) & USB_CMD_DNFW_INT_MASK)
  400. /*
  401. * Device Notification 'Latency Tolerance Message' -373 BELT value [7:0]
  402. * (used only in SS mode).
  403. */
  404. #define USB_CMD_DNLTM_BELT_MASK GENMASK(27, 16)
  405. #define USB_STS_DNLTM_BELT(p) (((p) << 16) & USB_CMD_DNLTM_BELT_MASK)
  406. /* USB_ITPN - bitmasks */
  407. /*
  408. * ITP(SS) / SOF (HS/FS) number
  409. * In SS mode this field represent number of last ITP received from host.
  410. * In HS/FS mode this field represent number of last SOF received from host.
  411. */
  412. #define USB_ITPN_MASK GENMASK(13, 0)
  413. #define USB_ITPN(p) ((p) & USB_ITPN_MASK)
  414. /* USB_LPM - bitmasks */
  415. /* Host Initiated Resume Duration. */
  416. #define USB_LPM_HIRD_MASK GENMASK(3, 0)
  417. #define USB_LPM_HIRD(p) ((p) & USB_LPM_HIRD_MASK)
  418. /* Remote Wakeup Enable (bRemoteWake). */
  419. #define USB_LPM_BRW BIT(4)
  420. /* USB_IEN - bitmasks */
  421. /* SS connection interrupt enable */
  422. #define USB_IEN_CONIEN BIT(0)
  423. /* SS disconnection interrupt enable. */
  424. #define USB_IEN_DISIEN BIT(1)
  425. /* USB SS warm reset interrupt enable. */
  426. #define USB_IEN_UWRESIEN BIT(2)
  427. /* USB SS hot reset interrupt enable */
  428. #define USB_IEN_UHRESIEN BIT(3)
  429. /* SS link U3 state enter interrupt enable (suspend).*/
  430. #define USB_IEN_U3ENTIEN BIT(4)
  431. /* SS link U3 state exit interrupt enable (wakeup). */
  432. #define USB_IEN_U3EXTIEN BIT(5)
  433. /* SS link U2 state enter interrupt enable.*/
  434. #define USB_IEN_U2ENTIEN BIT(6)
  435. /* SS link U2 state exit interrupt enable.*/
  436. #define USB_IEN_U2EXTIEN BIT(7)
  437. /* SS link U1 state enter interrupt enable.*/
  438. #define USB_IEN_U1ENTIEN BIT(8)
  439. /* SS link U1 state exit interrupt enable.*/
  440. #define USB_IEN_U1EXTIEN BIT(9)
  441. /* ITP/SOF packet detected interrupt enable.*/
  442. #define USB_IEN_ITPIEN BIT(10)
  443. /* Wakeup interrupt enable.*/
  444. #define USB_IEN_WAKEIEN BIT(11)
  445. /* Send Custom Packet interrupt enable.*/
  446. #define USB_IEN_SPKTIEN BIT(12)
  447. /* HS/FS mode connection interrupt enable.*/
  448. #define USB_IEN_CON2IEN BIT(16)
  449. /* HS/FS mode disconnection interrupt enable.*/
  450. #define USB_IEN_DIS2IEN BIT(17)
  451. /* USB reset (HS/FS mode) interrupt enable.*/
  452. #define USB_IEN_U2RESIEN BIT(18)
  453. /* LPM L2 state enter interrupt enable.*/
  454. #define USB_IEN_L2ENTIEN BIT(20)
  455. /* LPM L2 state exit interrupt enable.*/
  456. #define USB_IEN_L2EXTIEN BIT(21)
  457. /* LPM L1 state enter interrupt enable.*/
  458. #define USB_IEN_L1ENTIEN BIT(24)
  459. /* LPM L1 state exit interrupt enable.*/
  460. #define USB_IEN_L1EXTIEN BIT(25)
  461. /* Configuration reset interrupt enable.*/
  462. #define USB_IEN_CFGRESIEN BIT(26)
  463. /* Start of the USB SS warm reset interrupt enable.*/
  464. #define USB_IEN_UWRESSIEN BIT(28)
  465. /* End of the USB SS warm reset interrupt enable.*/
  466. #define USB_IEN_UWRESEIEN BIT(29)
  467. #define USB_IEN_INIT (USB_IEN_U2RESIEN | USB_ISTS_DIS2I | USB_IEN_CON2IEN \
  468. | USB_IEN_UHRESIEN | USB_IEN_UWRESIEN | USB_IEN_DISIEN \
  469. | USB_IEN_CONIEN | USB_IEN_U3EXTIEN | USB_IEN_L2ENTIEN \
  470. | USB_IEN_L2EXTIEN | USB_IEN_L1ENTIEN | USB_IEN_U3ENTIEN)
  471. /* USB_ISTS - bitmasks */
  472. /* SS Connection detected. */
  473. #define USB_ISTS_CONI BIT(0)
  474. /* SS Disconnection detected. */
  475. #define USB_ISTS_DISI BIT(1)
  476. /* UUSB warm reset detectede. */
  477. #define USB_ISTS_UWRESI BIT(2)
  478. /* USB hot reset detected. */
  479. #define USB_ISTS_UHRESI BIT(3)
  480. /* U3 link state enter detected (suspend).*/
  481. #define USB_ISTS_U3ENTI BIT(4)
  482. /* U3 link state exit detected (wakeup). */
  483. #define USB_ISTS_U3EXTI BIT(5)
  484. /* U2 link state enter detected.*/
  485. #define USB_ISTS_U2ENTI BIT(6)
  486. /* U2 link state exit detected.*/
  487. #define USB_ISTS_U2EXTI BIT(7)
  488. /* U1 link state enter detected.*/
  489. #define USB_ISTS_U1ENTI BIT(8)
  490. /* U1 link state exit detected.*/
  491. #define USB_ISTS_U1EXTI BIT(9)
  492. /* ITP/SOF packet detected.*/
  493. #define USB_ISTS_ITPI BIT(10)
  494. /* Wakeup detected.*/
  495. #define USB_ISTS_WAKEI BIT(11)
  496. /* Send Custom Packet detected.*/
  497. #define USB_ISTS_SPKTI BIT(12)
  498. /* HS/FS mode connection detected.*/
  499. #define USB_ISTS_CON2I BIT(16)
  500. /* HS/FS mode disconnection detected.*/
  501. #define USB_ISTS_DIS2I BIT(17)
  502. /* USB reset (HS/FS mode) detected.*/
  503. #define USB_ISTS_U2RESI BIT(18)
  504. /* LPM L2 state enter detected.*/
  505. #define USB_ISTS_L2ENTI BIT(20)
  506. /* LPM L2 state exit detected.*/
  507. #define USB_ISTS_L2EXTI BIT(21)
  508. /* LPM L1 state enter detected.*/
  509. #define USB_ISTS_L1ENTI BIT(24)
  510. /* LPM L1 state exit detected.*/
  511. #define USB_ISTS_L1EXTI BIT(25)
  512. /* USB configuration reset detected.*/
  513. #define USB_ISTS_CFGRESI BIT(26)
  514. /* Start of the USB warm reset detected.*/
  515. #define USB_ISTS_UWRESSI BIT(28)
  516. /* End of the USB warm reset detected.*/
  517. #define USB_ISTS_UWRESEI BIT(29)
  518. /* USB_SEL - bitmasks */
  519. #define EP_SEL_EPNO_MASK GENMASK(3, 0)
  520. /* Endpoint number. */
  521. #define EP_SEL_EPNO(p) ((p) & EP_SEL_EPNO_MASK)
  522. /* Endpoint direction bit - 0 - OUT, 1 - IN. */
  523. #define EP_SEL_DIR BIT(7)
  524. #define select_ep_in(nr) (EP_SEL_EPNO(p) | EP_SEL_DIR)
  525. #define select_ep_out (EP_SEL_EPNO(p))
  526. /* EP_TRADDR - bitmasks */
  527. /* Transfer Ring address. */
  528. #define EP_TRADDR_TRADDR(p) ((p))
  529. /* EP_CFG - bitmasks */
  530. /* Endpoint enable */
  531. #define EP_CFG_ENABLE BIT(0)
  532. /*
  533. * Endpoint type.
  534. * 1 - isochronous
  535. * 2 - bulk
  536. * 3 - interrupt
  537. */
  538. #define EP_CFG_EPTYPE_MASK GENMASK(2, 1)
  539. #define EP_CFG_EPTYPE(p) (((p) << 1) & EP_CFG_EPTYPE_MASK)
  540. /* Stream support enable (only in SS mode). */
  541. #define EP_CFG_STREAM_EN BIT(3)
  542. /* TDL check (only in SS mode for BULK EP). */
  543. #define EP_CFG_TDL_CHK BIT(4)
  544. /* SID check (only in SS mode for BULK OUT EP). */
  545. #define EP_CFG_SID_CHK BIT(5)
  546. /* DMA transfer endianness. */
  547. #define EP_CFG_EPENDIAN BIT(7)
  548. /* Max burst size (used only in SS mode). */
  549. #define EP_CFG_MAXBURST_MASK GENMASK(11, 8)
  550. #define EP_CFG_MAXBURST(p) (((p) << 8) & EP_CFG_MAXBURST_MASK)
  551. /* ISO max burst. */
  552. #define EP_CFG_MULT_MASK GENMASK(15, 14)
  553. #define EP_CFG_MULT(p) (((p) << 14) & EP_CFG_MULT_MASK)
  554. /* ISO max burst. */
  555. #define EP_CFG_MAXPKTSIZE_MASK GENMASK(26, 16)
  556. #define EP_CFG_MAXPKTSIZE(p) (((p) << 16) & EP_CFG_MAXPKTSIZE_MASK)
  557. /* Max number of buffered packets. */
  558. #define EP_CFG_BUFFERING_MASK GENMASK(31, 27)
  559. #define EP_CFG_BUFFERING(p) (((p) << 27) & EP_CFG_BUFFERING_MASK)
  560. /* EP_CMD - bitmasks */
  561. /* Endpoint reset. */
  562. #define EP_CMD_EPRST BIT(0)
  563. /* Endpoint STALL set. */
  564. #define EP_CMD_SSTALL BIT(1)
  565. /* Endpoint STALL clear. */
  566. #define EP_CMD_CSTALL BIT(2)
  567. /* Send ERDY TP. */
  568. #define EP_CMD_ERDY BIT(3)
  569. /* Request complete. */
  570. #define EP_CMD_REQ_CMPL BIT(5)
  571. /* Transfer descriptor ready. */
  572. #define EP_CMD_DRDY BIT(6)
  573. /* Data flush. */
  574. #define EP_CMD_DFLUSH BIT(7)
  575. /*
  576. * Transfer Descriptor Length write (used only for Bulk Stream capable
  577. * endpoints in SS mode).
  578. * Bit Removed from DEV_VER_V3 controller version.
  579. */
  580. #define EP_CMD_STDL BIT(8)
  581. /*
  582. * Transfer Descriptor Length (used only in SS mode for bulk endpoints).
  583. * Bits Removed from DEV_VER_V3 controller version.
  584. */
  585. #define EP_CMD_TDL_MASK GENMASK(15, 9)
  586. #define EP_CMD_TDL_SET(p) (((p) << 9) & EP_CMD_TDL_MASK)
  587. #define EP_CMD_TDL_GET(p) (((p) & EP_CMD_TDL_MASK) >> 9)
  588. /* ERDY Stream ID value (used in SS mode). */
  589. #define EP_CMD_ERDY_SID_MASK GENMASK(31, 16)
  590. #define EP_CMD_ERDY_SID(p) (((p) << 16) & EP_CMD_ERDY_SID_MASK)
  591. /* EP_STS - bitmasks */
  592. /* Setup transfer complete. */
  593. #define EP_STS_SETUP BIT(0)
  594. /* Endpoint STALL status. */
  595. #define EP_STS_STALL(p) ((p) & BIT(1))
  596. /* Interrupt On Complete. */
  597. #define EP_STS_IOC BIT(2)
  598. /* Interrupt on Short Packet. */
  599. #define EP_STS_ISP BIT(3)
  600. /* Transfer descriptor missing. */
  601. #define EP_STS_DESCMIS BIT(4)
  602. /* Stream Rejected (used only in SS mode) */
  603. #define EP_STS_STREAMR BIT(5)
  604. /* EXIT from MOVE DATA State (used only for stream transfers in SS mode). */
  605. #define EP_STS_MD_EXIT BIT(6)
  606. /* TRB error. */
  607. #define EP_STS_TRBERR BIT(7)
  608. /* Not ready (used only in SS mode). */
  609. #define EP_STS_NRDY BIT(8)
  610. /* DMA busy bit. */
  611. #define EP_STS_DBUSY BIT(9)
  612. /* Endpoint Buffer Empty */
  613. #define EP_STS_BUFFEMPTY(p) ((p) & BIT(10))
  614. /* Current Cycle Status */
  615. #define EP_STS_CCS(p) ((p) & BIT(11))
  616. /* Prime (used only in SS mode. */
  617. #define EP_STS_PRIME BIT(12)
  618. /* Stream error (used only in SS mode). */
  619. #define EP_STS_SIDERR BIT(13)
  620. /* OUT size mismatch. */
  621. #define EP_STS_OUTSMM BIT(14)
  622. /* ISO transmission error. */
  623. #define EP_STS_ISOERR BIT(15)
  624. /* Host Packet Pending (only for SS mode). */
  625. #define EP_STS_HOSTPP(p) ((p) & BIT(16))
  626. /* Stream Protocol State Machine State (only for Bulk stream endpoints). */
  627. #define EP_STS_SPSMST_MASK GENMASK(18, 17)
  628. #define EP_STS_SPSMST_DISABLED(p) (((p) & EP_STS_SPSMST_MASK) >> 17)
  629. #define EP_STS_SPSMST_IDLE(p) (((p) & EP_STS_SPSMST_MASK) >> 17)
  630. #define EP_STS_SPSMST_START_STREAM(p) (((p) & EP_STS_SPSMST_MASK) >> 17)
  631. #define EP_STS_SPSMST_MOVE_DATA(p) (((p) & EP_STS_SPSMST_MASK) >> 17)
  632. /* Interrupt On Transfer complete. */
  633. #define EP_STS_IOT BIT(19)
  634. /* OUT queue endpoint number. */
  635. #define EP_STS_OUTQ_NO_MASK GENMASK(27, 24)
  636. #define EP_STS_OUTQ_NO(p) (((p) & EP_STS_OUTQ_NO_MASK) >> 24)
  637. /* OUT queue valid flag. */
  638. #define EP_STS_OUTQ_VAL_MASK BIT(28)
  639. #define EP_STS_OUTQ_VAL(p) ((p) & EP_STS_OUTQ_VAL_MASK)
  640. /* SETUP WAIT. */
  641. #define EP_STS_STPWAIT BIT(31)
  642. /* EP_STS_SID - bitmasks */
  643. /* Stream ID (used only in SS mode). */
  644. #define EP_STS_SID_MASK GENMASK(15, 0)
  645. #define EP_STS_SID(p) ((p) & EP_STS_SID_MASK)
  646. /* EP_STS_EN - bitmasks */
  647. /* SETUP interrupt enable. */
  648. #define EP_STS_EN_SETUPEN BIT(0)
  649. /* OUT transfer missing descriptor enable. */
  650. #define EP_STS_EN_DESCMISEN BIT(4)
  651. /* Stream Rejected enable. */
  652. #define EP_STS_EN_STREAMREN BIT(5)
  653. /* Move Data Exit enable.*/
  654. #define EP_STS_EN_MD_EXITEN BIT(6)
  655. /* TRB enable. */
  656. #define EP_STS_EN_TRBERREN BIT(7)
  657. /* NRDY enable. */
  658. #define EP_STS_EN_NRDYEN BIT(8)
  659. /* Prime enable. */
  660. #define EP_STS_EN_PRIMEEEN BIT(12)
  661. /* Stream error enable. */
  662. #define EP_STS_EN_SIDERREN BIT(13)
  663. /* OUT size mismatch enable. */
  664. #define EP_STS_EN_OUTSMMEN BIT(14)
  665. /* ISO transmission error enable. */
  666. #define EP_STS_EN_ISOERREN BIT(15)
  667. /* Interrupt on Transmission complete enable. */
  668. #define EP_STS_EN_IOTEN BIT(19)
  669. /* Setup Wait interrupt enable. */
  670. #define EP_STS_EN_STPWAITEN BIT(31)
  671. /* DRBL- bitmasks */
  672. #define DB_VALUE_BY_INDEX(index) (1 << (index))
  673. #define DB_VALUE_EP0_OUT BIT(0)
  674. #define DB_VALUE_EP0_IN BIT(16)
  675. /* EP_IEN - bitmasks */
  676. #define EP_IEN(index) (1 << (index))
  677. #define EP_IEN_EP_OUT0 BIT(0)
  678. #define EP_IEN_EP_IN0 BIT(16)
  679. /* EP_ISTS - bitmasks */
  680. #define EP_ISTS(index) (1 << (index))
  681. #define EP_ISTS_EP_OUT0 BIT(0)
  682. #define EP_ISTS_EP_IN0 BIT(16)
  683. /* USB_PWR- bitmasks */
  684. /*Power Shut Off capability enable*/
  685. #define PUSB_PWR_PSO_EN BIT(0)
  686. /*Power Shut Off capability disable*/
  687. #define PUSB_PWR_PSO_DS BIT(1)
  688. /*
  689. * Enables turning-off Reference Clock.
  690. * This bit is optional and implemented only when support for OTG is
  691. * implemented (indicated by OTG_READY bit set to '1').
  692. */
  693. #define PUSB_PWR_STB_CLK_SWITCH_EN BIT(8)
  694. /*
  695. * Status bit indicating that operation required by STB_CLK_SWITCH_EN write
  696. * is completed
  697. */
  698. #define PUSB_PWR_STB_CLK_SWITCH_DONE BIT(9)
  699. /* This bit informs if Fast Registers Access is enabled. */
  700. #define PUSB_PWR_FST_REG_ACCESS_STAT BIT(30)
  701. /* Fast Registers Access Enable. */
  702. #define PUSB_PWR_FST_REG_ACCESS BIT(31)
  703. /* USB_CONF2- bitmasks */
  704. /*
  705. * Writing 1 disables TDL calculation basing on TRB feature in controller
  706. * for DMULT mode.
  707. * Bit supported only for DEV_VER_V2 version.
  708. */
  709. #define USB_CONF2_DIS_TDL_TRB BIT(1)
  710. /*
  711. * Writing 1 enables TDL calculation basing on TRB feature in controller
  712. * for DMULT mode.
  713. * Bit supported only for DEV_VER_V2 version.
  714. */
  715. #define USB_CONF2_EN_TDL_TRB BIT(2)
  716. /* USB_CAP1- bitmasks */
  717. /*
  718. * SFR Interface type
  719. * These field reflects type of SFR interface implemented:
  720. * 0x0 - OCP
  721. * 0x1 - AHB,
  722. * 0x2 - PLB
  723. * 0x3 - AXI
  724. * 0x4-0xF - reserved
  725. */
  726. #define USB_CAP1_SFR_TYPE_MASK GENMASK(3, 0)
  727. #define DEV_SFR_TYPE_OCP(p) (((p) & USB_CAP1_SFR_TYPE_MASK) == 0x0)
  728. #define DEV_SFR_TYPE_AHB(p) (((p) & USB_CAP1_SFR_TYPE_MASK) == 0x1)
  729. #define DEV_SFR_TYPE_PLB(p) (((p) & USB_CAP1_SFR_TYPE_MASK) == 0x2)
  730. #define DEV_SFR_TYPE_AXI(p) (((p) & USB_CAP1_SFR_TYPE_MASK) == 0x3)
  731. /*
  732. * SFR Interface width
  733. * These field reflects width of SFR interface implemented:
  734. * 0x0 - 8 bit interface,
  735. * 0x1 - 16 bit interface,
  736. * 0x2 - 32 bit interface
  737. * 0x3 - 64 bit interface
  738. * 0x4-0xF - reserved
  739. */
  740. #define USB_CAP1_SFR_WIDTH_MASK GENMASK(7, 4)
  741. #define DEV_SFR_WIDTH_8(p) (((p) & USB_CAP1_SFR_WIDTH_MASK) == (0x0 << 4))
  742. #define DEV_SFR_WIDTH_16(p) (((p) & USB_CAP1_SFR_WIDTH_MASK) == (0x1 << 4))
  743. #define DEV_SFR_WIDTH_32(p) (((p) & USB_CAP1_SFR_WIDTH_MASK) == (0x2 << 4))
  744. #define DEV_SFR_WIDTH_64(p) (((p) & USB_CAP1_SFR_WIDTH_MASK) == (0x3 << 4))
  745. /*
  746. * DMA Interface type
  747. * These field reflects type of DMA interface implemented:
  748. * 0x0 - OCP
  749. * 0x1 - AHB,
  750. * 0x2 - PLB
  751. * 0x3 - AXI
  752. * 0x4-0xF - reserved
  753. */
  754. #define USB_CAP1_DMA_TYPE_MASK GENMASK(11, 8)
  755. #define DEV_DMA_TYPE_OCP(p) (((p) & USB_CAP1_DMA_TYPE_MASK) == (0x0 << 8))
  756. #define DEV_DMA_TYPE_AHB(p) (((p) & USB_CAP1_DMA_TYPE_MASK) == (0x1 << 8))
  757. #define DEV_DMA_TYPE_PLB(p) (((p) & USB_CAP1_DMA_TYPE_MASK) == (0x2 << 8))
  758. #define DEV_DMA_TYPE_AXI(p) (((p) & USB_CAP1_DMA_TYPE_MASK) == (0x3 << 8))
  759. /*
  760. * DMA Interface width
  761. * These field reflects width of DMA interface implemented:
  762. * 0x0 - reserved,
  763. * 0x1 - reserved,
  764. * 0x2 - 32 bit interface
  765. * 0x3 - 64 bit interface
  766. * 0x4-0xF - reserved
  767. */
  768. #define USB_CAP1_DMA_WIDTH_MASK GENMASK(15, 12)
  769. #define DEV_DMA_WIDTH_32(p) (((p) & USB_CAP1_DMA_WIDTH_MASK) == (0x2 << 12))
  770. #define DEV_DMA_WIDTH_64(p) (((p) & USB_CAP1_DMA_WIDTH_MASK) == (0x3 << 12))
  771. /*
  772. * USB3 PHY Interface type
  773. * These field reflects type of USB3 PHY interface implemented:
  774. * 0x0 - USB PIPE,
  775. * 0x1 - RMMI,
  776. * 0x2-0xF - reserved
  777. */
  778. #define USB_CAP1_U3PHY_TYPE_MASK GENMASK(19, 16)
  779. #define DEV_U3PHY_PIPE(p) (((p) & USB_CAP1_U3PHY_TYPE_MASK) == (0x0 << 16))
  780. #define DEV_U3PHY_RMMI(p) (((p) & USB_CAP1_U3PHY_TYPE_MASK) == (0x1 << 16))
  781. /*
  782. * USB3 PHY Interface width
  783. * These field reflects width of USB3 PHY interface implemented:
  784. * 0x0 - 8 bit PIPE interface,
  785. * 0x1 - 16 bit PIPE interface,
  786. * 0x2 - 32 bit PIPE interface,
  787. * 0x3 - 64 bit PIPE interface
  788. * 0x4-0xF - reserved
  789. * Note: When SSIC interface is implemented this field shows the width of
  790. * internal PIPE interface. The RMMI interface is always 20bit wide.
  791. */
  792. #define USB_CAP1_U3PHY_WIDTH_MASK GENMASK(23, 20)
  793. #define DEV_U3PHY_WIDTH_8(p) \
  794. (((p) & USB_CAP1_U3PHY_WIDTH_MASK) == (0x0 << 20))
  795. #define DEV_U3PHY_WIDTH_16(p) \
  796. (((p) & USB_CAP1_U3PHY_WIDTH_MASK) == (0x1 << 16))
  797. #define DEV_U3PHY_WIDTH_32(p) \
  798. (((p) & USB_CAP1_U3PHY_WIDTH_MASK) == (0x2 << 20))
  799. #define DEV_U3PHY_WIDTH_64(p) \
  800. (((p) & USB_CAP1_U3PHY_WIDTH_MASK) == (0x3 << 16))
  801. /*
  802. * USB2 PHY Interface enable
  803. * These field informs if USB2 PHY interface is implemented:
  804. * 0x0 - interface NOT implemented,
  805. * 0x1 - interface implemented
  806. */
  807. #define USB_CAP1_U2PHY_EN(p) ((p) & BIT(24))
  808. /*
  809. * USB2 PHY Interface type
  810. * These field reflects type of USB2 PHY interface implemented:
  811. * 0x0 - UTMI,
  812. * 0x1 - ULPI
  813. */
  814. #define DEV_U2PHY_ULPI(p) ((p) & BIT(25))
  815. /*
  816. * USB2 PHY Interface width
  817. * These field reflects width of USB2 PHY interface implemented:
  818. * 0x0 - 8 bit interface,
  819. * 0x1 - 16 bit interface,
  820. * Note: The ULPI interface is always 8bit wide.
  821. */
  822. #define DEV_U2PHY_WIDTH_16(p) ((p) & BIT(26))
  823. /*
  824. * OTG Ready
  825. * 0x0 - pure device mode
  826. * 0x1 - some features and ports for CDNS USB OTG controller are implemented.
  827. */
  828. #define USB_CAP1_OTG_READY(p) ((p) & BIT(27))
  829. /*
  830. * When set, indicates that controller supports automatic internal TDL
  831. * calculation basing on the size provided in TRB (TRB[22:17]) for DMULT mode
  832. * Supported only for DEV_VER_V2 controller version.
  833. */
  834. #define USB_CAP1_TDL_FROM_TRB(p) ((p) & BIT(28))
  835. /* USB_CAP2- bitmasks */
  836. /*
  837. * The actual size of the connected On-chip RAM memory in kB:
  838. * - 0 means 256 kB (max supported mem size)
  839. * - value other than 0 reflects the mem size in kB
  840. */
  841. #define USB_CAP2_ACTUAL_MEM_SIZE(p) ((p) & GENMASK(7, 0))
  842. /*
  843. * Max supported mem size
  844. * These field reflects width of on-chip RAM address bus width,
  845. * which determines max supported mem size:
  846. * 0x0-0x7 - reserved,
  847. * 0x8 - support for 4kB mem,
  848. * 0x9 - support for 8kB mem,
  849. * 0xA - support for 16kB mem,
  850. * 0xB - support for 32kB mem,
  851. * 0xC - support for 64kB mem,
  852. * 0xD - support for 128kB mem,
  853. * 0xE - support for 256kB mem,
  854. * 0xF - reserved
  855. */
  856. #define USB_CAP2_MAX_MEM_SIZE(p) ((p) & GENMASK(11, 8))
  857. /* USB_CAP3- bitmasks */
  858. #define EP_IS_IMPLEMENTED(reg, index) ((reg) & (1 << (index)))
  859. /* USB_CAP4- bitmasks */
  860. #define EP_SUPPORT_ISO(reg, index) ((reg) & (1 << (index)))
  861. /* USB_CAP5- bitmasks */
  862. #define EP_SUPPORT_STREAM(reg, index) ((reg) & (1 << (index)))
  863. /* USB_CAP6- bitmasks */
  864. /* The USBSS-DEV Controller Internal build number. */
  865. #define GET_DEV_BASE_VERSION(p) ((p) & GENMASK(23, 0))
  866. /* The USBSS-DEV Controller version number. */
  867. #define GET_DEV_CUSTOM_VERSION(p) ((p) & GENMASK(31, 24))
  868. #define DEV_VER_NXP_V1 0x00024502
  869. #define DEV_VER_TI_V1 0x00024509
  870. #define DEV_VER_V2 0x0002450C
  871. #define DEV_VER_V3 0x0002450d
  872. /* DBG_LINK1- bitmasks */
  873. /*
  874. * LFPS_MIN_DET_U1_EXIT value This parameter configures the minimum
  875. * time required for decoding the received LFPS as an LFPS.U1_Exit.
  876. */
  877. #define DBG_LINK1_LFPS_MIN_DET_U1_EXIT(p) ((p) & GENMASK(7, 0))
  878. /*
  879. * LFPS_MIN_GEN_U1_EXIT value This parameter configures the minimum time for
  880. * phytxelecidle deassertion when LFPS.U1_Exit
  881. */
  882. #define DBG_LINK1_LFPS_MIN_GEN_U1_EXIT_MASK GENMASK(15, 8)
  883. #define DBG_LINK1_LFPS_MIN_GEN_U1_EXIT(p) (((p) << 8) & GENMASK(15, 8))
  884. /*
  885. * RXDET_BREAK_DIS value This parameter configures terminating the Far-end
  886. * Receiver termination detection sequence:
  887. * 0: it is possible that USBSS_DEV will terminate Farend receiver
  888. * termination detection sequence
  889. * 1: USBSS_DEV will not terminate Far-end receiver termination
  890. * detection sequence
  891. */
  892. #define DBG_LINK1_RXDET_BREAK_DIS BIT(16)
  893. /* LFPS_GEN_PING value This parameter configures the LFPS.Ping generation */
  894. #define DBG_LINK1_LFPS_GEN_PING(p) (((p) << 17) & GENMASK(21, 17))
  895. /*
  896. * Set the LFPS_MIN_DET_U1_EXIT value Writing '1' to this bit writes the
  897. * LFPS_MIN_DET_U1_EXIT field value to the device. This bit is automatically
  898. * cleared. Writing '0' has no effect
  899. */
  900. #define DBG_LINK1_LFPS_MIN_DET_U1_EXIT_SET BIT(24)
  901. /*
  902. * Set the LFPS_MIN_GEN_U1_EXIT value. Writing '1' to this bit writes the
  903. * LFPS_MIN_GEN_U1_EXIT field value to the device. This bit is automatically
  904. * cleared. Writing '0' has no effect
  905. */
  906. #define DBG_LINK1_LFPS_MIN_GEN_U1_EXIT_SET BIT(25)
  907. /*
  908. * Set the RXDET_BREAK_DIS value Writing '1' to this bit writes
  909. * the RXDET_BREAK_DIS field value to the device. This bit is automatically
  910. * cleared. Writing '0' has no effect
  911. */
  912. #define DBG_LINK1_RXDET_BREAK_DIS_SET BIT(26)
  913. /*
  914. * Set the LFPS_GEN_PING_SET value Writing '1' to this bit writes
  915. * the LFPS_GEN_PING field value to the device. This bit is automatically
  916. * cleared. Writing '0' has no effect."
  917. */
  918. #define DBG_LINK1_LFPS_GEN_PING_SET BIT(27)
  919. /* DMA_AXI_CTRL- bitmasks */
  920. /* The mawprot pin configuration. */
  921. #define DMA_AXI_CTRL_MARPROT(p) ((p) & GENMASK(2, 0))
  922. /* The marprot pin configuration. */
  923. #define DMA_AXI_CTRL_MAWPROT(p) (((p) & GENMASK(2, 0)) << 16)
  924. #define DMA_AXI_CTRL_NON_SECURE 0x02
  925. #define gadget_to_cdns3_device(g) (container_of(g, struct cdns3_device, gadget))
  926. #define ep_to_cdns3_ep(ep) (container_of(ep, struct cdns3_endpoint, endpoint))
  927. /*-------------------------------------------------------------------------*/
  928. /*
  929. * USBSS-DEV DMA interface.
  930. */
  931. #define TRBS_PER_SEGMENT 40
  932. #define ISO_MAX_INTERVAL 10
  933. #if TRBS_PER_SEGMENT < 2
  934. #error "Incorrect TRBS_PER_SEGMENT. Minimal Transfer Ring size is 2."
  935. #endif
  936. /*
  937. *Only for ISOC endpoints - maximum number of TRBs is calculated as
  938. * pow(2, bInterval-1) * number of usb requests. It is limitation made by
  939. * driver to save memory. Controller must prepare TRB for each ITP even
  940. * if bInterval > 1. It's the reason why driver needs so many TRBs for
  941. * isochronous endpoints.
  942. */
  943. #define TRBS_PER_ISOC_SEGMENT (ISO_MAX_INTERVAL * 8)
  944. #define GET_TRBS_PER_SEGMENT(ep_type) ((ep_type) == USB_ENDPOINT_XFER_ISOC ? \
  945. TRBS_PER_ISOC_SEGMENT : TRBS_PER_SEGMENT)
  946. /**
  947. * struct cdns3_trb - represent Transfer Descriptor block.
  948. * @buffer: pointer to buffer data
  949. * @length: length of data
  950. * @control: control flags.
  951. *
  952. * This structure describes transfer block serviced by DMA module.
  953. */
  954. struct cdns3_trb {
  955. __le32 buffer;
  956. __le32 length;
  957. __le32 control;
  958. };
  959. #define TRB_SIZE (sizeof(struct cdns3_trb))
  960. #define TRB_RING_SIZE (TRB_SIZE * TRBS_PER_SEGMENT)
  961. #define TRB_ISO_RING_SIZE (TRB_SIZE * TRBS_PER_ISOC_SEGMENT)
  962. #define TRB_CTRL_RING_SIZE (TRB_SIZE * 2)
  963. /* TRB bit mask */
  964. #define TRB_TYPE_BITMASK GENMASK(15, 10)
  965. #define TRB_TYPE(p) ((p) << 10)
  966. #define TRB_FIELD_TO_TYPE(p) (((p) & TRB_TYPE_BITMASK) >> 10)
  967. /* TRB type IDs */
  968. /* bulk, interrupt, isoc , and control data stage */
  969. #define TRB_NORMAL 1
  970. /* TRB for linking ring segments */
  971. #define TRB_LINK 6
  972. /* Cycle bit - indicates TRB ownership by driver or hw*/
  973. #define TRB_CYCLE BIT(0)
  974. /*
  975. * When set to '1', the device will toggle its interpretation of the Cycle bit
  976. */
  977. #define TRB_TOGGLE BIT(1)
  978. /*
  979. * Short Packet (SP). OUT EPs at DMULT=1 only. Indicates if the TRB was
  980. * processed while USB short packet was received. No more buffers defined by
  981. * the TD will be used. DMA will automatically advance to next TD.
  982. * - Shall be set to 0 by Software when putting TRB on the Transfer Ring
  983. * - Shall be set to 1 by Controller when Short Packet condition for this TRB
  984. * is detected independent if ISP is set or not.
  985. */
  986. #define TRB_SP BIT(1)
  987. /* Interrupt on short packet*/
  988. #define TRB_ISP BIT(2)
  989. /*Setting this bit enables FIFO DMA operation mode*/
  990. #define TRB_FIFO_MODE BIT(3)
  991. /* Set PCIe no snoop attribute */
  992. #define TRB_CHAIN BIT(4)
  993. /* Interrupt on completion */
  994. #define TRB_IOC BIT(5)
  995. /* stream ID bitmasks. */
  996. #define TRB_STREAM_ID_BITMASK GENMASK(31, 16)
  997. #define TRB_STREAM_ID(p) ((p) << 16)
  998. #define TRB_FIELD_TO_STREAMID(p) (((p) & TRB_STREAM_ID_BITMASK) >> 16)
  999. /* Size of TD expressed in USB packets for HS/FS mode. */
  1000. #define TRB_TDL_HS_SIZE(p) (((p) << 16) & GENMASK(31, 16))
  1001. #define TRB_TDL_HS_SIZE_GET(p) (((p) & GENMASK(31, 16)) >> 16)
  1002. /* transfer_len bitmasks. */
  1003. #define TRB_LEN(p) ((p) & GENMASK(16, 0))
  1004. /* Size of TD expressed in USB packets for SS mode. */
  1005. #define TRB_TDL_SS_SIZE(p) (((p) << 17) & GENMASK(23, 17))
  1006. #define TRB_TDL_SS_SIZE_GET(p) (((p) & GENMASK(23, 17)) >> 17)
  1007. /* transfer_len bitmasks - bits 31:24 */
  1008. #define TRB_BURST_LEN(p) (((p) << 24) & GENMASK(31, 24))
  1009. #define TRB_BURST_LEN_GET(p) (((p) & GENMASK(31, 24)) >> 24)
  1010. /* Data buffer pointer bitmasks*/
  1011. #define TRB_BUFFER(p) ((p) & GENMASK(31, 0))
  1012. /*-------------------------------------------------------------------------*/
  1013. /* Driver numeric constants */
  1014. /* Such declaration should be added to ch9.h */
  1015. #define USB_DEVICE_MAX_ADDRESS 127
  1016. /* Endpoint init values */
  1017. #define CDNS3_EP_MAX_PACKET_LIMIT 1024
  1018. #define CDNS3_EP_MAX_STREAMS 15
  1019. #define CDNS3_EP0_MAX_PACKET_LIMIT 512
  1020. /* All endpoints including EP0 */
  1021. #define CDNS3_ENDPOINTS_MAX_COUNT 32
  1022. #define CDNS3_EP_ZLP_BUF_SIZE 1024
  1023. #define CDNS3_EP_BUF_SIZE 2 /* KB */
  1024. #define CDNS3_EP_ISO_HS_MULT 3
  1025. #define CDNS3_EP_ISO_SS_BURST 3
  1026. #define CDNS3_MAX_NUM_DESCMISS_BUF 32
  1027. #define CDNS3_DESCMIS_BUF_SIZE 2048 /* Bytes */
  1028. #define CDNS3_WA2_NUM_BUFFERS 128
  1029. /*-------------------------------------------------------------------------*/
  1030. /* Used structs */
  1031. struct cdns3_device;
  1032. /**
  1033. * struct cdns3_endpoint - extended device side representation of USB endpoint.
  1034. * @endpoint: usb endpoint
  1035. * @pending_req_list: list of requests queuing on transfer ring.
  1036. * @deferred_req_list: list of requests waiting for queuing on transfer ring.
  1037. * @wa2_descmiss_req_list: list of requests internally allocated by driver.
  1038. * @trb_pool: transfer ring - array of transaction buffers
  1039. * @trb_pool_dma: dma address of transfer ring
  1040. * @cdns3_dev: device associated with this endpoint
  1041. * @name: a human readable name e.g. ep1out
  1042. * @flags: specify the current state of endpoint
  1043. * @descmis_req: internal transfer object used for getting data from on-chip
  1044. * buffer. It can happen only if function driver doesn't send usb_request
  1045. * object on time.
  1046. * @dir: endpoint direction
  1047. * @num: endpoint number (1 - 15)
  1048. * @type: set to bmAttributes & USB_ENDPOINT_XFERTYPE_MASK
  1049. * @interval: interval between packets used for ISOC endpoint.
  1050. * @free_trbs: number of free TRBs in transfer ring
  1051. * @num_trbs: number of all TRBs in transfer ring
  1052. * @pcs: producer cycle state
  1053. * @ccs: consumer cycle state
  1054. * @enqueue: enqueue index in transfer ring
  1055. * @dequeue: dequeue index in transfer ring
  1056. * @trb_burst_size: number of burst used in trb.
  1057. */
  1058. struct cdns3_endpoint {
  1059. struct usb_ep endpoint;
  1060. struct list_head pending_req_list;
  1061. struct list_head deferred_req_list;
  1062. struct list_head wa2_descmiss_req_list;
  1063. int wa2_counter;
  1064. struct cdns3_trb *trb_pool;
  1065. dma_addr_t trb_pool_dma;
  1066. struct cdns3_device *cdns3_dev;
  1067. char name[20];
  1068. #define EP_ENABLED BIT(0)
  1069. #define EP_STALLED BIT(1)
  1070. #define EP_STALL_PENDING BIT(2)
  1071. #define EP_WEDGE BIT(3)
  1072. #define EP_TRANSFER_STARTED BIT(4)
  1073. #define EP_UPDATE_EP_TRBADDR BIT(5)
  1074. #define EP_PENDING_REQUEST BIT(6)
  1075. #define EP_RING_FULL BIT(7)
  1076. #define EP_CLAIMED BIT(8)
  1077. #define EP_DEFERRED_DRDY BIT(9)
  1078. #define EP_QUIRK_ISO_OUT_EN BIT(10)
  1079. #define EP_QUIRK_END_TRANSFER BIT(11)
  1080. #define EP_QUIRK_EXTRA_BUF_DET BIT(12)
  1081. #define EP_QUIRK_EXTRA_BUF_EN BIT(13)
  1082. u32 flags;
  1083. struct cdns3_request *descmis_req;
  1084. u8 dir;
  1085. u8 num;
  1086. u8 type;
  1087. int interval;
  1088. int free_trbs;
  1089. int num_trbs;
  1090. u8 pcs;
  1091. u8 ccs;
  1092. int enqueue;
  1093. int dequeue;
  1094. u8 trb_burst_size;
  1095. unsigned int wa1_set:1;
  1096. struct cdns3_trb *wa1_trb;
  1097. unsigned int wa1_trb_index;
  1098. unsigned int wa1_cycle_bit:1;
  1099. };
  1100. /**
  1101. * struct cdns3_aligned_buf - represent aligned buffer used for DMA transfer
  1102. * @buf: aligned to 8 bytes data buffer. Buffer address used in
  1103. * TRB shall be aligned to 8.
  1104. * @dma: dma address
  1105. * @size: size of buffer
  1106. * @in_use: inform if this buffer is associated with usb_request
  1107. * @list: used to adding instance of this object to list
  1108. */
  1109. struct cdns3_aligned_buf {
  1110. void *buf;
  1111. dma_addr_t dma;
  1112. u32 size;
  1113. int in_use:1;
  1114. struct list_head list;
  1115. };
  1116. /**
  1117. * struct cdns3_request - extended device side representation of usb_request
  1118. * object .
  1119. * @request: generic usb_request object describing single I/O request.
  1120. * @priv_ep: extended representation of usb_ep object
  1121. * @trb: the first TRB association with this request
  1122. * @start_trb: number of the first TRB in transfer ring
  1123. * @end_trb: number of the last TRB in transfer ring
  1124. * @aligned_buf: object holds information about aligned buffer associated whit
  1125. * this endpoint
  1126. * @flags: flag specifying special usage of request
  1127. * @list: used by internally allocated request to add to wa2_descmiss_req_list.
  1128. */
  1129. struct cdns3_request {
  1130. struct usb_request request;
  1131. struct cdns3_endpoint *priv_ep;
  1132. struct cdns3_trb *trb;
  1133. int start_trb;
  1134. int end_trb;
  1135. struct cdns3_aligned_buf *aligned_buf;
  1136. #define REQUEST_PENDING BIT(0)
  1137. #define REQUEST_INTERNAL BIT(1)
  1138. #define REQUEST_INTERNAL_CH BIT(2)
  1139. #define REQUEST_ZLP BIT(3)
  1140. #define REQUEST_UNALIGNED BIT(4)
  1141. u32 flags;
  1142. struct list_head list;
  1143. };
  1144. #define to_cdns3_request(r) (container_of(r, struct cdns3_request, request))
  1145. /*Stages used during enumeration process.*/
  1146. #define CDNS3_SETUP_STAGE 0x0
  1147. #define CDNS3_DATA_STAGE 0x1
  1148. #define CDNS3_STATUS_STAGE 0x2
  1149. /**
  1150. * struct cdns3_device - represent USB device.
  1151. * @dev: pointer to device structure associated whit this controller
  1152. * @sysdev: pointer to the DMA capable device
  1153. * @gadget: device side representation of the peripheral controller
  1154. * @gadget_driver: pointer to the gadget driver
  1155. * @dev_ver: device controller version.
  1156. * @lock: for synchronizing
  1157. * @regs: base address for device side registers
  1158. * @setup_buf: used while processing usb control requests
  1159. * @setup_dma: dma address for setup_buf
  1160. * @zlp_buf - zlp buffer
  1161. * @ep0_stage: ep0 stage during enumeration process.
  1162. * @ep0_data_dir: direction for control transfer
  1163. * @eps: array of pointers to all endpoints with exclusion ep0
  1164. * @aligned_buf_list: list of aligned buffers internally allocated by driver
  1165. * @aligned_buf_wq: workqueue freeing no longer used aligned buf.
  1166. * @selected_ep: actually selected endpoint. It's used only to improve
  1167. * performance.
  1168. * @isoch_delay: value from Set Isoch Delay request. Only valid on SS/SSP.
  1169. * @u1_allowed: allow device transition to u1 state
  1170. * @u2_allowed: allow device transition to u2 state
  1171. * @is_selfpowered: device is self powered
  1172. * @setup_pending: setup packet is processing by gadget driver
  1173. * @hw_configured_flag: hardware endpoint configuration was set.
  1174. * @wake_up_flag: allow device to remote up the host
  1175. * @status_completion_no_call: indicate that driver is waiting for status s
  1176. * stage completion. It's used in deferred SET_CONFIGURATION request.
  1177. * @onchip_buffers: number of available on-chip buffers.
  1178. * @onchip_used_size: actual size of on-chip memory assigned to endpoints.
  1179. * @pending_status_wq: workqueue handling status stage for deferred requests.
  1180. * @pending_status_request: request for which status stage was deferred
  1181. */
  1182. struct cdns3_device {
  1183. struct udevice *dev;
  1184. struct udevice *sysdev;
  1185. struct usb_gadget gadget;
  1186. struct usb_gadget_driver *gadget_driver;
  1187. #define CDNS_REVISION_V0 0x00024501
  1188. #define CDNS_REVISION_V1 0x00024509
  1189. u32 dev_ver;
  1190. /* generic spin-lock for drivers */
  1191. spinlock_t lock;
  1192. struct cdns3_usb_regs __iomem *regs;
  1193. struct usb_ctrlrequest *setup_buf;
  1194. dma_addr_t setup_dma;
  1195. void *zlp_buf;
  1196. u8 ep0_stage;
  1197. int ep0_data_dir;
  1198. struct cdns3_endpoint *eps[CDNS3_ENDPOINTS_MAX_COUNT];
  1199. struct list_head aligned_buf_list;
  1200. struct work_struct aligned_buf_wq;
  1201. u32 selected_ep;
  1202. u16 isoch_delay;
  1203. unsigned wait_for_setup:1;
  1204. unsigned u1_allowed:1;
  1205. unsigned u2_allowed:1;
  1206. unsigned is_selfpowered:1;
  1207. unsigned setup_pending:1;
  1208. int hw_configured_flag:1;
  1209. int wake_up_flag:1;
  1210. unsigned status_completion_no_call:1;
  1211. int out_mem_is_allocated;
  1212. struct work_struct pending_status_wq;
  1213. struct usb_request *pending_status_request;
  1214. /*in KB */
  1215. u32 onchip_buffers;
  1216. u16 onchip_used_size;
  1217. };
  1218. void cdns3_set_register_bit(void __iomem *ptr, u32 mask);
  1219. dma_addr_t cdns3_trb_virt_to_dma(struct cdns3_endpoint *priv_ep,
  1220. struct cdns3_trb *trb);
  1221. enum usb_device_speed cdns3_get_speed(struct cdns3_device *priv_dev);
  1222. void cdns3_pending_setup_status_handler(struct work_struct *work);
  1223. void cdns3_hw_reset_eps_config(struct cdns3_device *priv_dev);
  1224. void cdns3_set_hw_configuration(struct cdns3_device *priv_dev);
  1225. void cdns3_select_ep(struct cdns3_device *priv_dev, u32 ep);
  1226. void cdns3_allow_enable_l1(struct cdns3_device *priv_dev, int enable);
  1227. struct usb_request *cdns3_next_request(struct list_head *list);
  1228. int cdns3_ep_run_transfer(struct cdns3_endpoint *priv_ep,
  1229. struct usb_request *request);
  1230. void cdns3_rearm_transfer(struct cdns3_endpoint *priv_ep, u8 rearm);
  1231. int cdns3_allocate_trb_pool(struct cdns3_endpoint *priv_ep);
  1232. u8 cdns3_ep_addr_to_index(u8 ep_addr);
  1233. int cdns3_gadget_ep_set_wedge(struct usb_ep *ep);
  1234. int cdns3_gadget_ep_set_halt(struct usb_ep *ep, int value);
  1235. void __cdns3_gadget_ep_set_halt(struct cdns3_endpoint *priv_ep);
  1236. int __cdns3_gadget_ep_clear_halt(struct cdns3_endpoint *priv_ep);
  1237. struct usb_request *cdns3_gadget_ep_alloc_request(struct usb_ep *ep,
  1238. gfp_t gfp_flags);
  1239. void cdns3_gadget_ep_free_request(struct usb_ep *ep,
  1240. struct usb_request *request);
  1241. int cdns3_gadget_ep_dequeue(struct usb_ep *ep, struct usb_request *request);
  1242. void cdns3_gadget_giveback(struct cdns3_endpoint *priv_ep,
  1243. struct cdns3_request *priv_req,
  1244. int status);
  1245. int cdns3_init_ep0(struct cdns3_device *priv_dev,
  1246. struct cdns3_endpoint *priv_ep);
  1247. void cdns3_ep0_config(struct cdns3_device *priv_dev);
  1248. void cdns3_ep_config(struct cdns3_endpoint *priv_ep);
  1249. void cdns3_check_ep0_interrupt_proceed(struct cdns3_device *priv_dev, int dir);
  1250. int __cdns3_gadget_wakeup(struct cdns3_device *priv_dev);
  1251. #endif /* __LINUX_CDNS3_GADGET */