starfive_ddr.h 1.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2022-2023 StarFive Technology Co., Ltd.
  4. * Author: yanhong <yanhong.wang@starfivetech.com>
  5. *
  6. */
  7. #ifndef __STARFIVE_DDR_H__
  8. #define __STARFIVE_DDR_H__
  9. #define JH7110_SYS_CRG 0x13020000
  10. #define SEC_CTRL_ADDR 0x1000
  11. #define PHY_BASE_ADDR 0x800
  12. #define PHY_AC_BASE_ADDR 0x1000
  13. #define DDR_BUS_MASK GENMASK(29, 24)
  14. #define DDR_AXI_MASK BIT(31)
  15. #define DDR_BUS_OFFSET 0xAC
  16. #define DDR_AXI_OFFSET 0xB0
  17. #define DDR_BUS_OSC_DIV2 0
  18. #define DDR_BUS_PLL1_DIV2 1
  19. #define DDR_BUS_PLL1_DIV4 2
  20. #define DDR_BUS_PLL1_DIV8 3
  21. #define DDR_AXI_DISABLE 0
  22. #define DDR_AXI_ENABLE 1
  23. #define OFFSET_SEL BIT(31)
  24. #define REG2G BIT(30)
  25. #define REG4G BIT(29)
  26. #define REG8G BIT(28)
  27. #define F_ADDSET BIT(2)
  28. #define F_SET BIT(1)
  29. #define F_CLRSET BIT(0)
  30. #define REGALL (REG2G | REG4G | REG8G)
  31. #define REGSETALL (F_SET | REGALL)
  32. #define REGCLRSETALL (F_CLRSET | REGALL)
  33. #define REGADDSETALL (F_ADDSET | REGALL)
  34. struct ddr_reg_cfg {
  35. u32 offset;
  36. u32 mask;
  37. u32 val;
  38. u32 flag;
  39. };
  40. enum ddr_size_t {
  41. DDR_SIZE_2G,
  42. DDR_SIZE_4G,
  43. DDR_SIZE_8G,
  44. DDR_SIZE_16G,
  45. };
  46. void ddr_phy_train(u32 *phyreg);
  47. void ddr_phy_util(u32 *phyreg);
  48. void ddr_phy_start(u32 *phyreg, enum ddr_size_t size);
  49. void ddrcsr_boot(u32 *csrreg, u32 *secreg, u32 *phyreg, enum ddr_size_t size);
  50. #define DDR_REG_TRIGGER(addr, mask, value) \
  51. out_le32((addr), (in_le32(addr) & (mask)) | (value))
  52. #define DDR_REG_SET(type, val) \
  53. clrsetbits_le32(JH7110_SYS_CRG + DDR_##type##_OFFSET, \
  54. DDR_##type##_MASK, \
  55. ((val) << __ffs(DDR_##type##_MASK)) & DDR_##type##_MASK)
  56. #endif /*__STARFIVE_DDR_H__*/