starfive_ddr.c 3.3 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2022-2023 StarFive Technology Co., Ltd.
  4. * Author: yanhong <yanhong.wang@starfivetech.com>
  5. *
  6. */
  7. #include <common.h>
  8. #include <asm/arch/clk.h>
  9. #include <dm.h>
  10. #include <fdtdec.h>
  11. #include <init.h>
  12. #include <ram.h>
  13. #include <reset.h>
  14. #include <syscon.h>
  15. #include <asm/io.h>
  16. #include <clk.h>
  17. #include <wait_bit.h>
  18. #include <linux/bitops.h>
  19. #include "starfive_ddr.h"
  20. DECLARE_GLOBAL_DATA_PTR;
  21. struct starfive_ddr_priv {
  22. struct udevice *dev;
  23. struct ram_info info;
  24. void __iomem *ctrlreg;
  25. void __iomem *phyreg;
  26. struct reset_ctl rst_axi;
  27. struct reset_ctl rst_osc;
  28. struct reset_ctl rst_apb;
  29. u32 fre;
  30. };
  31. static int starfive_ddr_setup(struct udevice *dev, struct starfive_ddr_priv *priv)
  32. {
  33. enum ddr_size_t size;
  34. switch (priv->info.size) {
  35. case 0x80000000:
  36. size = DDR_SIZE_2G;
  37. break;
  38. case 0x100000000:
  39. size = DDR_SIZE_4G;
  40. break;
  41. case 0x200000000:
  42. size = DDR_SIZE_8G;
  43. break;
  44. case 0x400000000:
  45. default:
  46. pr_err("unsupport size %lx\n", priv->info.size);
  47. return -1;
  48. }
  49. ddr_phy_train(priv->phyreg + (PHY_BASE_ADDR << 2));
  50. ddr_phy_util(priv->phyreg + (PHY_AC_BASE_ADDR << 2));
  51. ddr_phy_start(priv->phyreg, size);
  52. DDR_REG_SET(BUS, DDR_BUS_OSC_DIV2);
  53. ddrcsr_boot(priv->ctrlreg, priv->ctrlreg + SEC_CTRL_ADDR,
  54. priv->phyreg, size);
  55. return 0;
  56. }
  57. static int starfive_ddr_probe(struct udevice *dev)
  58. {
  59. struct starfive_ddr_priv *priv = dev_get_priv(dev);
  60. fdt_addr_t addr;
  61. u64 rate;
  62. int ret;
  63. priv->dev = dev;
  64. addr = dev_read_addr_index(dev, 0);
  65. priv->ctrlreg = (void __iomem *)addr;
  66. addr = dev_read_addr_index(dev, 1);
  67. priv->phyreg = (void __iomem *)addr;
  68. ret = dev_read_u32(dev, "clock-frequency", &priv->fre);
  69. if (ret)
  70. goto init_end;
  71. ret = reset_get_by_name(dev, "axi", &priv->rst_axi);
  72. if (ret)
  73. goto init_end;
  74. ret = reset_get_by_name(dev, "osc", &priv->rst_osc);
  75. if (ret)
  76. goto err_axi;
  77. ret = reset_get_by_name(dev, "apb", &priv->rst_apb);
  78. if (ret)
  79. goto err_osc;
  80. priv->info.base = gd->ram_base;
  81. priv->info.size = gd->ram_size;
  82. switch (priv->fre) {
  83. case 2133:
  84. rate = 1066000000;
  85. break;
  86. case 2800:
  87. rate = 1400000000;
  88. break;
  89. default:
  90. printk("Unknown DDR frequency %d\n", priv->fre);
  91. ret = -1;
  92. goto init_end;
  93. };
  94. DDR_REG_SET(BUS, DDR_BUS_OSC_DIV2);
  95. starfive_jh7110_pll_set_rate(PLL1, rate);
  96. udelay(100);
  97. DDR_REG_SET(BUS, DDR_BUS_PLL1_DIV2);
  98. reset_assert(&priv->rst_osc);
  99. reset_deassert(&priv->rst_osc);
  100. reset_assert(&priv->rst_apb);
  101. reset_deassert(&priv->rst_apb);
  102. reset_assert(&priv->rst_axi);
  103. reset_deassert(&priv->rst_axi);
  104. ret = starfive_ddr_setup(dev, priv);
  105. printf("DDR version: dc2e84f0.\n");
  106. goto init_end;
  107. err_osc:
  108. reset_free(&priv->rst_osc);
  109. err_axi:
  110. reset_free(&priv->rst_axi);
  111. pr_err("reset_get_by_name(axi) failed: %d", ret);
  112. init_end:
  113. return ret;
  114. }
  115. static int starfive_ddr_get_info(struct udevice *dev, struct ram_info *info)
  116. {
  117. struct starfive_ddr_priv *priv = dev_get_priv(dev);
  118. *info = priv->info;
  119. return 0;
  120. }
  121. static struct ram_ops starfive_ddr_ops = {
  122. .get_info = starfive_ddr_get_info,
  123. };
  124. static const struct udevice_id starfive_ddr_ids[] = {
  125. { .compatible = "starfive,jh7110-dmc" },
  126. { }
  127. };
  128. U_BOOT_DRIVER(starfive_ddr) = {
  129. .name = "starfive_ddr",
  130. .id = UCLASS_RAM,
  131. .of_match = starfive_ddr_ids,
  132. .ops = &starfive_ddr_ops,
  133. .probe = starfive_ddr_probe,
  134. .priv_auto = sizeof(struct starfive_ddr_priv),
  135. };