ddrphy_start.c 13 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2022-2023 StarFive Technology Co., Ltd.
  4. * Author: yanhong <yanhong.wang@starfivetech.com>
  5. *
  6. */
  7. #include <common.h>
  8. #include <asm/io.h>
  9. #include "starfive_ddr.h"
  10. static struct ddr_reg_cfg ddr_start_cfg[] = {
  11. {89, 0xffffff00, 0x00000051, (OFFSET_SEL | REGCLRSETALL)},
  12. {78, 0xfffffcff, 0x0, (OFFSET_SEL | REGCLRSETALL)},
  13. {345, 0xffffff00, 0x00000051, (OFFSET_SEL | REGCLRSETALL)},
  14. {334, 0xfffffcff, 0x0, (OFFSET_SEL | REGCLRSETALL)},
  15. {601, 0xffffff00, 0x00000051, (OFFSET_SEL | REGCLRSETALL)},
  16. {590, 0xfffffcff, 0x0, (OFFSET_SEL | REGCLRSETALL)},
  17. {857, 0xffffff00, 0x00000051, (OFFSET_SEL | REGCLRSETALL)},
  18. {846, 0xfffffcff, 0x0, (OFFSET_SEL | REGCLRSETALL)},
  19. {1793, 0xfffffeff, 0x0, (OFFSET_SEL | REGCLRSETALL)},
  20. {1793, 0xfffcffff, 0x0, (OFFSET_SEL | REGCLRSETALL)},
  21. {125, 0xfff0ffff, 0x00010000, (OFFSET_SEL | REGCLRSETALL)},
  22. {102, 0xfffffffc, 0x00000001, (OFFSET_SEL | REGCLRSETALL)},
  23. {105, 0xffffffe0, 0x00000001, (OFFSET_SEL | REGCLRSETALL)},
  24. {92, 0xfffffffe, 0x00000001, (OFFSET_SEL | REGCLRSETALL)},
  25. {94, 0xffffe0ff, 0x00000200, (OFFSET_SEL | REGCLRSETALL)},
  26. {96, 0xfffff0ff, 0x00000400, (OFFSET_SEL | REGCLRSETALL)},
  27. {89, 0xffffff00, 0x00000051, (OFFSET_SEL | REGCLRSETALL)},
  28. {381, 0xfff0ffff, 0x00010000, (OFFSET_SEL | REGCLRSETALL)},
  29. {358, 0xfffffffc, 0x00000001, (OFFSET_SEL | REGCLRSETALL)},
  30. {361, 0xffffffe0, 0x00000001, (OFFSET_SEL | REGCLRSETALL)},
  31. {348, 0xfffffffe, 0x00000001, (OFFSET_SEL | REGCLRSETALL)},
  32. {350, 0xffffe0ff, 0x00000200, (OFFSET_SEL | REGCLRSETALL)},
  33. {352, 0xfffff0ff, 0x00000400, (OFFSET_SEL | REGCLRSETALL)},
  34. {345, 0xffffff00, 0x00000051, (OFFSET_SEL | REGCLRSETALL)},
  35. {637, 0xfff0ffff, 0x00010000, (OFFSET_SEL | REGCLRSETALL)},
  36. {614, 0xfffffffc, 0x00000001, (OFFSET_SEL | REGCLRSETALL)},
  37. {617, 0xffffffe0, 0x00000001, (OFFSET_SEL | REGCLRSETALL)},
  38. {604, 0xfffffffe, 0x00000001, (OFFSET_SEL | REGCLRSETALL)},
  39. {606, 0xffffe0ff, 0x00000200, (OFFSET_SEL | REGCLRSETALL)},
  40. {608, 0xfffff0ff, 0x00000400, (OFFSET_SEL | REGCLRSETALL)},
  41. {601, 0xffffff00, 0x00000051, (OFFSET_SEL | REGCLRSETALL)},
  42. {893, 0xfff0ffff, 0x00010000, (OFFSET_SEL | REGCLRSETALL)},
  43. {870, 0xfffffffc, 0x00000001, (OFFSET_SEL | REGCLRSETALL)},
  44. {873, 0xffffffe0, 0x00000001, (OFFSET_SEL | REGCLRSETALL)},
  45. {860, 0xfffffffe, 0x00000001, (OFFSET_SEL | REGCLRSETALL)},
  46. {862, 0xffffe0ff, 0x00000200, (OFFSET_SEL | REGCLRSETALL)},
  47. {864, 0xfffff0ff, 0x00000400, (OFFSET_SEL | REGCLRSETALL)},
  48. {857, 0xffffff00, 0x00000051, (OFFSET_SEL | REGCLRSETALL)},
  49. {1895, 0xffffe000, 0x00001342, (OFFSET_SEL | REGCLRSETALL)},
  50. {1835, 0xfffff0ff, 0x00000200, (OFFSET_SEL | REGCLRSETALL)},
  51. {1793, 0xfffffeff, 0x00000100, (OFFSET_SEL | REGCLRSETALL)},
  52. {62, 0xfffffeff, 0x0, REGCLRSETALL},
  53. {66, 0xfffffeff, 0x0, REGCLRSETALL},
  54. {166, 0xffffff80, 0x00000001, REGCLRSETALL},
  55. {62, 0xfff0ffff, 0x00010000, REGCLRSETALL},
  56. {62, 0xf0ffffff, 0x01000000, REGCLRSETALL},
  57. {166, 0xffff80ff, 0x00000100, REGCLRSETALL},
  58. {179, 0xff80ffff, 0x00010000, REGCLRSETALL},
  59. {67, 0xffe0ffff, 0x00010000, REGCLRSETALL},
  60. {67, 0xe0ffffff, 0x01000000, REGCLRSETALL},
  61. {179, 0x80ffffff, 0x01000000, REGCLRSETALL},
  62. {166, 0xff80ffff, 0x00010000, REGCLRSETALL},
  63. {62, 0xfff0ffff, 0x00010000, REGCLRSETALL},
  64. {62, 0xf0ffffff, 0x01000000, REGCLRSETALL},
  65. {166, 0x80ffffff, 0x01000000, REGCLRSETALL},
  66. {182, 0xff80ffff, 0x00010000, REGCLRSETALL},
  67. {67, 0xffe0ffff, 0x00010000, REGCLRSETALL},
  68. {67, 0xe0ffffff, 0x01000000, REGCLRSETALL},
  69. {182, 0x80ffffff, 0x01000000, REGCLRSETALL},
  70. {167, 0xffffff80, 0x00000017, REGCLRSETALL},
  71. {62, 0xfff0ffff, 0x00010000, REGCLRSETALL},
  72. {62, 0xf0ffffff, 0x01000000, REGCLRSETALL},
  73. {167, 0xffff80ff, 0x00001700, REGCLRSETALL},
  74. {185, 0xff80ffff, 0x00200000, REGCLRSETALL},
  75. {67, 0xffe0ffff, 0x00010000, REGCLRSETALL},
  76. {67, 0xe0ffffff, 0x01000000, REGCLRSETALL},
  77. {185, 0x80ffffff, 0x20000000, REGCLRSETALL},
  78. {10, 0xffffffe0, 0x00000002, REGCLRSETALL},
  79. {0, 0xfffffffe, 0x00000001, REGCLRSETALL},
  80. {11, 0xfffffff0, 0x00000005, (F_CLRSET | REG2G)},
  81. {247, 0xffffffff, 0x00000008, REGCLRSETALL},
  82. {249, 0xffffffff, 0x00000800, REGCLRSETALL},
  83. {252, 0xffffffff, 0x00000008, REGCLRSETALL},
  84. {254, 0xffffffff, 0x00000800, REGCLRSETALL},
  85. {281, 0xffffffff, 0x33000000, REGCLRSETALL},
  86. {305, 0xffffffff, 0x33000000, REGCLRSETALL},
  87. {329, 0xffffffff, 0x33000000, REGCLRSETALL},
  88. {353, 0xffffffff, 0x33000000, REGCLRSETALL},
  89. {289, 0xffffffff, 0x36000000, (F_CLRSET | REG8G)},
  90. {313, 0xffffffff, 0x36000000, (F_CLRSET | REG8G)},
  91. {337, 0xffffffff, 0x36000000, (F_CLRSET | REG8G)},
  92. {361, 0xffffffff, 0x36000000, (F_CLRSET | REG8G)},
  93. {289, 0xffffffff, 0x66000000, (F_CLRSET | REG2G | REG4G)},
  94. {313, 0xffffffff, 0x66000000, (F_CLRSET | REG2G | REG4G)},
  95. {337, 0xffffffff, 0x66000000, (F_CLRSET | REG2G | REG4G)},
  96. {361, 0xffffffff, 0x66000000, (F_CLRSET | REG2G | REG4G)},
  97. {282, 0xffffffff, 0x00160000, REGCLRSETALL},
  98. {306, 0xffffffff, 0x00160000, REGCLRSETALL},
  99. {330, 0xffffffff, 0x00160000, REGCLRSETALL},
  100. {354, 0xffffffff, 0x00160000, REGCLRSETALL},
  101. {290, 0xffffffff, 0x00160000, REGCLRSETALL},
  102. {314, 0xffffffff, 0x00160000, REGCLRSETALL},
  103. {338, 0xffffffff, 0x00160000, REGCLRSETALL},
  104. {362, 0xffffffff, 0x00160000, REGCLRSETALL},
  105. {282, 0xffffff00, 0x17, REGCLRSETALL},
  106. {306, 0xffffff00, 0x17, REGCLRSETALL},
  107. {330, 0xffffff00, 0x17, REGCLRSETALL},
  108. {354, 0xffffff00, 0x17, REGCLRSETALL},
  109. {290, 0xffffff00, 0x17, REGCLRSETALL},
  110. {314, 0xffffff00, 0x17, REGCLRSETALL},
  111. {338, 0xffffff00, 0x17, REGCLRSETALL},
  112. {362, 0xffffff00, 0x17, REGCLRSETALL},
  113. {282, 0xffff00ff, 0x2000, REGCLRSETALL},
  114. {306, 0xffff00ff, 0x2000, REGCLRSETALL},
  115. {330, 0xffff00ff, 0x2000, REGCLRSETALL},
  116. {354, 0xffff00ff, 0x2000, REGCLRSETALL},
  117. {290, 0xffff00ff, 0x2000, REGCLRSETALL},
  118. {314, 0xffff00ff, 0x2000, REGCLRSETALL},
  119. {338, 0xffff00ff, 0x2000, REGCLRSETALL},
  120. {362, 0xffff00ff, 0x2000, REGCLRSETALL},
  121. {65, 0xffffffff, 0x00000100, (OFFSET_SEL | REGCLRSETALL)},
  122. {321, 0xffffffff, 0x00000100, (OFFSET_SEL | REGCLRSETALL)},
  123. {577, 0xffffffff, 0x00000100, (OFFSET_SEL | REGCLRSETALL)},
  124. {833, 0xffffffff, 0x00000100, (OFFSET_SEL | REGCLRSETALL)},
  125. {96, 0x0, 0x300, (OFFSET_SEL | REGADDSETALL)},
  126. {352, 0x0, 0x300, (OFFSET_SEL | REGADDSETALL)},
  127. {608, 0x0, 0x300, (OFFSET_SEL | REGADDSETALL)},
  128. {864, 0x0, 0x300, (OFFSET_SEL | REGADDSETALL)},
  129. {96, 0xff00ffff, 0x00120000, (OFFSET_SEL | REGCLRSETALL)},
  130. {352, 0xff00ffff, 0x00120000, (OFFSET_SEL | REGCLRSETALL)},
  131. {608, 0xff00ffff, 0x00120000, (OFFSET_SEL | REGCLRSETALL)},
  132. {864, 0xff00ffff, 0x00120000, (OFFSET_SEL | REGCLRSETALL)},
  133. {33, 0xffffff00, 0x0040, (OFFSET_SEL | REGCLRSETALL)},
  134. {289, 0xffffff00, 0x0040, (OFFSET_SEL | REGCLRSETALL)},
  135. {545, 0xffffff00, 0x0040, (OFFSET_SEL | REGCLRSETALL)},
  136. {801, 0xffffff00, 0x0040, (OFFSET_SEL | REGCLRSETALL)},
  137. {1038, 0xfcffffff, 0x03000000, (OFFSET_SEL | REGCLRSETALL)},
  138. {1294, 0xfcffffff, 0x03000000, (OFFSET_SEL | REGCLRSETALL)},
  139. {1550, 0xfcffffff, 0x03000000, (OFFSET_SEL | REGCLRSETALL)},
  140. {83, 0xffc0ffff, 0x70000, (OFFSET_SEL | REGCLRSETALL)},
  141. {339, 0xffc0ffff, 0x70000, (OFFSET_SEL | REGCLRSETALL)},
  142. {595, 0xffc0ffff, 0x70000, (OFFSET_SEL | REGCLRSETALL)},
  143. {851, 0xffc0ffff, 0x70000, (OFFSET_SEL | REGCLRSETALL)},
  144. {1062, 0xf800ffff, 0x70000, (OFFSET_SEL | REGCLRSETALL)},
  145. {1318, 0xf800ffff, 0x70000, (OFFSET_SEL | REGCLRSETALL)},
  146. {1574, 0xf800ffff, 0x70000, (OFFSET_SEL | REGCLRSETALL)},
  147. {1892, 0xfffc0000, 0x15547, (OFFSET_SEL | REGCLRSETALL)},
  148. {1893, 0xfffc0000, 0x7, (OFFSET_SEL | REGCLRSETALL)},
  149. {1852, 0xffffe000, 0x07a, (OFFSET_SEL | REGCLRSETALL)},
  150. {1853, 0xffffffff, 0x0100, (OFFSET_SEL | REGCLRSETALL)},
  151. {1822, 0xffffffff, 0xFF, (OFFSET_SEL | REGCLRSETALL)},
  152. {1896, 0xfffffc00, 0x03d5, (OFFSET_SEL | REGCLRSETALL)},
  153. {91, 0xfc00ffff, 0x03d50000, (OFFSET_SEL | REGCLRSETALL)},
  154. {347, 0xfc00ffff, 0x03d50000, (OFFSET_SEL | REGCLRSETALL)},
  155. {603, 0xfc00ffff, 0x03d50000, (OFFSET_SEL | REGCLRSETALL)},
  156. {859, 0xfc00ffff, 0x03d50000, (OFFSET_SEL | REGCLRSETALL)},
  157. {1912, 0x0, 0xcc3bfc7, (OFFSET_SEL | REGSETALL)},
  158. {1913, 0x0, 0xff8f, (OFFSET_SEL | REGSETALL)},
  159. {1914, 0x0, 0x33f07ff, (OFFSET_SEL | REGSETALL)},
  160. {1915, 0x0, 0xc3c37ff, (OFFSET_SEL | REGSETALL)},
  161. {1916, 0x0, 0x1fffff10, (OFFSET_SEL | REGSETALL)},
  162. {1917, 0x0, 0x230070, (OFFSET_SEL | REGSETALL)},
  163. {1918, 0x0, 0x3ff7ffff, (OFFSET_SEL | REG4G | REG2G | F_SET)},
  164. {1918, 0x0, 0x3ff7ffff, (OFFSET_SEL | REG8G | F_SET)},
  165. {1919, 0x0, 0xe10, (OFFSET_SEL | REGSETALL)},
  166. {1920, 0x0, 0x1fffffff, (OFFSET_SEL | REGSETALL)},
  167. {1921, 0x0, 0x188411, (OFFSET_SEL | REGSETALL)},
  168. {1922, 0x0, 0x1fffffff, (OFFSET_SEL | REGSETALL)},
  169. {1923, 0x0, 0x180400, (OFFSET_SEL | REGSETALL)},
  170. {1924, 0x0, 0x1fffffff, (OFFSET_SEL | REGSETALL)},
  171. {1925, 0x0, 0x180400, (OFFSET_SEL | REGSETALL)},
  172. {1926, 0x0, 0x1fffffcf, (OFFSET_SEL | REGSETALL)},
  173. {1927, 0x0, 0x188400, (OFFSET_SEL | REGSETALL)},
  174. {1928, 0x0, 0x1fffffff, (OFFSET_SEL | REGSETALL)},
  175. {1929, 0x0, 0x4188411, (OFFSET_SEL | REGSETALL)},
  176. {1837, 0x0, 0x24410, (OFFSET_SEL | REGSETALL)},
  177. {1840, 0x0, 0x24410, (OFFSET_SEL | REGSETALL)},
  178. {1842, 0x0, 0x2ffff, (OFFSET_SEL | REGSETALL)},
  179. {76, 0xff0000f8, 0x00ff8f07, (OFFSET_SEL | REGCLRSETALL)},
  180. {332, 0xff0000f8, 0x00ff8f07, (OFFSET_SEL | REGCLRSETALL)},
  181. {588, 0xff0000f8, 0x00ff8f07, (OFFSET_SEL | REGCLRSETALL)},
  182. {844, 0xff0000f8, 0x00ff8f07, (OFFSET_SEL | REGCLRSETALL)},
  183. {77, 0xffff0000, 0xff8f, (OFFSET_SEL | REGCLRSETALL)},
  184. {333, 0xffff0000, 0xff8f, (OFFSET_SEL | REGCLRSETALL)},
  185. {589, 0xffff0000, 0xff8f, (OFFSET_SEL | REGCLRSETALL)},
  186. {845, 0xffff0000, 0xff8f, (OFFSET_SEL | REGCLRSETALL)},
  187. {1062, 0xffffff00, 0xff, (OFFSET_SEL | REG4G | REG2G | F_CLRSET)},
  188. {1318, 0xffffff00, 0xff, (OFFSET_SEL | REG4G | REG2G | F_CLRSET)},
  189. {1574, 0xffffff00, 0xff, (OFFSET_SEL | REG4G | REG2G | F_CLRSET)},
  190. {1062, 0xffffff00, 0xfb, (OFFSET_SEL | REG8G | F_CLRSET)},
  191. {1318, 0xffffff00, 0xfb, (OFFSET_SEL | REG8G | F_CLRSET)},
  192. {1574, 0xffffff00, 0xfb, (OFFSET_SEL | REG8G | F_CLRSET)},
  193. {1028, 0xffffffff, 0x1000000, (OFFSET_SEL | REGCLRSETALL)},
  194. {1284, 0xffffffff, 0x1000000, (OFFSET_SEL | REGCLRSETALL)},
  195. {1540, 0xffffffff, 0x1000000, (OFFSET_SEL | REGCLRSETALL)},
  196. {1848, 0x0, 0x3cf07f8, (OFFSET_SEL | REGSETALL)},
  197. {1849, 0x0, 0x3f, (OFFSET_SEL | REGSETALL)},
  198. {1850, 0x0, 0x1fffff, (OFFSET_SEL | REGSETALL)},
  199. {1851, 0x0, 0x060000, (OFFSET_SEL | REGSETALL)},
  200. {130, 0x0000ffff, 0xffff0000, (OFFSET_SEL | REGCLRSETALL)},
  201. {386, 0x0000ffff, 0xffff0000, (OFFSET_SEL | REGCLRSETALL)},
  202. {642, 0x0000ffff, 0xffff0000, (OFFSET_SEL | REGCLRSETALL)},
  203. {898, 0x0000ffff, 0xffff0000, (OFFSET_SEL | REGCLRSETALL)},
  204. {131, 0xfffffff0, 0xf, (OFFSET_SEL | REGCLRSETALL)},
  205. {387, 0xfffffff0, 0xf, (OFFSET_SEL | REGCLRSETALL)},
  206. {643, 0xfffffff0, 0xf, (OFFSET_SEL | REGCLRSETALL)},
  207. {899, 0xfffffff0, 0xf, (OFFSET_SEL | REGCLRSETALL)},
  208. {29, 0xc0ffffff, 0x10000000, (OFFSET_SEL | REGCLRSETALL)},
  209. {285, 0xc0ffffff, 0x10000000, (OFFSET_SEL | REGCLRSETALL)},
  210. {541, 0xc0ffffff, 0x10000000, (OFFSET_SEL | REGCLRSETALL)},
  211. {797, 0xc0ffffff, 0x10000000, (OFFSET_SEL | REGCLRSETALL)},
  212. {30, 0xffffffff, 0x00080000, (OFFSET_SEL | REGCLRSETALL)},
  213. {286, 0xffffffff, 0x00080000, (OFFSET_SEL | REGCLRSETALL)},
  214. {542, 0xffffffff, 0x00080000, (OFFSET_SEL | REGCLRSETALL)},
  215. {798, 0xffffffff, 0x00080000, (OFFSET_SEL | REGCLRSETALL)},
  216. {31, 0xffffffc0, 0x00000010, (OFFSET_SEL | REGCLRSETALL)},
  217. {287, 0xffffffc0, 0x00000010, (OFFSET_SEL | REGCLRSETALL)},
  218. {543, 0xffffffc0, 0x00000010, (OFFSET_SEL | REGCLRSETALL)},
  219. {799, 0xffffffc0, 0x00000010, (OFFSET_SEL | REGCLRSETALL)},
  220. {1071, 0xfffffff0, 0x00000008, (OFFSET_SEL | REGCLRSETALL)},
  221. {1327, 0xfffffff0, 0x00000008, (OFFSET_SEL | REGCLRSETALL)},
  222. {1583, 0xfffffff0, 0x00000008, (OFFSET_SEL | REGCLRSETALL)},
  223. {1808, 0xfffffff0, 0x00000008, (OFFSET_SEL | REGCLRSETALL)},
  224. {1896, 0xfff0ffff, 0x00080000, (OFFSET_SEL | REGCLRSETALL)},
  225. };
  226. void ddr_reg_set(u32 *reg, struct ddr_reg_cfg *data,
  227. u32 len, u32 mask)
  228. {
  229. u32 *addr;
  230. u32 i;
  231. for (i = 0; i < len; i++) {
  232. if (!(data[i].flag & mask))
  233. continue;
  234. if (data[i].flag & OFFSET_SEL)
  235. addr = reg + PHY_AC_BASE_ADDR + data[i].offset;
  236. else
  237. addr = reg + PHY_BASE_ADDR + data[i].offset;
  238. if (data[i].flag & F_CLRSET)
  239. DDR_REG_TRIGGER(addr, data[i].mask, data[i].val);
  240. else if (data[i].flag & F_SET)
  241. out_le32(addr, data[i].val);
  242. else
  243. out_le32(addr, in_le32(addr) + data[i].val);
  244. }
  245. }
  246. void ddr_phy_start(u32 *phyreg, enum ddr_size_t size)
  247. {
  248. u32 len;
  249. u32 mask;
  250. switch (size) {
  251. case DDR_SIZE_2G:
  252. mask = REG2G;
  253. break;
  254. case DDR_SIZE_4G:
  255. mask = REG4G;
  256. break;
  257. case DDR_SIZE_8G:
  258. mask = REG8G;
  259. break;
  260. case DDR_SIZE_16G:
  261. default:
  262. return;
  263. };
  264. len = sizeof(ddr_start_cfg) / sizeof(struct ddr_reg_cfg);
  265. ddr_reg_set(phyreg, ddr_start_cfg, len, mask);
  266. out_le32(phyreg, 0x01);
  267. }