ddrcsr_boot.c 10 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2022-2023 StarFive Technology Co., Ltd.
  4. * Author: yanhong <yanhong.wang@starfivetech.com>
  5. *
  6. */
  7. #include <common.h>
  8. #include <asm/io.h>
  9. #include "starfive_ddr.h"
  10. #include <linux/delay.h>
  11. #define REGOFFSET(offset) ((offset) / 4)
  12. static struct ddr_reg_cfg ddr_csr_cfg[] = {
  13. {0x0, 0x0, 0x00000001, REGSETALL},
  14. {0xf00, 0x0, 0x40001030, (OFFSET_SEL | F_SET | REG4G | REG8G)},
  15. {0xf00, 0x0, 0x40001030, (OFFSET_SEL | F_SET | REG2G)},
  16. {0xf04, 0x0, 0x00000001, (OFFSET_SEL | F_SET | REG4G | REG8G)},
  17. {0xf04, 0x0, 0x00800001, (OFFSET_SEL | F_SET | REG2G)},
  18. {0xf10, 0x0, 0x00400000, (OFFSET_SEL | REGSETALL)},
  19. {0xf14, 0x0, 0x043fffff, (OFFSET_SEL | REGSETALL)},
  20. {0xf18, 0x0, 0x00000000, (OFFSET_SEL | REGSETALL)},
  21. {0xf30, 0x0, 0x1f000041, (OFFSET_SEL | REGSETALL)},
  22. {0xf34, 0x0, 0x1f000041, (OFFSET_SEL | F_SET | REG4G | REG8G)},
  23. {0x110, 0x0, 0xc0000001, (OFFSET_SEL | REGSETALL)},
  24. {0x114, 0x0, 0xffffffff, (OFFSET_SEL | REGSETALL)},
  25. {0x10c, 0x0, 0x00000505, REGSETALL},
  26. {0x11c, 0x0, 0x00000000, REGSETALL},
  27. {0x500, 0x0, 0x00000201, REGSETALL},
  28. {0x514, 0x0, 0x00000100, REGSETALL},
  29. {0x6a8, 0x0, 0x00040000, REGSETALL},
  30. {0xea8, 0x0, 0x00040000, REGSETALL},
  31. {0x504, 0x0, 0x40000000, REGSETALL}
  32. };
  33. static struct ddr_reg_cfg ddr_csr_cfg1[] = {
  34. {0x310, 0x0, 0x00020000, REGSETALL},
  35. {0x310, 0x0, 0x00020001, REGSETALL},
  36. {0x600, 0x0, 0x002e0176, REGSETALL},
  37. {0x604, 0x0, 0x002e0176, REGSETALL},
  38. {0x608, 0x0, 0x001700bb, REGSETALL},
  39. {0x60c, 0x0, 0x000b005d, REGSETALL},
  40. {0x610, 0x0, 0x0005002e, REGSETALL},
  41. {0x614, 0x0, 0x00020017, REGSETALL},
  42. {0x618, 0x0, 0x00020017, REGSETALL},
  43. {0x61c, 0x0, 0x00020017, REGSETALL},
  44. {0x678, 0x0, 0x00000019, REGSETALL},
  45. {0x100, 0x0, 0x000000f8, REGSETALL},
  46. {0x620, 0x0, 0x03030404, REGSETALL},
  47. {0x624, 0x0, 0x04030505, REGSETALL},
  48. {0x628, 0x0, 0x07030884, REGSETALL},
  49. {0x62c, 0x0, 0x13150401, REGSETALL},
  50. {0x630, 0x0, 0x17150604, REGSETALL},
  51. {0x634, 0x0, 0x00110000, REGSETALL},
  52. {0x638, 0x0, 0x200a0a08, REGSETALL},
  53. {0x63c, 0x0, 0x1730f803, REGSETALL},
  54. {0x640, 0x0, 0x000a0c00, REGSETALL},
  55. {0x644, 0x0, 0xa005000a, REGSETALL},
  56. {0x648, 0x0, 0x00000000, REGSETALL},
  57. {0x64c, 0x0, 0x00081306, REGSETALL},
  58. {0x650, 0x0, 0x04070304, REGSETALL},
  59. {0x654, 0x0, 0x00000404, REGSETALL},
  60. {0x658, 0x0, 0x00000060, REGSETALL},
  61. {0x65c, 0x0, 0x00030008, REGSETALL},
  62. {0x660, 0x0, 0x00000000, REGSETALL},
  63. {0x680, 0x0, 0x00000603, REGSETALL},
  64. {0x684, 0x0, 0x01000202, REGSETALL},
  65. {0x688, 0x0, 0x0413040d, REGSETALL},
  66. {0x68c, 0x0, 0x20002420, REGSETALL},
  67. {0x690, 0x0, 0x00140000, REGSETALL},
  68. {0x69c, 0x0, 0x01240074, REGSETALL},
  69. {0x6a0, 0x0, 0x00000000, REGSETALL},
  70. {0x6a4, 0x0, 0x20240c00, REGSETALL},
  71. {0x6a8, 0x0, 0x00040000, REGSETALL},
  72. {0x4, 0x0, 0x30010006, (F_SET | REG4G | REG8G)},
  73. {0x4, 0x0, 0x10010006, (F_SET | REG2G)},
  74. {0xc, 0x0, 0x00000002, REGSETALL},
  75. {0x4, 0x0, 0x30020000, (F_SET | REG4G | REG8G)},
  76. {0x4, 0x0, 0x10020000, (F_SET | REG2G)},
  77. {0xc, 0x0, 0x00000002, REGSETALL},
  78. {0x4, 0x0, 0x30030031, (F_SET | REG4G | REG8G)},
  79. {0x4, 0x0, 0x10030031, (F_SET | REG2G)},
  80. {0xc, 0x0, 0x00000002, REGSETALL},
  81. {0x4, 0x0, 0x300b0033, (F_SET | REG4G | REG8G)},
  82. {0x4, 0x0, 0x100b0033, (F_SET | REG2G)},
  83. {0xc, 0x0, 0x00000002, REGSETALL},
  84. {0x4, 0x0, 0x30160016, (F_SET | REG4G | REG8G)},
  85. {0x4, 0x0, 0x10160016, (F_SET | REG2G)},
  86. {0xc, 0x0, 0x00000002, REGSETALL},
  87. {0x10, 0x0, 0x00000010, REGSETALL},
  88. {0x14, 0x0, 0x00000001, REGSETALL},
  89. };
  90. static struct ddr_reg_cfg ddr_csr_cfg2[] = {
  91. {0xb8, 0xf0ffffff, 0x3000000, REGCLRSETALL},
  92. {0x84, 0xFEFFFFFF, 0x0, REGCLRSETALL},
  93. {0xb0, 0xFFFEFFFF, 0x0, REGCLRSETALL},
  94. {0xb0, 0xFEFFFFFF, 0x0, REGCLRSETALL},
  95. {0xb4, 0xffffffff, 0x1, REGCLRSETALL},
  96. {0x248, 0xffffffff, 0x3000000, REGCLRSETALL},
  97. {0x24c, 0xffffffff, 0x300, REGCLRSETALL},
  98. {0x24c, 0xffffffff, 0x3000000, REGCLRSETALL},
  99. {0xb0, 0xffffffff, 0x100, REGCLRSETALL},
  100. {0xb8, 0xFFF0FFFF, 0x30000, REGCLRSETALL},
  101. {0x84, 0xFFFEFFFF, 0x0, REGCLRSETALL},
  102. {0xac, 0xFFFEFFFF, 0x0, REGCLRSETALL},
  103. {0xac, 0xFEFFFFFF, 0x0, REGCLRSETALL},
  104. {0xb0, 0xffffffff, 0x1, REGCLRSETALL},
  105. {0x248, 0xffffffff, 0x30000, REGCLRSETALL},
  106. {0x24c, 0xffffffff, 0x3, REGCLRSETALL},
  107. {0x24c, 0xffffffff, 0x30000, REGCLRSETALL},
  108. {0x250, 0xffffffff, 0x3000000, REGCLRSETALL},
  109. {0x254, 0xffffffff, 0x3000000, REGCLRSETALL},
  110. {0x258, 0xffffffff, 0x3000000, REGCLRSETALL},
  111. {0xac, 0xffffffff, 0x100, REGCLRSETALL},
  112. {0x10c, 0xFFFFF0FF, 0x300, REGCLRSETALL},
  113. {0x110, 0xFFFFFEFF, 0x0, REGCLRSETALL},
  114. {0x11c, 0xFFFEFFFF, 0x0, REGCLRSETALL},
  115. {0x11c, 0xFEFFFFFF, 0x0, REGCLRSETALL},
  116. {0x120, 0xffffffff, 0x100, REGCLRSETALL},
  117. {0x2d0, 0xffffffff, 0x300, REGCLRSETALL},
  118. {0x2dc, 0xffffffff, 0x300, REGCLRSETALL},
  119. {0x2e8, 0xffffffff, 0x300, REGCLRSETALL},
  120. };
  121. static struct ddr_reg_cfg ddr_csr_cfg3[] = {
  122. {0x100, 0x0, 0x000000e0, REGSETALL},
  123. {0x620, 0x0, 0x04041417, REGSETALL},
  124. {0x624, 0x0, 0x09110609, REGSETALL},
  125. {0x628, 0x0, 0x442d0994, REGSETALL},
  126. {0x62c, 0x0, 0x271e102b, REGSETALL},
  127. {0x630, 0x0, 0x291b140a, REGSETALL},
  128. {0x634, 0x0, 0x001c0000, REGSETALL},
  129. {0x638, 0x0, 0x200f0f08, REGSETALL},
  130. {0x63c, 0x0, 0x29420a06, REGSETALL},
  131. {0x640, 0x0, 0x019e1fc1, REGSETALL},
  132. {0x644, 0x0, 0x10cb0196, REGSETALL},
  133. {0x648, 0x0, 0x00000000, REGSETALL},
  134. {0x64c, 0x0, 0x00082714, REGSETALL},
  135. {0x650, 0x0, 0x16442f0d, REGSETALL},
  136. {0x654, 0x0, 0x00001916, REGSETALL},
  137. {0x658, 0x0, 0x00000060, REGSETALL},
  138. {0x65c, 0x0, 0x00600020, REGSETALL},
  139. {0x660, 0x0, 0x00000000, REGSETALL},
  140. {0x680, 0x0, 0x0c00040f, REGSETALL},
  141. {0x684, 0x0, 0x03000604, REGSETALL},
  142. {0x688, 0x0, 0x0515040d, REGSETALL},
  143. {0x68c, 0x0, 0x20002c20, REGSETALL},
  144. {0x690, 0x0, 0x00140000, REGSETALL},
  145. {0x69c, 0x0, 0x01240074, REGSETALL},
  146. {0x6a0, 0x0, 0x00000000, REGSETALL},
  147. {0x6a4, 0x0, 0x202c0c00, REGSETALL},
  148. {0x6a8, 0x0, 0x00040000, REGSETALL},
  149. {0x4, 0x0, 0x30010036, (F_SET | REG4G | REG8G)},
  150. {0x4, 0x0, 0x10010036, (F_SET | REG2G)},
  151. {0xc, 0x0, 0x00000002, REGSETALL},
  152. {0x4, 0x0, 0x3002001b, (F_SET | REG4G | REG8G)},
  153. {0x4, 0x0, 0x10010036, (F_SET | REG2G)},
  154. {0xc, 0x0, 0x00000002, REGSETALL},
  155. {0x4, 0x0, 0x30030031, (F_SET | REG4G | REG8G)},
  156. {0x4, 0x0, 0x10030031, (F_SET | REG2G)},
  157. {0xc, 0x0, 0x00000002, REGSETALL},
  158. {0x4, 0x0, 0x300b0066, (F_SET | REG4G)},
  159. {0x4, 0x0, 0x300b0036, (F_SET | REG8G)},
  160. {0x4, 0x0, 0x100b0066, (F_SET | REG2G)},
  161. {0xc, 0x0, 0x00000002, REGSETALL},
  162. {0x4, 0x0, 0x30160016, (F_SET | REG4G | REG8G)},
  163. {0x4, 0x0, 0x10160016, (F_SET | REG2G)},
  164. {0xc, 0x0, 0x00000002, REGSETALL},
  165. {0x410, 0x0, 0x00101010, REGSETALL},
  166. {0x420, 0x0, 0x0c181006, REGSETALL},
  167. {0x424, 0x0, 0x20200820, REGSETALL},
  168. {0x428, 0x0, 0x80000020, REGSETALL},
  169. {0x0, 0x0, 0x00000001, REGSETALL},
  170. {0x108, 0x0, 0x00003000, REGSETALL},
  171. {0x704, 0x0, 0x00000007, REGSETALL | OFFSET_SEL},
  172. {0x330, 0x0, 0x09313fff, (F_SET | REG4G | REG8G)},
  173. {0x330, 0x0, 0x09311fff, (F_SET | REG2G)},
  174. {0x508, 0x0, 0x00000033, (F_SET | REG4G | REG8G)},
  175. {0x508, 0x0, 0x00000013, (F_SET | REG2G)},
  176. {0x324, 0x0, 0x00002000, REGSETALL},
  177. {0x104, 0x0, 0x90000000, REGSETALL},
  178. {0x510, 0x0, 0x00000100, REGSETALL},
  179. {0x514, 0x0, 0x00000000, REGSETALL},
  180. {0x700, 0x0, 0x00000003, REGSETALL | OFFSET_SEL},
  181. {0x514, 0x0, 0x00000600, REGSETALL},
  182. {0x20, 0x0, 0x00000001, REGSETALL},
  183. };
  184. static void ddr_csr_set(u32 *csrreg, u32 *secreg, struct ddr_reg_cfg *data,
  185. u32 len, u32 mask)
  186. {
  187. u32 *addr;
  188. u32 i;
  189. for (i = 0; i < len; i++) {
  190. if (!(data[i].flag & mask))
  191. continue;
  192. if (data[i].flag & OFFSET_SEL)
  193. addr = secreg + REGOFFSET(data[i].offset);
  194. else
  195. addr = csrreg + REGOFFSET(data[i].offset);
  196. if (data[i].flag & F_CLRSET)
  197. DDR_REG_TRIGGER(addr, data[i].mask, data[i].val);
  198. else
  199. out_le32(addr, data[i].val);
  200. }
  201. }
  202. void ddrcsr_boot(u32 *csrreg, u32 *secreg, u32 *phyreg, enum ddr_size_t size)
  203. {
  204. u32 len;
  205. u32 val;
  206. u32 mask;
  207. switch (size) {
  208. case DDR_SIZE_2G:
  209. mask = REG2G;
  210. break;
  211. case DDR_SIZE_4G:
  212. mask = REG4G;
  213. break;
  214. case DDR_SIZE_8G:
  215. mask = REG8G;
  216. break;
  217. case DDR_SIZE_16G:
  218. default:
  219. return;
  220. };
  221. len = sizeof(ddr_csr_cfg)/sizeof(struct ddr_reg_cfg);
  222. ddr_csr_set(csrreg, secreg, ddr_csr_cfg, len, mask);
  223. do {
  224. udelay(1);
  225. val = in_le32(csrreg + REGOFFSET(0x504));
  226. } while ((val & 0x80000000) != 0x80000000);
  227. out_le32(csrreg + REGOFFSET(0x504), 0x00000000);
  228. out_le32(csrreg + REGOFFSET(0x50c), 0x00000000);
  229. udelay(300);
  230. out_le32(csrreg + REGOFFSET(0x50c), 0x00000001);
  231. udelay(3000);
  232. switch (size) {
  233. case DDR_SIZE_2G:
  234. out_le32(csrreg + REGOFFSET(0x10), 0x0000001c);
  235. break;
  236. case DDR_SIZE_8G:
  237. case DDR_SIZE_4G:
  238. out_le32(csrreg + REGOFFSET(0x10), 0x0000003c);
  239. break;
  240. case DDR_SIZE_16G:
  241. default:
  242. break;
  243. };
  244. out_le32(csrreg + REGOFFSET(0x14), 0x00000001);
  245. udelay(4);
  246. len = sizeof(ddr_csr_cfg1)/sizeof(struct ddr_reg_cfg);
  247. ddr_csr_set(csrreg, secreg, ddr_csr_cfg1, len, mask);
  248. udelay(4);
  249. out_le32(csrreg + REGOFFSET(0x10), 0x00000011);
  250. out_le32(csrreg + REGOFFSET(0x14), 0x00000001);
  251. switch (size) {
  252. case DDR_SIZE_4G:
  253. case DDR_SIZE_8G:
  254. out_le32(csrreg + REGOFFSET(0x10), 0x00000020);
  255. out_le32(csrreg + REGOFFSET(0x14), 0x00000001);
  256. udelay(4);
  257. out_le32(csrreg + REGOFFSET(0x10), 0x00000021);
  258. out_le32(csrreg + REGOFFSET(0x14), 0x00000001);
  259. break;
  260. case DDR_SIZE_2G:
  261. case DDR_SIZE_16G:
  262. default:
  263. break;
  264. };
  265. out_le32(csrreg + REGOFFSET(0x514), 0x00000000);
  266. do {
  267. udelay(1);
  268. val = in_le32(csrreg + REGOFFSET(0x518));
  269. } while ((val & 0x2) != 0x2);
  270. val = in_le32(csrreg + REGOFFSET(0x518));
  271. while ((val & 0x2) != 0x0) {
  272. val = in_le32(phyreg + 1);
  273. if ((val & 0x20) == 0x20) {
  274. switch (val & 0x0000001f) {
  275. case 0: //ddrc_clock=12M
  276. DDR_REG_SET(BUS, DDR_BUS_OSC_DIV2);
  277. break;
  278. case 1: //ddrc_clock=200M
  279. DDR_REG_SET(BUS, DDR_BUS_PLL1_DIV8);
  280. break;
  281. case 2: //ddrc_clock=800M
  282. DDR_REG_SET(BUS, DDR_BUS_PLL1_DIV2);
  283. break;
  284. default:
  285. break;
  286. };
  287. out_le32((phyreg + 2), 0x1);
  288. do {
  289. udelay(2);
  290. val = in_le32(phyreg + 2);
  291. } while ((val & 0x00000001) != 0x00000000);
  292. }
  293. udelay(1);
  294. val = in_le32(csrreg + REGOFFSET(0x518));
  295. };
  296. val = in_le32(phyreg + 2048 + 83);
  297. val = in_le32(phyreg + 2048 + 84);
  298. out_le32((phyreg + 2048 + 84), val & 0xF8000000);
  299. len = sizeof(ddr_csr_cfg2)/sizeof(struct ddr_reg_cfg);
  300. ddr_csr_set((phyreg + PHY_BASE_ADDR), secreg, ddr_csr_cfg2, len, mask);
  301. len = sizeof(ddr_csr_cfg3)/sizeof(struct ddr_reg_cfg);
  302. ddr_csr_set(csrreg, secreg, ddr_csr_cfg3, len, mask);
  303. }